SIRegisterInfo.h revision 263508
1249259Sdim//===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief Interface definition for SIRegisterInfo 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim 16249259Sdim#ifndef SIREGISTERINFO_H_ 17249259Sdim#define SIREGISTERINFO_H_ 18249259Sdim 19249259Sdim#include "AMDGPURegisterInfo.h" 20249259Sdim 21249259Sdimnamespace llvm { 22249259Sdim 23249259Sdimclass AMDGPUTargetMachine; 24249259Sdim 25249259Sdimstruct SIRegisterInfo : public AMDGPURegisterInfo { 26249259Sdim AMDGPUTargetMachine &TM; 27249259Sdim 28263508Sdim SIRegisterInfo(AMDGPUTargetMachine &tm); 29249259Sdim 30249259Sdim virtual BitVector getReservedRegs(const MachineFunction &MF) const; 31249259Sdim 32249259Sdim virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC, 33249259Sdim MachineFunction &MF) const; 34249259Sdim 35249259Sdim /// \param RC is an AMDIL reg class. 36249259Sdim /// 37249259Sdim /// \returns the SI register class that is equivalent to \p RC. 38249259Sdim virtual const TargetRegisterClass * 39249259Sdim getISARegClass(const TargetRegisterClass *RC) const; 40249259Sdim 41249259Sdim /// \brief get the register class of the specified type to use in the 42249259Sdim /// CFGStructurizer 43249259Sdim virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const; 44263508Sdim 45263508Sdim virtual unsigned getHWRegIndex(unsigned Reg) const; 46263508Sdim 47263508Sdim /// \brief Return the 'base' register class for this register. 48263508Sdim /// e.g. SGPR0 => SReg_32, VGPR => VReg_32 SGPR0_SGPR1 -> SReg_32, etc. 49263508Sdim const TargetRegisterClass *getPhysRegClass(unsigned Reg) const; 50263508Sdim 51263508Sdim /// \returns true if this class contains only SGPR registers 52263508Sdim bool isSGPRClass(const TargetRegisterClass *RC) const; 53263508Sdim 54263508Sdim /// \returns true if this class contains VGPR registers. 55263508Sdim bool hasVGPRs(const TargetRegisterClass *RC) const; 56263508Sdim 57263508Sdim /// \returns A VGPR reg class with the same width as \p SRC 58263508Sdim const TargetRegisterClass *getEquivalentVGPRClass( 59263508Sdim const TargetRegisterClass *SRC) const; 60263508Sdim 61263508Sdim /// \returns The register class that is used for a sub-register of \p RC for 62263508Sdim /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will 63263508Sdim /// be returned. 64263508Sdim const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC, 65263508Sdim unsigned SubIdx) const; 66249259Sdim}; 67249259Sdim 68249259Sdim} // End namespace llvm 69249259Sdim 70249259Sdim#endif // SIREGISTERINFO_H_ 71