SIInstructions.td revision 285830
1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This file was originally auto-generated from a GPU register header file and 10// all the instruction definitions were originally commented out. Instructions 11// that are not yet supported remain commented out. 12//===----------------------------------------------------------------------===// 13 14class InterpSlots { 15int P0 = 2; 16int P10 = 0; 17int P20 = 1; 18} 19def INTERP : InterpSlots; 20 21def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23} 24 25def SendMsgImm : Operand<i32>; 26 27def isSI : Predicate<"Subtarget.getGeneration() " 28 ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; 29 30def WAIT_FLAG : InstFlag<"printWaitFlag">; 31 32let Predicates = [isSI] in { 33 34let neverHasSideEffects = 1 in { 35 36let isMoveImm = 1 in { 37def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 38def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 39def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 40def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 41} // End isMoveImm = 1 42 43def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 44def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 45def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 46def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 47def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 48def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 49} // End neverHasSideEffects = 1 50 51////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 52////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 53////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 54////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 55////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 56////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 57////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 58////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 59//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 60//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 61def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 62//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 63//def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 64//def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 65////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 66////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 67////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 68////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 69def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 70def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 71def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 72def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 73 74let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 75 76def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 77def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 78def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 79def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 80def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 81def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 82def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 83def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 84 85} // End hasSideEffects = 1 86 87def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 88def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 89def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 90def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 91def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 92def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 93//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 94def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 95def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 96def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 97def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 98def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 99 100/* 101This instruction is disabled for now until we can figure out how to teach 102the instruction selector to correctly use the S_CMP* vs V_CMP* 103instructions. 104 105When this instruction is enabled the code generator sometimes produces this 106invalid sequence: 107 108SCC = S_CMPK_EQ_I32 SGPR0, imm 109VCC = COPY SCC 110VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 111 112def S_CMPK_EQ_I32 : SOPK < 113 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 114 "S_CMPK_EQ_I32", 115 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 116>; 117*/ 118 119let isCompare = 1 in { 120def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 121def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 122def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 123def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 124def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 125def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 126def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 127def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 128def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 129def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 130def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 131} // End isCompare = 1 132 133let Defs = [SCC], isCommutable = 1 in { 134 def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 135 def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 136} 137 138//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 139def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 140def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 141def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 142//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 143//def EXP : EXP_ <0x00000000, "EXP", []>; 144 145let isCompare = 1 in { 146 147defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 148defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>; 149defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>; 150defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>; 151defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>; 152defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">; 153defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>; 154defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>; 155defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>; 156defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 157defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 158defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 159defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 160defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>; 161defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 162defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 163 164let hasSideEffects = 1, Defs = [EXEC] in { 165 166defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 167defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 168defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 169defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 170defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 171defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 172defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 173defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 174defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 175defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 176defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 177defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 178defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 179defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 180defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 181defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 182 183} // End hasSideEffects = 1, Defs = [EXEC] 184 185defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 186defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>; 187defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>; 188defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>; 189defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>; 190defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 191defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>; 192defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>; 193defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>; 194defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 195defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 196defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 197defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 198defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>; 199defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 200defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 201 202let hasSideEffects = 1, Defs = [EXEC] in { 203 204defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 205defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 206defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 207defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 208defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 209defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 210defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 211defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 212defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 213defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 214defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 215defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 216defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 217defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 218defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 219defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 220 221} // End hasSideEffects = 1, Defs = [EXEC] 222 223defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 224defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 225defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 226defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 227defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 228defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 229defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 230defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 231defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 232defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 233defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 234defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 235defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 236defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 237defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 238defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 239 240let hasSideEffects = 1, Defs = [EXEC] in { 241 242defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 243defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 244defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 245defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 246defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 247defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 248defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 249defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 250defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 251defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 252defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 253defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 254defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 255defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 256defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 257defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 258 259} // End hasSideEffects = 1, Defs = [EXEC] 260 261defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 262defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 263defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 264defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 265defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 266defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 267defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 268defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 269defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 270defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 271defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 272defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 273defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 274defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 275defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 276defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 277 278let hasSideEffects = 1, Defs = [EXEC] in { 279 280defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 281defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 282defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 283defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 284defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 285defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 286defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 287defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 288defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 289defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 290defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 291defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 292defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 293defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 294defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 295defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 296 297} // End hasSideEffects = 1, Defs = [EXEC] 298 299defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 300defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>; 301defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 302defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>; 303defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>; 304defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 305defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>; 306defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 307 308let hasSideEffects = 1, Defs = [EXEC] in { 309 310defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 311defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 312defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 313defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 314defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 315defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 316defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 317defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 318 319} // End hasSideEffects = 1, Defs = [EXEC] 320 321defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 322defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>; 323defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>; 324defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>; 325defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>; 326defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>; 327defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>; 328defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 329 330let hasSideEffects = 1, Defs = [EXEC] in { 331 332defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 333defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 334defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 335defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 336defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 337defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 338defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 339defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 340 341} // End hasSideEffects = 1, Defs = [EXEC] 342 343defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 344defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>; 345defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>; 346defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>; 347defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>; 348defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>; 349defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>; 350defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 351 352let hasSideEffects = 1, Defs = [EXEC] in { 353 354defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 355defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 356defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 357defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 358defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 359defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 360defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 361defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 362 363} // End hasSideEffects = 1, Defs = [EXEC] 364 365defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 366defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>; 367defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>; 368defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>; 369defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>; 370defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>; 371defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>; 372defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 373 374let hasSideEffects = 1, Defs = [EXEC] in { 375 376defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 377defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 378defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 379defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 380defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 381defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 382defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 383defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 384 385} // End hasSideEffects = 1, Defs = [EXEC] 386 387defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 388 389let hasSideEffects = 1, Defs = [EXEC] in { 390defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 391} // End hasSideEffects = 1, Defs = [EXEC] 392 393defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 394 395let hasSideEffects = 1, Defs = [EXEC] in { 396defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 397} // End hasSideEffects = 1, Defs = [EXEC] 398 399} // End isCompare = 1 400 401def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>; 402def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>; 403def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>; 404def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>; 405def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>; 406def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>; 407def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>; 408def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>; 409def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>; 410def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>; 411 412//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 413//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 414//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 415defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 416//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 417//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 418//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 419//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 420defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>; 421defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>; 422defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>; 423defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>; 424defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 425defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 426defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 427 428def BUFFER_STORE_BYTE : MUBUF_Store_Helper < 429 0x00000018, "BUFFER_STORE_BYTE", VReg_32 430>; 431 432def BUFFER_STORE_SHORT : MUBUF_Store_Helper < 433 0x0000001a, "BUFFER_STORE_SHORT", VReg_32 434>; 435 436def BUFFER_STORE_DWORD : MUBUF_Store_Helper < 437 0x0000001c, "BUFFER_STORE_DWORD", VReg_32 438>; 439 440def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 441 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64 442>; 443 444def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 445 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128 446>; 447//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 448//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 449//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 450//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 451//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 452//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 453//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 454//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 455//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 456//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 457//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 458//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 459//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 460//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 461//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 462//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 463//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 464//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 465//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 466//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 467//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 468//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 469//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 470//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 471//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 472//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 473//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 474//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 475//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 476//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 477//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 478//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 479//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 480//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 481//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 482//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 483//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 484//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 485//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 486def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 487def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>; 488def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>; 489def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>; 490def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>; 491 492let mayLoad = 1 in { 493 494// We are using the SGPR_32 and not the SReg_32 register class for 32-bit 495// SMRD instructions, because the SGPR_32 register class does not include M0 496// and writing to M0 from an SMRD instruction will hang the GPU. 497defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>; 498defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 499defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 500defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 501defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 502 503defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 504 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32 505>; 506 507defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 508 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 509>; 510 511defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 512 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 513>; 514 515defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 516 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 517>; 518 519defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 520 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 521>; 522 523} // mayLoad = 1 524 525//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 526//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 527defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">; 528defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">; 529//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 530//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 531//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 532//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 533//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 534//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 535//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 536//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 537defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">; 538//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 539//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 540//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 541//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 542//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 543//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 544//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 545//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 546//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 547//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 548//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 549//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 550//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 551//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 552//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 553//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 554//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 555defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">; 556//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 557defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">; 558//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 559defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">; 560defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">; 561//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 562//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 563defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">; 564//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 565defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">; 566//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 567defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">; 568defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">; 569//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 570//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 571//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 572//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 573//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 574//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 575//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 576//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 577//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 578//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 579//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 580//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 581//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 582//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 583//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 584//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 585//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 586//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 587//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 588//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 589//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 590//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 591//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 592//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 593//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 594//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 595//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 596//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 597//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 598//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 599//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 600//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 601//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 602//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 603//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 604//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 605//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 606//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 607//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 608//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 609//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 610//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 611//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 612//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 613//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 614//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 615//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 616//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 617//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 618//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 619//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 620//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 621//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 622//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 623 624 625let neverHasSideEffects = 1, isMoveImm = 1 in { 626defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 627} // End neverHasSideEffects = 1, isMoveImm = 1 628 629defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; 630defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64", 631 [(set i32:$dst, (fp_to_sint f64:$src0))] 632>; 633defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32", 634 [(set f64:$dst, (sint_to_fp i32:$src0))] 635>; 636defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 637 [(set f32:$dst, (sint_to_fp i32:$src0))] 638>; 639defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", 640 [(set f32:$dst, (uint_to_fp i32:$src0))] 641>; 642defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", 643 [(set i32:$dst, (fp_to_uint f32:$src0))] 644>; 645defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 646 [(set i32:$dst, (fp_to_sint f32:$src0))] 647>; 648defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 649////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 650//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 651//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 652//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 653//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 654defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64", 655 [(set f32:$dst, (fround f64:$src0))] 656>; 657defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32", 658 [(set f64:$dst, (fextend f32:$src0))] 659>; 660//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 661//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 662//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 663//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 664//defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 665//defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 666defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 667 [(set f32:$dst, (AMDGPUfract f32:$src0))] 668>; 669defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", 670 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))] 671>; 672defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 673 [(set f32:$dst, (fceil f32:$src0))] 674>; 675defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 676 [(set f32:$dst, (frint f32:$src0))] 677>; 678defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 679 [(set f32:$dst, (ffloor f32:$src0))] 680>; 681defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 682 [(set f32:$dst, (fexp2 f32:$src0))] 683>; 684defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 685defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 686 [(set f32:$dst, (flog2 f32:$src0))] 687>; 688defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 689defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 690defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 691 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 692>; 693defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 694defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 695defm V_RSQ_LEGACY_F32 : VOP1_32 < 696 0x0000002d, "V_RSQ_LEGACY_F32", 697 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))] 698>; 699defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 700defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", 701 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))] 702>; 703defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 704defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 705defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 706defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", 707 [(set f32:$dst, (fsqrt f32:$src0))] 708>; 709defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", 710 [(set f64:$dst, (fsqrt f64:$src0))] 711>; 712defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 713defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 714defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 715defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 716defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 717defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 718defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 719//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 720defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 721defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 722//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 723defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 724//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 725defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 726defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 727defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 728 729def V_INTERP_P1_F32 : VINTRP < 730 0x00000000, 731 (outs VReg_32:$dst), 732 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 733 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 734 []> { 735 let DisableEncoding = "$m0"; 736} 737 738def V_INTERP_P2_F32 : VINTRP < 739 0x00000001, 740 (outs VReg_32:$dst), 741 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 742 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 743 []> { 744 745 let Constraints = "$src0 = $dst"; 746 let DisableEncoding = "$src0,$m0"; 747 748} 749 750def V_INTERP_MOV_F32 : VINTRP < 751 0x00000002, 752 (outs VReg_32:$dst), 753 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 754 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 755 []> { 756 let DisableEncoding = "$m0"; 757} 758 759//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 760 761let isTerminator = 1 in { 762 763def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 764 [(IL_retflag)]> { 765 let SIMM16 = 0; 766 let isBarrier = 1; 767 let hasCtrlDep = 1; 768} 769 770let isBranch = 1 in { 771def S_BRANCH : SOPP < 772 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 773 [(br bb:$target)]> { 774 let isBarrier = 1; 775} 776 777let DisableEncoding = "$scc" in { 778def S_CBRANCH_SCC0 : SOPP < 779 0x00000004, (ins brtarget:$target, SCCReg:$scc), 780 "S_CBRANCH_SCC0 $target", [] 781>; 782def S_CBRANCH_SCC1 : SOPP < 783 0x00000005, (ins brtarget:$target, SCCReg:$scc), 784 "S_CBRANCH_SCC1 $target", 785 [] 786>; 787} // End DisableEncoding = "$scc" 788 789def S_CBRANCH_VCCZ : SOPP < 790 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 791 "S_CBRANCH_VCCZ $target", 792 [] 793>; 794def S_CBRANCH_VCCNZ : SOPP < 795 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 796 "S_CBRANCH_VCCNZ $target", 797 [] 798>; 799 800let DisableEncoding = "$exec" in { 801def S_CBRANCH_EXECZ : SOPP < 802 0x00000008, (ins brtarget:$target, EXECReg:$exec), 803 "S_CBRANCH_EXECZ $target", 804 [] 805>; 806def S_CBRANCH_EXECNZ : SOPP < 807 0x00000009, (ins brtarget:$target, EXECReg:$exec), 808 "S_CBRANCH_EXECNZ $target", 809 [] 810>; 811} // End DisableEncoding = "$exec" 812 813 814} // End isBranch = 1 815} // End isTerminator = 1 816 817let hasSideEffects = 1 in { 818def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", 819 [(int_AMDGPU_barrier_local)] 820> { 821 let SIMM16 = 0; 822 let isBarrier = 1; 823 let hasCtrlDep = 1; 824 let mayLoad = 1; 825 let mayStore = 1; 826} 827 828def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16", 829 [] 830>; 831//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 832//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 833//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 834 835let Uses = [EXEC] in { 836 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16, M0Reg:$m0), "S_SENDMSG $simm16", 837 [(int_SI_sendmsg imm:$simm16, M0Reg:$m0)] 838 > { 839 let DisableEncoding = "$m0"; 840 } 841} // End Uses = [EXEC] 842 843//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 844//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 845//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 846//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 847//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 848//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 849} // End hasSideEffects 850 851def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 852 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 853 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 854 [] 855>{ 856 let DisableEncoding = "$vcc"; 857} 858 859def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 860 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 861 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 862 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 863 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] 864>; 865 866//f32 pattern for V_CNDMASK_B32_e64 867def : Pat < 868 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 869 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 870>; 871 872def : Pat < 873 (i32 (trunc i64:$val)), 874 (EXTRACT_SUBREG $val, sub0) 875>; 876 877//use two V_CNDMASK_B32_e64 instructions for f64 878def : Pat < 879 (f64 (select i1:$src2, f64:$src1, f64:$src0)), 880 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 881 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub0), 882 (EXTRACT_SUBREG $src1, sub0), 883 $src2), sub0), 884 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub1), 885 (EXTRACT_SUBREG $src1, sub1), 886 $src2), sub1) 887>; 888 889defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; 890defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; 891 892let isCommutable = 1 in { 893defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 894 [(set f32:$dst, (fadd f32:$src0, f32:$src1))] 895>; 896 897defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 898 [(set f32:$dst, (fsub f32:$src0, f32:$src1))] 899>; 900defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; 901} // End isCommutable = 1 902 903defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 904 905let isCommutable = 1 in { 906 907defm V_MUL_LEGACY_F32 : VOP2_32 < 908 0x00000007, "V_MUL_LEGACY_F32", 909 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] 910>; 911 912defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 913 [(set f32:$dst, (fmul f32:$src0, f32:$src1))] 914>; 915 916 917defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", 918 [(set i32:$dst, (mul I24:$src0, I24:$src1))] 919>; 920//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 921defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", 922 [(set i32:$dst, (mul U24:$src0, U24:$src1))] 923>; 924//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 925 926 927defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 928 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] 929>; 930 931defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 932 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] 933>; 934 935defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 936defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 937defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", 938 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] 939>; 940defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", 941 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] 942>; 943defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", 944 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] 945>; 946defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", 947 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] 948>; 949 950defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", 951 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 952>; 953defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; 954 955defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", 956 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 957>; 958defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; 959 960let hasPostISelHook = 1 in { 961 962defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", 963 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 964>; 965 966} 967defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; 968 969defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", 970 [(set i32:$dst, (and i32:$src0, i32:$src1))] 971>; 972defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", 973 [(set i32:$dst, (or i32:$src0, i32:$src1))] 974>; 975defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", 976 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 977>; 978 979} // End isCommutable = 1 980 981defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; 982defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 983defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 984defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 985//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 986defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 987defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 988 989let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC 990// No patterns so that the scalar instructions are always selected. 991// The scalar versions will be replaced with vector when needed later. 992defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", [], VSrc_32>; 993defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", [], VSrc_32>; 994defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], VSrc_32, 995 "V_SUB_I32">; 996 997let Uses = [VCC] in { // Carry-in comes from VCC 998defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", [], VReg_32>; 999defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", [], VReg_32>; 1000defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], VReg_32, 1001 "V_SUBB_U32">; 1002} // End Uses = [VCC] 1003} // End isCommutable = 1, Defs = [VCC] 1004 1005defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 1006////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 1007////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 1008////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 1009defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 1010 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] 1011>; 1012////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 1013////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 1014def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 1015def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 1016def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 1017def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 1018def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 1019def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 1020def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 1021def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 1022def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 1023def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 1024def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 1025def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 1026////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 1027////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 1028////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 1029////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 1030//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 1031 1032let neverHasSideEffects = 1 in { 1033 1034def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 1035def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 1036def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", 1037 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))] 1038>; 1039def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", 1040 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))] 1041>; 1042 1043} // End neverHasSideEffects 1044def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 1045def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 1046def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 1047def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 1048def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; 1049def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; 1050def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; 1051defm : BFIPatterns <V_BFI_B32>; 1052def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", 1053 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))] 1054>; 1055def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", 1056 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 1057>; 1058//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 1059def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 1060def : ROTRPattern <V_ALIGNBIT_B32>; 1061 1062def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 1063def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 1064////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 1065////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 1066////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 1067////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 1068////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 1069////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 1070////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 1071////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 1072////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 1073//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 1074//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 1075//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 1076def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 1077////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 1078def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 1079def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 1080 1081def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64", 1082 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1083>; 1084def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64", 1085 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1086>; 1087def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64", 1088 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1089>; 1090 1091let isCommutable = 1 in { 1092 1093def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 1094def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 1095def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 1096def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 1097 1098} // isCommutable = 1 1099 1100def : Pat < 1101 (fadd f64:$src0, f64:$src1), 1102 (V_ADD_F64 $src0, $src1, (i64 0)) 1103>; 1104 1105def : Pat < 1106 (fmul f64:$src0, f64:$src1), 1107 (V_MUL_F64 $src0, $src1, (i64 0)) 1108>; 1109 1110def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 1111 1112let isCommutable = 1 in { 1113 1114def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 1115def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 1116def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 1117def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 1118 1119} // isCommutable = 1 1120 1121def : Pat < 1122 (mul i32:$src0, i32:$src1), 1123 (V_MUL_LO_I32 $src0, $src1, (i32 0)) 1124>; 1125 1126def : Pat < 1127 (mulhu i32:$src0, i32:$src1), 1128 (V_MUL_HI_U32 $src0, $src1, (i32 0)) 1129>; 1130 1131def : Pat < 1132 (mulhs i32:$src0, i32:$src1), 1133 (V_MUL_HI_I32 $src0, $src1, (i32 0)) 1134>; 1135 1136def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 1137def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 1138def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 1139def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 1140//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 1141//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 1142//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 1143def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 1144 1145let Defs = [SCC] in { // Carry out goes to SCC 1146let isCommutable = 1 in { 1147def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 1148def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", 1149 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))] 1150>; 1151} // End isCommutable = 1 1152 1153def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 1154def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", 1155 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))] 1156>; 1157 1158let Uses = [SCC] in { // Carry in comes from SCC 1159let isCommutable = 1 in { 1160def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", 1161 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 1162} // End isCommutable = 1 1163 1164def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", 1165 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 1166} // End Uses = [SCC] 1167} // End Defs = [SCC] 1168 1169def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; 1170def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; 1171def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; 1172def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; 1173 1174def S_CSELECT_B32 : SOP2 < 1175 0x0000000a, (outs SReg_32:$dst), 1176 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 1177 [] 1178>; 1179 1180def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 1181 1182def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; 1183 1184def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 1185 [(set i64:$dst, (and i64:$src0, i64:$src1))] 1186>; 1187 1188def : Pat < 1189 (i1 (and i1:$src0, i1:$src1)), 1190 (S_AND_B64 $src0, $src1) 1191>; 1192 1193def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; 1194def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; 1195def : Pat < 1196 (i1 (or i1:$src0, i1:$src1)), 1197 (S_OR_B64 $src0, $src1) 1198>; 1199def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; 1200def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", 1201 [(set i1:$dst, (xor i1:$src0, i1:$src1))] 1202>; 1203def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 1204def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 1205def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 1206def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 1207def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 1208def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 1209def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 1210def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 1211def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 1212def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 1213 1214// Use added complexity so these patterns are preferred to the VALU patterns. 1215let AddedComplexity = 1 in { 1216 1217def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", 1218 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 1219>; 1220def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64", 1221 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1222>; 1223def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", 1224 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 1225>; 1226def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64", 1227 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1228>; 1229def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", 1230 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 1231>; 1232def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64", 1233 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1234>; 1235 1236} // End AddedComplexity = 1 1237 1238def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 1239def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 1240def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 1241def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 1242def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 1243def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 1244def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 1245//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 1246def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 1247 1248let isCodeGenOnly = 1, isPseudo = 1 in { 1249 1250def LOAD_CONST : AMDGPUShaderInst < 1251 (outs GPRF32:$dst), 1252 (ins i32imm:$src), 1253 "LOAD_CONST $dst, $src", 1254 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 1255>; 1256 1257// SI pseudo instructions. These are used by the CFG structurizer pass 1258// and should be lowered to ISA instructions prior to codegen. 1259 1260let mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1261 Uses = [EXEC], Defs = [EXEC] in { 1262 1263let isBranch = 1, isTerminator = 1 in { 1264 1265def SI_IF : InstSI < 1266 (outs SReg_64:$dst), 1267 (ins SReg_64:$vcc, brtarget:$target), 1268 "SI_IF $dst, $vcc, $target", 1269 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))] 1270>; 1271 1272def SI_ELSE : InstSI < 1273 (outs SReg_64:$dst), 1274 (ins SReg_64:$src, brtarget:$target), 1275 "SI_ELSE $dst, $src, $target", 1276 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> { 1277 1278 let Constraints = "$src = $dst"; 1279} 1280 1281def SI_LOOP : InstSI < 1282 (outs), 1283 (ins SReg_64:$saved, brtarget:$target), 1284 "SI_LOOP $saved, $target", 1285 [(int_SI_loop i64:$saved, bb:$target)] 1286>; 1287 1288} // end isBranch = 1, isTerminator = 1 1289 1290def SI_BREAK : InstSI < 1291 (outs SReg_64:$dst), 1292 (ins SReg_64:$src), 1293 "SI_ELSE $dst, $src", 1294 [(set i64:$dst, (int_SI_break i64:$src))] 1295>; 1296 1297def SI_IF_BREAK : InstSI < 1298 (outs SReg_64:$dst), 1299 (ins SReg_64:$vcc, SReg_64:$src), 1300 "SI_IF_BREAK $dst, $vcc, $src", 1301 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] 1302>; 1303 1304def SI_ELSE_BREAK : InstSI < 1305 (outs SReg_64:$dst), 1306 (ins SReg_64:$src0, SReg_64:$src1), 1307 "SI_ELSE_BREAK $dst, $src0, $src1", 1308 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] 1309>; 1310 1311def SI_END_CF : InstSI < 1312 (outs), 1313 (ins SReg_64:$saved), 1314 "SI_END_CF $saved", 1315 [(int_SI_end_cf i64:$saved)] 1316>; 1317 1318def SI_KILL : InstSI < 1319 (outs), 1320 (ins VReg_32:$src), 1321 "SI_KIL $src", 1322 [(int_AMDGPU_kill f32:$src)] 1323>; 1324 1325} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1326 // Uses = [EXEC], Defs = [EXEC] 1327 1328let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1329 1330//defm SI_ : RegisterLoadStore <VReg_32, FRAMEri64, ADDRIndirect>; 1331 1332let UseNamedOperandTable = 1 in { 1333 1334def SI_RegisterLoad : AMDGPUShaderInst < 1335 (outs VReg_32:$dst, SReg_64:$temp), 1336 (ins FRAMEri64:$addr, i32imm:$chan), 1337 "", [] 1338> { 1339 let isRegisterLoad = 1; 1340 let mayLoad = 1; 1341} 1342 1343class SIRegStore<dag outs> : AMDGPUShaderInst < 1344 outs, 1345 (ins VReg_32:$val, FRAMEri64:$addr, i32imm:$chan), 1346 "", [] 1347> { 1348 let isRegisterStore = 1; 1349 let mayStore = 1; 1350} 1351 1352let usesCustomInserter = 1 in { 1353def SI_RegisterStorePseudo : SIRegStore<(outs)>; 1354} // End usesCustomInserter = 1 1355def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>; 1356 1357 1358} // End UseNamedOperandTable = 1 1359 1360def SI_INDIRECT_SRC : InstSI < 1361 (outs VReg_32:$dst, SReg_64:$temp), 1362 (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1363 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1364 [] 1365>; 1366 1367class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1368 (outs rc:$dst, SReg_64:$temp), 1369 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1370 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1371 [] 1372> { 1373 let Constraints = "$src = $dst"; 1374} 1375 1376def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>; 1377def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1378def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1379def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1380def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1381 1382} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1383 1384let usesCustomInserter = 1 in { 1385 1386// This pseudo instruction takes a pointer as input and outputs a resource 1387// constant that can be used with the ADDR64 MUBUF instructions. 1388def SI_ADDR64_RSRC : InstSI < 1389 (outs SReg_128:$srsrc), 1390 (ins SReg_64:$ptr), 1391 "", [] 1392>; 1393 1394def V_SUB_F64 : InstSI < 1395 (outs VReg_64:$dst), 1396 (ins VReg_64:$src0, VReg_64:$src1), 1397 "V_SUB_F64 $dst, $src0, $src1", 1398 [] 1399>; 1400 1401} // end usesCustomInserter 1402 1403} // end IsCodeGenOnly, isPseudo 1404 1405def : Pat< 1406 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), 1407 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) 1408>; 1409 1410def : Pat < 1411 (int_AMDGPU_kilp), 1412 (SI_KILL (V_MOV_B32_e32 0xbf800000)) 1413>; 1414 1415/* int_SI_vs_load_input */ 1416def : Pat< 1417 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr), 1418 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset, 0, 0, 0, 0) 1419>; 1420 1421/* int_SI_export */ 1422def : Pat < 1423 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1424 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 1425 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1426 $src0, $src1, $src2, $src3) 1427>; 1428 1429def : Pat < 1430 (f64 (fsub f64:$src0, f64:$src1)), 1431 (V_SUB_F64 $src0, $src1) 1432>; 1433 1434/********** ======================= **********/ 1435/********** Image sampling patterns **********/ 1436/********** ======================= **********/ 1437 1438/* SIsample for simple 1D texture lookup */ 1439def : Pat < 1440 (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm), 1441 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1442>; 1443 1444class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1445 (name vt:$addr, v32i8:$rsrc, i128:$sampler, imm), 1446 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1447>; 1448 1449class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1450 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_RECT), 1451 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1452>; 1453 1454class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1455 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_ARRAY), 1456 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1457>; 1458 1459class SampleShadowPattern<SDNode name, MIMG opcode, 1460 ValueType vt> : Pat < 1461 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW), 1462 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1463>; 1464 1465class SampleShadowArrayPattern<SDNode name, MIMG opcode, 1466 ValueType vt> : Pat < 1467 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW_ARRAY), 1468 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1469>; 1470 1471/* SIsample* for texture lookups consuming more address parameters */ 1472multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 1473 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 1474MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 1475 def : SamplePattern <SIsample, sample, addr_type>; 1476 def : SampleRectPattern <SIsample, sample, addr_type>; 1477 def : SampleArrayPattern <SIsample, sample, addr_type>; 1478 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 1479 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 1480 1481 def : SamplePattern <SIsamplel, sample_l, addr_type>; 1482 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 1483 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 1484 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 1485 1486 def : SamplePattern <SIsampleb, sample_b, addr_type>; 1487 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 1488 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 1489 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 1490 1491 def : SamplePattern <SIsampled, sample_d, addr_type>; 1492 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 1493 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 1494 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 1495} 1496 1497defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 1498 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 1499 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 1500 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 1501 v2i32>; 1502defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 1503 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 1504 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 1505 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 1506 v4i32>; 1507defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 1508 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 1509 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 1510 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 1511 v8i32>; 1512defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 1513 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 1514 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 1515 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 1516 v16i32>; 1517 1518/* int_SI_imageload for texture fetches consuming varying address parameters */ 1519class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1520 (name addr_type:$addr, v32i8:$rsrc, imm), 1521 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1522>; 1523 1524class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1525 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY), 1526 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1527>; 1528 1529class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1530 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA), 1531 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1532>; 1533 1534class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1535 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA), 1536 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1537>; 1538 1539multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> { 1540 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>; 1541 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>; 1542} 1543 1544multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> { 1545 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>; 1546 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>; 1547} 1548 1549defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>; 1550defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>; 1551 1552defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>; 1553defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>; 1554 1555/* Image resource information */ 1556def : Pat < 1557 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm), 1558 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1559>; 1560 1561def : Pat < 1562 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY), 1563 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1564>; 1565 1566def : Pat < 1567 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA), 1568 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1569>; 1570 1571/********** ============================================ **********/ 1572/********** Extraction, Insertion, Building and Casting **********/ 1573/********** ============================================ **********/ 1574 1575foreach Index = 0-2 in { 1576 def Extract_Element_v2i32_#Index : Extract_Element < 1577 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1578 >; 1579 def Insert_Element_v2i32_#Index : Insert_Element < 1580 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1581 >; 1582 1583 def Extract_Element_v2f32_#Index : Extract_Element < 1584 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1585 >; 1586 def Insert_Element_v2f32_#Index : Insert_Element < 1587 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1588 >; 1589} 1590 1591foreach Index = 0-3 in { 1592 def Extract_Element_v4i32_#Index : Extract_Element < 1593 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1594 >; 1595 def Insert_Element_v4i32_#Index : Insert_Element < 1596 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1597 >; 1598 1599 def Extract_Element_v4f32_#Index : Extract_Element < 1600 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1601 >; 1602 def Insert_Element_v4f32_#Index : Insert_Element < 1603 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1604 >; 1605} 1606 1607foreach Index = 0-7 in { 1608 def Extract_Element_v8i32_#Index : Extract_Element < 1609 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1610 >; 1611 def Insert_Element_v8i32_#Index : Insert_Element < 1612 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1613 >; 1614 1615 def Extract_Element_v8f32_#Index : Extract_Element < 1616 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1617 >; 1618 def Insert_Element_v8f32_#Index : Insert_Element < 1619 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1620 >; 1621} 1622 1623foreach Index = 0-15 in { 1624 def Extract_Element_v16i32_#Index : Extract_Element < 1625 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1626 >; 1627 def Insert_Element_v16i32_#Index : Insert_Element < 1628 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1629 >; 1630 1631 def Extract_Element_v16f32_#Index : Extract_Element < 1632 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1633 >; 1634 def Insert_Element_v16f32_#Index : Insert_Element < 1635 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1636 >; 1637} 1638 1639def : BitConvert <i32, f32, SReg_32>; 1640def : BitConvert <i32, f32, VReg_32>; 1641 1642def : BitConvert <f32, i32, SReg_32>; 1643def : BitConvert <f32, i32, VReg_32>; 1644 1645def : BitConvert <i64, f64, VReg_64>; 1646 1647def : BitConvert <f64, i64, VReg_64>; 1648 1649def : BitConvert <v2f32, v2i32, VReg_64>; 1650def : BitConvert <v2i32, v2f32, VReg_64>; 1651def : BitConvert <v2i32, i64, VReg_64>; 1652 1653def : BitConvert <v4f32, v4i32, VReg_128>; 1654def : BitConvert <v4i32, v4f32, VReg_128>; 1655def : BitConvert <v4i32, i128, VReg_128>; 1656def : BitConvert <i128, v4i32, VReg_128>; 1657 1658def : BitConvert <v8i32, v32i8, SReg_256>; 1659def : BitConvert <v32i8, v8i32, SReg_256>; 1660def : BitConvert <v8i32, v32i8, VReg_256>; 1661def : BitConvert <v32i8, v8i32, VReg_256>; 1662 1663/********** =================== **********/ 1664/********** Src & Dst modifiers **********/ 1665/********** =================== **********/ 1666 1667def : Pat < 1668 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1669 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1670 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1671>; 1672 1673/********** ================================ **********/ 1674/********** Floating point absolute/negative **********/ 1675/********** ================================ **********/ 1676 1677// Manipulate the sign bit directly, as e.g. using the source negation modifier 1678// in V_ADD_F32_e64 $src, 0, [...] does not result in -0.0 for $src == +0.0, 1679// breaking the piglit *s-floatBitsToInt-neg* tests 1680 1681// TODO: Look into not implementing isFNegFree/isFAbsFree for SI, and possibly 1682// removing these patterns 1683 1684def : Pat < 1685 (fneg (fabs f32:$src)), 1686 (V_OR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Set sign bit */ 1687>; 1688 1689def : Pat < 1690 (fabs f32:$src), 1691 (V_AND_B32_e32 $src, (V_MOV_B32_e32 0x7fffffff)) /* Clear sign bit */ 1692>; 1693 1694def : Pat < 1695 (fneg f32:$src), 1696 (V_XOR_B32_e32 $src, (V_MOV_B32_e32 0x80000000)) /* Toggle sign bit */ 1697>; 1698 1699/********** ================== **********/ 1700/********** Immediate Patterns **********/ 1701/********** ================== **********/ 1702 1703def : Pat < 1704 (SGPRImm<(i32 imm)>:$imm), 1705 (S_MOV_B32 imm:$imm) 1706>; 1707 1708def : Pat < 1709 (SGPRImm<(f32 fpimm)>:$imm), 1710 (S_MOV_B32 fpimm:$imm) 1711>; 1712 1713def : Pat < 1714 (i32 imm:$imm), 1715 (V_MOV_B32_e32 imm:$imm) 1716>; 1717 1718def : Pat < 1719 (f32 fpimm:$imm), 1720 (V_MOV_B32_e32 fpimm:$imm) 1721>; 1722 1723def : Pat < 1724 (i1 imm:$imm), 1725 (S_MOV_B64 imm:$imm) 1726>; 1727 1728def : Pat < 1729 (i64 InlineImm<i64>:$imm), 1730 (S_MOV_B64 InlineImm<i64>:$imm) 1731>; 1732 1733// i64 immediates aren't supported in hardware, split it into two 32bit values 1734def : Pat < 1735 (i64 imm:$imm), 1736 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1737 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0), 1738 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1) 1739>; 1740 1741def : Pat < 1742 (f64 fpimm:$imm), 1743 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 1744 (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0), 1745 (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1) 1746>; 1747 1748/********** ===================== **********/ 1749/********** Interpolation Paterns **********/ 1750/********** ===================== **********/ 1751 1752def : Pat < 1753 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params), 1754 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params) 1755>; 1756 1757def : Pat < 1758 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij), 1759 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0), 1760 imm:$attr_chan, imm:$attr, i32:$params), 1761 (EXTRACT_SUBREG $ij, sub1), 1762 imm:$attr_chan, imm:$attr, $params) 1763>; 1764 1765/********** ================== **********/ 1766/********** Intrinsic Patterns **********/ 1767/********** ================== **********/ 1768 1769/* llvm.AMDGPU.pow */ 1770def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 1771 1772def : Pat < 1773 (int_AMDGPU_div f32:$src0, f32:$src1), 1774 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) 1775>; 1776 1777def : Pat< 1778 (fdiv f32:$src0, f32:$src1), 1779 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1)) 1780>; 1781 1782def : Pat< 1783 (fdiv f64:$src0, f64:$src1), 1784 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0)) 1785>; 1786 1787def : Pat < 1788 (fcos f32:$src0), 1789 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1790>; 1791 1792def : Pat < 1793 (fsin f32:$src0), 1794 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1795>; 1796 1797def : Pat < 1798 (int_AMDGPU_cube v4f32:$src), 1799 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 1800 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), 1801 (EXTRACT_SUBREG $src, sub1), 1802 (EXTRACT_SUBREG $src, sub2)), 1803 sub0), 1804 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), 1805 (EXTRACT_SUBREG $src, sub1), 1806 (EXTRACT_SUBREG $src, sub2)), 1807 sub1), 1808 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), 1809 (EXTRACT_SUBREG $src, sub1), 1810 (EXTRACT_SUBREG $src, sub2)), 1811 sub2), 1812 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), 1813 (EXTRACT_SUBREG $src, sub1), 1814 (EXTRACT_SUBREG $src, sub2)), 1815 sub3) 1816>; 1817 1818def : Pat < 1819 (i32 (sext i1:$src0)), 1820 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 1821>; 1822 1823def : Pat < 1824 (i32 (zext i1:$src0)), 1825 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src0) 1826>; 1827 1828// 1. Offset as 8bit DWORD immediate 1829def : Pat < 1830 (SIload_constant i128:$sbase, IMM8bitDWORD:$offset), 1831 (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset) 1832>; 1833 1834// 2. Offset loaded in an 32bit SGPR 1835def : Pat < 1836 (SIload_constant i128:$sbase, imm:$offset), 1837 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) 1838>; 1839 1840// 3. Offset in an 32Bit VGPR 1841def : Pat < 1842 (SIload_constant i128:$sbase, i32:$voff), 1843 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff, 0, 0, 0, 0) 1844>; 1845 1846// The multiplication scales from [0,1] to the unsigned integer range 1847def : Pat < 1848 (AMDGPUurecip i32:$src0), 1849 (V_CVT_U32_F32_e32 1850 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 1851 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 1852>; 1853 1854def : Pat < 1855 (int_SI_tid), 1856 (V_MBCNT_HI_U32_B32_e32 0xffffffff, 1857 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0)) 1858>; 1859 1860/********** ================== **********/ 1861/********** VOP3 Patterns **********/ 1862/********** ================== **********/ 1863 1864def : Pat < 1865 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)), 1866 (V_MAD_F32 $src0, $src1, $src2) 1867>; 1868 1869/********** ======================= **********/ 1870/********** Load/Store Patterns **********/ 1871/********** ======================= **********/ 1872 1873class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat < 1874 (frag i32:$src0), 1875 (vt (inst 0, $src0, $src0, $src0, 0, 0)) 1876>; 1877 1878def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>; 1879def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>; 1880def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>; 1881def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>; 1882def : DSReadPat <DS_READ_B32, i32, local_load>; 1883def : Pat < 1884 (local_load i32:$src0), 1885 (i32 (DS_READ_B32 0, $src0, $src0, $src0, 0, 0)) 1886>; 1887 1888class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat < 1889 (frag i32:$src1, i32:$src0), 1890 (inst 0, $src0, $src1, $src1, 0, 0) 1891>; 1892 1893def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>; 1894def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>; 1895def : DSWritePat <DS_WRITE_B32, i32, local_store>; 1896 1897def : Pat <(atomic_load_add_local i32:$ptr, i32:$val), 1898 (DS_ADD_U32_RTN 0, $ptr, $val, 0, 0)>; 1899 1900def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val), 1901 (DS_SUB_U32_RTN 0, $ptr, $val, 0, 0)>; 1902 1903/********** ================== **********/ 1904/********** SMRD Patterns **********/ 1905/********** ================== **********/ 1906 1907multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1908 1909 // 1. Offset as 8bit DWORD immediate 1910 def : Pat < 1911 (constant_load (SIadd64bit32bit i64:$sbase, IMM8bitDWORD:$offset)), 1912 (vt (Instr_IMM $sbase, IMM8bitDWORD:$offset)) 1913 >; 1914 1915 // 2. Offset loaded in an 32bit SGPR 1916 def : Pat < 1917 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)), 1918 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset))) 1919 >; 1920 1921 // 3. No offset at all 1922 def : Pat < 1923 (constant_load i64:$sbase), 1924 (vt (Instr_IMM $sbase, 0)) 1925 >; 1926} 1927 1928defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1929defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1930defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>; 1931defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>; 1932defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, i128>; 1933defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>; 1934defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1935defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>; 1936defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>; 1937 1938//===----------------------------------------------------------------------===// 1939// MUBUF Patterns 1940//===----------------------------------------------------------------------===// 1941 1942multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 1943 PatFrag global_ld, PatFrag constant_ld> { 1944 def : Pat < 1945 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))), 1946 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) 1947 >; 1948 1949 def : Pat < 1950 (vt (global_ld i64:$ptr)), 1951 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1952 >; 1953 1954 def : Pat < 1955 (vt (global_ld (add i64:$ptr, i64:$offset))), 1956 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1957 >; 1958 1959 def : Pat < 1960 (vt (constant_ld (add i64:$ptr, i64:$offset))), 1961 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1962 >; 1963} 1964 1965defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, 1966 sextloadi8_global, sextloadi8_constant>; 1967defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, 1968 az_extloadi8_global, az_extloadi8_constant>; 1969defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, 1970 sextloadi16_global, sextloadi16_constant>; 1971defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, 1972 az_extloadi16_global, az_extloadi16_constant>; 1973defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, 1974 global_load, constant_load>; 1975defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1976 global_load, constant_load>; 1977defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1978 az_extloadi32_global, az_extloadi32_constant>; 1979defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, 1980 global_load, constant_load>; 1981defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, 1982 global_load, constant_load>; 1983 1984multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> { 1985 1986 def : Pat < 1987 (st vt:$value, i64:$ptr), 1988 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1989 >; 1990 1991 def : Pat < 1992 (st vt:$value, (add i64:$ptr, i64:$offset)), 1993 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0) 1994 >; 1995} 1996 1997defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>; 1998defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>; 1999defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>; 2000defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>; 2001defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>; 2002defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>; 2003 2004// BUFFER_LOAD_DWORD*, addr64=0 2005multiclass MUBUF_Load_Dword <ValueType vt, MUBUF offset, MUBUF offen, MUBUF idxen, 2006 MUBUF bothen> { 2007 2008 def : Pat < 2009 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset, 2010 imm:$offset, 0, 0, imm:$glc, imm:$slc, 2011 imm:$tfe)), 2012 (offset $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc), 2013 (as_i1imm $slc), (as_i1imm $tfe)) 2014 >; 2015 2016 def : Pat < 2017 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset, 2018 imm, 1, 0, imm:$glc, imm:$slc, 2019 imm:$tfe)), 2020 (offen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc), 2021 (as_i1imm $tfe)) 2022 >; 2023 2024 def : Pat < 2025 (vt (int_SI_buffer_load_dword i128:$rsrc, i32:$vaddr, i32:$soffset, 2026 imm:$offset, 0, 1, imm:$glc, imm:$slc, 2027 imm:$tfe)), 2028 (idxen $rsrc, $vaddr, (as_i16imm $offset), $soffset, (as_i1imm $glc), 2029 (as_i1imm $slc), (as_i1imm $tfe)) 2030 >; 2031 2032 def : Pat < 2033 (vt (int_SI_buffer_load_dword i128:$rsrc, v2i32:$vaddr, i32:$soffset, 2034 imm, 1, 1, imm:$glc, imm:$slc, 2035 imm:$tfe)), 2036 (bothen $rsrc, $vaddr, $soffset, (as_i1imm $glc), (as_i1imm $slc), 2037 (as_i1imm $tfe)) 2038 >; 2039} 2040 2041defm : MUBUF_Load_Dword <i32, BUFFER_LOAD_DWORD_OFFSET, BUFFER_LOAD_DWORD_OFFEN, 2042 BUFFER_LOAD_DWORD_IDXEN, BUFFER_LOAD_DWORD_BOTHEN>; 2043defm : MUBUF_Load_Dword <v2i32, BUFFER_LOAD_DWORDX2_OFFSET, BUFFER_LOAD_DWORDX2_OFFEN, 2044 BUFFER_LOAD_DWORDX2_IDXEN, BUFFER_LOAD_DWORDX2_BOTHEN>; 2045defm : MUBUF_Load_Dword <v4i32, BUFFER_LOAD_DWORDX4_OFFSET, BUFFER_LOAD_DWORDX4_OFFEN, 2046 BUFFER_LOAD_DWORDX4_IDXEN, BUFFER_LOAD_DWORDX4_BOTHEN>; 2047 2048//===----------------------------------------------------------------------===// 2049// MTBUF Patterns 2050//===----------------------------------------------------------------------===// 2051 2052// TBUFFER_STORE_FORMAT_*, addr64=0 2053class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 2054 (SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 2055 i32:$soffset, imm:$inst_offset, imm:$dfmt, 2056 imm:$nfmt, imm:$offen, imm:$idxen, 2057 imm:$glc, imm:$slc, imm:$tfe), 2058 (opcode 2059 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 2060 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 2061 (as_i1imm $slc), (as_i1imm $tfe), $soffset) 2062>; 2063 2064def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 2065def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 2066def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 2067def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 2068 2069/********** ====================== **********/ 2070/********** Indirect adressing **********/ 2071/********** ====================== **********/ 2072 2073multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> { 2074 2075 // 1. Extract with offset 2076 def : Pat< 2077 (vector_extract vt:$vec, (add i32:$idx, imm:$off)), 2078 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off)) 2079 >; 2080 2081 // 2. Extract without offset 2082 def : Pat< 2083 (vector_extract vt:$vec, i32:$idx), 2084 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) 2085 >; 2086 2087 // 3. Insert with offset 2088 def : Pat< 2089 (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)), 2090 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) 2091 >; 2092 2093 // 4. Insert without offset 2094 def : Pat< 2095 (vector_insert vt:$vec, f32:$val, i32:$idx), 2096 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) 2097 >; 2098} 2099 2100defm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>; 2101defm : SI_INDIRECT_Pattern <v4f32, SI_INDIRECT_DST_V4>; 2102defm : SI_INDIRECT_Pattern <v8f32, SI_INDIRECT_DST_V8>; 2103defm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>; 2104 2105/********** =============== **********/ 2106/********** Conditions **********/ 2107/********** =============== **********/ 2108 2109def : Pat< 2110 (i1 (setcc f32:$src0, f32:$src1, SETO)), 2111 (V_CMP_O_F32_e64 $src0, $src1) 2112>; 2113 2114def : Pat< 2115 (i1 (setcc f32:$src0, f32:$src1, SETUO)), 2116 (V_CMP_U_F32_e64 $src0, $src1) 2117>; 2118 2119//===----------------------------------------------------------------------===// 2120// Miscellaneous Patterns 2121//===----------------------------------------------------------------------===// 2122 2123def : Pat < 2124 (i64 (trunc i128:$x)), 2125 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2126 (i32 (EXTRACT_SUBREG $x, sub0)), sub0), 2127 (i32 (EXTRACT_SUBREG $x, sub1)), sub1) 2128>; 2129 2130def : Pat < 2131 (i32 (trunc i64:$a)), 2132 (EXTRACT_SUBREG $a, sub0) 2133>; 2134 2135def : Pat < 2136 (i1 (trunc i32:$a)), 2137 (V_CMP_EQ_I32_e64 (V_AND_B32_e32 (i32 1), $a), 1) 2138>; 2139 2140// V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector 2141// case, the sgpr-copies pass will fix this to use the vector version. 2142def : Pat < 2143 (i32 (addc i32:$src0, i32:$src1)), 2144 (S_ADD_I32 $src0, $src1) 2145>; 2146 2147def : Pat < 2148 (or i64:$a, i64:$b), 2149 (INSERT_SUBREG 2150 (INSERT_SUBREG (IMPLICIT_DEF), 2151 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub0), (EXTRACT_SUBREG $b, sub0)), sub0), 2152 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub1), (EXTRACT_SUBREG $b, sub1)), sub1) 2153>; 2154 2155//============================================================================// 2156// Miscellaneous Optimization Patterns 2157//============================================================================// 2158 2159def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>; 2160 2161} // End isSI predicate 2162