SIInstructions.td revision 263508
1193323Sed//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// This file was originally auto-generated from a GPU register header file and 10193323Sed// all the instruction definitions were originally commented out. Instructions 11193323Sed// that are not yet supported remain commented out. 12193323Sed//===----------------------------------------------------------------------===// 13193323Sed 14193323Sedclass InterpSlots { 15193323Sedint P0 = 2; 16193323Sedint P10 = 0; 17193323Sedint P20 = 1; 18193323Sed} 19193323Seddef INTERP : InterpSlots; 20193323Sed 21193323Seddef InterpSlot : Operand<i32> { 22193323Sed let PrintMethod = "printInterpSlot"; 23193323Sed} 24193323Sed 25193323Seddef isSI : Predicate<"Subtarget.getGeneration() " 26193323Sed ">= AMDGPUSubtarget::SOUTHERN_ISLANDS">; 27193323Sed 28193323Seddef WAIT_FLAG : InstFlag<"printWaitFlag">; 29193323Sed 30193323Sedlet Predicates = [isSI] in { 31198090Srdivacky 32198090Srdivackylet neverHasSideEffects = 1 in { 33193323Sed 34193323Sedlet isMoveImm = 1 in { 35193323Seddef S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 36198090Srdivackydef S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 37193323Seddef S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 38193323Seddef S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 39193323Sed} // End isMoveImm = 1 40193323Sed 41193323Seddef S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 42193323Seddef S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 43193323Seddef S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 44193323Seddef S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 45198090Srdivackydef S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 46198090Srdivackydef S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 47198090Srdivacky} // End neverHasSideEffects = 1 48203954Srdivacky 49203954Srdivacky////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 50203954Srdivacky////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 51193574Sed////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 52193574Sed////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 53193574Sed////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 54193323Sed////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 55193323Sed////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 56193323Sed////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 57198090Srdivacky//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 58198090Srdivacky//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 59198090Srdivackydef S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 60203954Srdivacky//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 61203954Srdivacky//def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 62203954Srdivacky//def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 63193574Sed////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 64193574Sed////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 65193574Sed////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 66193323Sed////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 67193323Seddef S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 68193323Seddef S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 69201360Srdivackydef S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 70201360Srdivackydef S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 71201360Srdivacky 72203954Srdivackylet hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 73203954Srdivacky 74203954Srdivackydef S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 75193574Seddef S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 76193574Seddef S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 77193574Seddef S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 78193323Seddef S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 79193323Seddef S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 80193323Seddef S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 81193323Seddef S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 82193323Sed 83193323Sed} // End hasSideEffects = 1 84198090Srdivacky 85198090Srdivackydef S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 86198090Srdivackydef S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 87193323Seddef S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 88193323Seddef S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 89193323Seddef S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 90193323Seddef S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 91193323Sed//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 92193323Seddef S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 93193323Seddef S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 94193323Seddef S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 95193323Seddef S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 96193323Seddef S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 97193323Sed 98193323Sed/* 99193323SedThis instruction is disabled for now until we can figure out how to teach 100193323Sedthe instruction selector to correctly use the S_CMP* vs V_CMP* 101193323Sedinstructions. 102193323Sed 103193323SedWhen this instruction is enabled the code generator sometimes produces this 104193323Sedinvalid sequence: 105193323Sed 106193323SedSCC = S_CMPK_EQ_I32 SGPR0, imm 107193323SedVCC = COPY SCC 108193323SedVGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 109193323Sed 110193323Seddef S_CMPK_EQ_I32 : SOPK < 111193323Sed 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 112193323Sed "S_CMPK_EQ_I32", 113193323Sed [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 114193323Sed>; 115193323Sed*/ 116193323Sed 117193323Sedlet isCompare = 1 in { 118193323Seddef S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 119193323Seddef S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 120193323Seddef S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 121193323Seddef S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 122193323Seddef S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 123193323Seddef S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 124193323Seddef S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 125193323Seddef S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 126193323Seddef S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 127193323Seddef S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 128193323Seddef S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 129193323Sed} // End isCompare = 1 130201360Srdivacky 131201360Srdivackylet Defs = [SCC], isCommutable = 1 in { 132201360Srdivacky def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 133203954Srdivacky def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 134203954Srdivacky} 135203954Srdivacky 136193323Sed//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 137193323Seddef S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 138193323Seddef S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 139193323Seddef S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 140193323Sed//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 141193323Sed//def EXP : EXP_ <0x00000000, "EXP", []>; 142193323Sed 143193323Sedlet isCompare = 1 in { 144193323Sed 145193323Seddefm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 146193323Seddefm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_OLT>; 147193323Seddefm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_OEQ>; 148193323Seddefm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_OLE>; 149193323Seddefm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_OGT>; 150193323Seddefm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32">; 151193323Seddefm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_OGE>; 152193323Seddefm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32", f32, COND_O>; 153198090Srdivackydefm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32", f32, COND_UO>; 154198090Srdivackydefm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 155198090Srdivackydefm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 156198090Srdivackydefm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 157198090Srdivackydefm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 158198090Srdivackydefm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_UNE>; 159198090Srdivackydefm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 160198090Srdivackydefm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 161198090Srdivacky 162193323Sedlet hasSideEffects = 1, Defs = [EXEC] in { 163193323Sed 164193323Seddefm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 165193323Seddefm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 166193323Seddefm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 167193323Seddefm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 168193323Seddefm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 169193323Seddefm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 170193323Seddefm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 171193323Seddefm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 172193323Seddefm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 173193323Seddefm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 174193323Seddefm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 175193323Seddefm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 176193323Seddefm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 177193323Seddefm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 178193323Seddefm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 179193323Seddefm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 180193323Sed 181193323Sed} // End hasSideEffects = 1, Defs = [EXEC] 182193323Sed 183193323Seddefm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 184193323Seddefm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64", f64, COND_OLT>; 185193323Seddefm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64", f64, COND_OEQ>; 186193323Seddefm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64", f64, COND_OLE>; 187193323Seddefm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64", f64, COND_OGT>; 188193323Seddefm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 189193323Seddefm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64", f64, COND_OGE>; 190193323Seddefm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64", f64, COND_O>; 191193323Seddefm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64", f64, COND_UO>; 192193323Seddefm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 193193323Seddefm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 194193323Seddefm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 195199989Srdivackydefm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 196193323Seddefm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64", f64, COND_UNE>; 197193323Seddefm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 198193323Seddefm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 199193323Sed 200193323Sedlet hasSideEffects = 1, Defs = [EXEC] in { 201193323Sed 202193323Seddefm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 203193323Seddefm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 204193323Seddefm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 205193323Seddefm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 206193323Seddefm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 207193323Seddefm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 208193323Seddefm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 209193323Seddefm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 210193323Seddefm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 211193323Seddefm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 212193323Seddefm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 213193323Seddefm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 214193323Seddefm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 215193323Seddefm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 216193323Seddefm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 217193323Seddefm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 218193323Sed 219193323Sed} // End hasSideEffects = 1, Defs = [EXEC] 220193323Sed 221defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 222defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 223defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 224defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 225defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 226defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 227defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 228defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 229defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 230defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 231defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 232defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 233defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 234defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 235defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 236defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 237 238let hasSideEffects = 1, Defs = [EXEC] in { 239 240defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 241defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 242defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 243defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 244defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 245defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 246defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 247defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 248defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 249defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 250defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 251defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 252defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 253defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 254defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 255defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 256 257} // End hasSideEffects = 1, Defs = [EXEC] 258 259defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 260defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 261defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 262defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 263defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 264defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 265defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 266defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 267defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 268defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 269defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 270defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 271defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 272defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 273defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 274defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 275 276let hasSideEffects = 1, Defs = [EXEC] in { 277 278defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 279defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 280defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 281defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 282defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 283defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 284defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 285defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 286defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 287defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 288defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 289defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 290defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 291defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 292defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 293defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 294 295} // End hasSideEffects = 1, Defs = [EXEC] 296 297defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 298defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_SLT>; 299defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 300defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_SLE>; 301defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_SGT>; 302defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 303defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_SGE>; 304defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 305 306let hasSideEffects = 1, Defs = [EXEC] in { 307 308defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 309defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 310defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 311defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 312defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 313defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 314defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 315defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 316 317} // End hasSideEffects = 1, Defs = [EXEC] 318 319defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 320defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64", i64, COND_SLT>; 321defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64", i64, COND_EQ>; 322defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64", i64, COND_SLE>; 323defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64", i64, COND_SGT>; 324defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64", i64, COND_NE>; 325defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64", i64, COND_SGE>; 326defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 327 328let hasSideEffects = 1, Defs = [EXEC] in { 329 330defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 331defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 332defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 333defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 334defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 335defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 336defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 337defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 338 339} // End hasSideEffects = 1, Defs = [EXEC] 340 341defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 342defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32", i32, COND_ULT>; 343defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32", i32, COND_EQ>; 344defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32", i32, COND_ULE>; 345defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32", i32, COND_UGT>; 346defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32", i32, COND_NE>; 347defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32", i32, COND_UGE>; 348defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 349 350let hasSideEffects = 1, Defs = [EXEC] in { 351 352defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 353defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 354defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 355defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 356defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 357defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 358defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 359defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 360 361} // End hasSideEffects = 1, Defs = [EXEC] 362 363defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 364defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64", i64, COND_ULT>; 365defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64", i64, COND_EQ>; 366defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64", i64, COND_ULE>; 367defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64", i64, COND_UGT>; 368defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64", i64, COND_NE>; 369defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64", i64, COND_UGE>; 370defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 371 372let hasSideEffects = 1, Defs = [EXEC] in { 373 374defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 375defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 376defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 377defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 378defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 379defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 380defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 381defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 382 383} // End hasSideEffects = 1, Defs = [EXEC] 384 385defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 386 387let hasSideEffects = 1, Defs = [EXEC] in { 388defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 389} // End hasSideEffects = 1, Defs = [EXEC] 390 391defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 392 393let hasSideEffects = 1, Defs = [EXEC] in { 394defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 395} // End hasSideEffects = 1, Defs = [EXEC] 396 397} // End isCompare = 1 398 399def DS_ADD_U32_RTN : DS_1A1D_RET <0x20, "DS_ADD_U32_RTN", VReg_32>; 400def DS_SUB_U32_RTN : DS_1A1D_RET <0x21, "DS_SUB_U32_RTN", VReg_32>; 401def DS_WRITE_B32 : DS_Store_Helper <0x0000000d, "DS_WRITE_B32", VReg_32>; 402def DS_WRITE_B8 : DS_Store_Helper <0x00000001e, "DS_WRITE_B8", VReg_32>; 403def DS_WRITE_B16 : DS_Store_Helper <0x00000001f, "DS_WRITE_B16", VReg_32>; 404def DS_READ_B32 : DS_Load_Helper <0x00000036, "DS_READ_B32", VReg_32>; 405def DS_READ_I8 : DS_Load_Helper <0x00000039, "DS_READ_I8", VReg_32>; 406def DS_READ_U8 : DS_Load_Helper <0x0000003a, "DS_READ_U8", VReg_32>; 407def DS_READ_I16 : DS_Load_Helper <0x0000003b, "DS_READ_I16", VReg_32>; 408def DS_READ_U16 : DS_Load_Helper <0x0000003c, "DS_READ_U16", VReg_32>; 409 410//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 411//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 412//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 413defm BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 414//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 415//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 416//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 417//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 418defm BUFFER_LOAD_UBYTE : MUBUF_Load_Helper <0x00000008, "BUFFER_LOAD_UBYTE", VReg_32>; 419defm BUFFER_LOAD_SBYTE : MUBUF_Load_Helper <0x00000009, "BUFFER_LOAD_SBYTE", VReg_32>; 420defm BUFFER_LOAD_USHORT : MUBUF_Load_Helper <0x0000000a, "BUFFER_LOAD_USHORT", VReg_32>; 421defm BUFFER_LOAD_SSHORT : MUBUF_Load_Helper <0x0000000b, "BUFFER_LOAD_SSHORT", VReg_32>; 422defm BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 423defm BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 424defm BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 425 426def BUFFER_STORE_BYTE : MUBUF_Store_Helper < 427 0x00000018, "BUFFER_STORE_BYTE", VReg_32 428>; 429 430def BUFFER_STORE_SHORT : MUBUF_Store_Helper < 431 0x0000001a, "BUFFER_STORE_SHORT", VReg_32 432>; 433 434def BUFFER_STORE_DWORD : MUBUF_Store_Helper < 435 0x0000001c, "BUFFER_STORE_DWORD", VReg_32 436>; 437 438def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 439 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64 440>; 441 442def BUFFER_STORE_DWORDX4 : MUBUF_Store_Helper < 443 0x0000001e, "BUFFER_STORE_DWORDX4", VReg_128 444>; 445//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 446//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 447//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 448//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 449//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 450//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 451//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 452//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 453//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 454//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 455//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 456//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 457//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 458//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 459//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 460//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 461//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 462//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 463//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 464//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 465//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 466//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 467//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 468//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 469//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 470//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 471//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 472//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 473//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 474//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 475//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 476//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 477//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 478//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 479//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 480//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 481//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 482//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 483//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 484def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 485def TBUFFER_STORE_FORMAT_X : MTBUF_Store_Helper <0x00000004, "TBUFFER_STORE_FORMAT_X", VReg_32>; 486def TBUFFER_STORE_FORMAT_XY : MTBUF_Store_Helper <0x00000005, "TBUFFER_STORE_FORMAT_XY", VReg_64>; 487def TBUFFER_STORE_FORMAT_XYZ : MTBUF_Store_Helper <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", VReg_128>; 488def TBUFFER_STORE_FORMAT_XYZW : MTBUF_Store_Helper <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", VReg_128>; 489 490let mayLoad = 1 in { 491 492// We are using the SGPR_32 and not the SReg_32 register class for 32-bit 493// SMRD instructions, because the SGPR_32 register class does not include M0 494// and writing to M0 from an SMRD instruction will hang the GPU. 495defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SGPR_32>; 496defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 497defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 498defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 499defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 500 501defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 502 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SGPR_32 503>; 504 505defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 506 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 507>; 508 509defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 510 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 511>; 512 513defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 514 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 515>; 516 517defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 518 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 519>; 520 521} // mayLoad = 1 522 523//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 524//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 525defm IMAGE_LOAD : MIMG_NoSampler <0x00000000, "IMAGE_LOAD">; 526defm IMAGE_LOAD_MIP : MIMG_NoSampler <0x00000001, "IMAGE_LOAD_MIP">; 527//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 528//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 529//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 530//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 531//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 532//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 533//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 534//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 535defm IMAGE_GET_RESINFO : MIMG_NoSampler <0x0000000e, "IMAGE_GET_RESINFO">; 536//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 537//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 538//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 539//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 540//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 541//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 542//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 543//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 544//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 545//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 546//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 547//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 548//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 549//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 550//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 551//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 552//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 553defm IMAGE_SAMPLE : MIMG_Sampler <0x00000020, "IMAGE_SAMPLE">; 554//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 555defm IMAGE_SAMPLE_D : MIMG_Sampler <0x00000022, "IMAGE_SAMPLE_D">; 556//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 557defm IMAGE_SAMPLE_L : MIMG_Sampler <0x00000024, "IMAGE_SAMPLE_L">; 558defm IMAGE_SAMPLE_B : MIMG_Sampler <0x00000025, "IMAGE_SAMPLE_B">; 559//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 560//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 561defm IMAGE_SAMPLE_C : MIMG_Sampler <0x00000028, "IMAGE_SAMPLE_C">; 562//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 563defm IMAGE_SAMPLE_C_D : MIMG_Sampler <0x0000002a, "IMAGE_SAMPLE_C_D">; 564//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 565defm IMAGE_SAMPLE_C_L : MIMG_Sampler <0x0000002c, "IMAGE_SAMPLE_C_L">; 566defm IMAGE_SAMPLE_C_B : MIMG_Sampler <0x0000002d, "IMAGE_SAMPLE_C_B">; 567//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 568//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 569//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 570//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 571//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 572//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 573//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 574//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 575//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 576//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 577//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 578//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 579//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 580//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 581//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 582//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 583//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 584//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 585//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 586//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 587//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 588//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 589//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 590//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 591//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 592//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 593//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 594//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 595//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 596//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 597//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 598//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 599//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 600//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 601//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 602//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 603//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 604//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 605//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 606//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 607//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 608//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 609//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 610//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 611//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 612//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 613//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 614//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 615//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 616//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 617//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 618//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 619//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 620//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 621 622 623let neverHasSideEffects = 1, isMoveImm = 1 in { 624defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 625} // End neverHasSideEffects = 1, isMoveImm = 1 626 627defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; 628defm V_CVT_I32_F64 : VOP1_32_64 <0x00000003, "V_CVT_I32_F64", 629 [(set i32:$dst, (fp_to_sint f64:$src0))] 630>; 631defm V_CVT_F64_I32 : VOP1_64_32 <0x00000004, "V_CVT_F64_I32", 632 [(set f64:$dst, (sint_to_fp i32:$src0))] 633>; 634defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 635 [(set f32:$dst, (sint_to_fp i32:$src0))] 636>; 637defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", 638 [(set f32:$dst, (uint_to_fp i32:$src0))] 639>; 640defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", 641 [(set i32:$dst, (fp_to_uint f32:$src0))] 642>; 643defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 644 [(set i32:$dst, (fp_to_sint f32:$src0))] 645>; 646defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 647////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 648//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 649//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 650//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 651//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 652defm V_CVT_F32_F64 : VOP1_32_64 <0x0000000f, "V_CVT_F32_F64", 653 [(set f32:$dst, (fround f64:$src0))] 654>; 655defm V_CVT_F64_F32 : VOP1_64_32 <0x00000010, "V_CVT_F64_F32", 656 [(set f64:$dst, (fextend f32:$src0))] 657>; 658//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 659//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 660//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 661//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 662//defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 663//defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 664defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 665 [(set f32:$dst, (AMDGPUfract f32:$src0))] 666>; 667defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", 668 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))] 669>; 670defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 671 [(set f32:$dst, (fceil f32:$src0))] 672>; 673defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 674 [(set f32:$dst, (frint f32:$src0))] 675>; 676defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 677 [(set f32:$dst, (ffloor f32:$src0))] 678>; 679defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 680 [(set f32:$dst, (fexp2 f32:$src0))] 681>; 682defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 683defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 684 [(set f32:$dst, (flog2 f32:$src0))] 685>; 686defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 687defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 688defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 689 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 690>; 691defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 692defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 693defm V_RSQ_LEGACY_F32 : VOP1_32 < 694 0x0000002d, "V_RSQ_LEGACY_F32", 695 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))] 696>; 697defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 698defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", 699 [(set f64:$dst, (fdiv FP_ONE, f64:$src0))] 700>; 701defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 702defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 703defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 704defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", 705 [(set f32:$dst, (fsqrt f32:$src0))] 706>; 707defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", 708 [(set f64:$dst, (fsqrt f64:$src0))] 709>; 710defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 711defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 712defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 713defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 714defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 715defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 716defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 717//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 718defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 719defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 720//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 721defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 722//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 723defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 724defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 725defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 726 727def V_INTERP_P1_F32 : VINTRP < 728 0x00000000, 729 (outs VReg_32:$dst), 730 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 731 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 732 []> { 733 let DisableEncoding = "$m0"; 734} 735 736def V_INTERP_P2_F32 : VINTRP < 737 0x00000001, 738 (outs VReg_32:$dst), 739 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 740 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 741 []> { 742 743 let Constraints = "$src0 = $dst"; 744 let DisableEncoding = "$src0,$m0"; 745 746} 747 748def V_INTERP_MOV_F32 : VINTRP < 749 0x00000002, 750 (outs VReg_32:$dst), 751 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 752 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 753 []> { 754 let DisableEncoding = "$m0"; 755} 756 757//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 758 759let isTerminator = 1 in { 760 761def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 762 [(IL_retflag)]> { 763 let SIMM16 = 0; 764 let isBarrier = 1; 765 let hasCtrlDep = 1; 766} 767 768let isBranch = 1 in { 769def S_BRANCH : SOPP < 770 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 771 [(br bb:$target)]> { 772 let isBarrier = 1; 773} 774 775let DisableEncoding = "$scc" in { 776def S_CBRANCH_SCC0 : SOPP < 777 0x00000004, (ins brtarget:$target, SCCReg:$scc), 778 "S_CBRANCH_SCC0 $target", [] 779>; 780def S_CBRANCH_SCC1 : SOPP < 781 0x00000005, (ins brtarget:$target, SCCReg:$scc), 782 "S_CBRANCH_SCC1 $target", 783 [] 784>; 785} // End DisableEncoding = "$scc" 786 787def S_CBRANCH_VCCZ : SOPP < 788 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 789 "S_CBRANCH_VCCZ $target", 790 [] 791>; 792def S_CBRANCH_VCCNZ : SOPP < 793 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 794 "S_CBRANCH_VCCNZ $target", 795 [] 796>; 797 798let DisableEncoding = "$exec" in { 799def S_CBRANCH_EXECZ : SOPP < 800 0x00000008, (ins brtarget:$target, EXECReg:$exec), 801 "S_CBRANCH_EXECZ $target", 802 [] 803>; 804def S_CBRANCH_EXECNZ : SOPP < 805 0x00000009, (ins brtarget:$target, EXECReg:$exec), 806 "S_CBRANCH_EXECNZ $target", 807 [] 808>; 809} // End DisableEncoding = "$exec" 810 811 812} // End isBranch = 1 813} // End isTerminator = 1 814 815let hasSideEffects = 1 in { 816def S_BARRIER : SOPP <0x0000000a, (ins), "S_BARRIER", 817 [(int_AMDGPU_barrier_local)] 818> { 819 let SIMM16 = 0; 820 let isBarrier = 1; 821 let hasCtrlDep = 1; 822 let mayLoad = 1; 823 let mayStore = 1; 824} 825 826def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "S_WAITCNT $simm16", 827 [] 828>; 829} // End hasSideEffects 830//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 831//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 832//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 833//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>; 834//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 835//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 836//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 837//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 838//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 839//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 840 841def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 842 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 843 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 844 [] 845>{ 846 let DisableEncoding = "$vcc"; 847} 848 849def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 850 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 851 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 852 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 853 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] 854>; 855 856//f32 pattern for V_CNDMASK_B32_e64 857def : Pat < 858 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 859 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 860>; 861 862def : Pat < 863 (i32 (trunc i64:$val)), 864 (EXTRACT_SUBREG $val, sub0) 865>; 866 867//use two V_CNDMASK_B32_e64 instructions for f64 868def : Pat < 869 (f64 (select i1:$src2, f64:$src1, f64:$src0)), 870 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 871 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub0), 872 (EXTRACT_SUBREG $src1, sub0), 873 $src2), sub0), 874 (V_CNDMASK_B32_e64 (EXTRACT_SUBREG $src0, sub1), 875 (EXTRACT_SUBREG $src1, sub1), 876 $src2), sub1) 877>; 878 879defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; 880defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; 881 882let isCommutable = 1 in { 883defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 884 [(set f32:$dst, (fadd f32:$src0, f32:$src1))] 885>; 886 887defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 888 [(set f32:$dst, (fsub f32:$src0, f32:$src1))] 889>; 890defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; 891} // End isCommutable = 1 892 893defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 894 895let isCommutable = 1 in { 896 897defm V_MUL_LEGACY_F32 : VOP2_32 < 898 0x00000007, "V_MUL_LEGACY_F32", 899 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] 900>; 901 902defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 903 [(set f32:$dst, (fmul f32:$src0, f32:$src1))] 904>; 905 906 907defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", 908 [(set i32:$dst, (mul I24:$src0, I24:$src1))] 909>; 910//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 911defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", 912 [(set i32:$dst, (mul U24:$src0, U24:$src1))] 913>; 914//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 915 916 917defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 918 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] 919>; 920 921defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 922 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] 923>; 924 925defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 926defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 927defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", 928 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] 929>; 930defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", 931 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] 932>; 933defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", 934 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] 935>; 936defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", 937 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] 938>; 939 940defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", 941 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 942>; 943defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; 944 945defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", 946 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 947>; 948defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; 949 950let hasPostISelHook = 1 in { 951 952defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", 953 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 954>; 955 956} 957defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; 958 959defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", 960 [(set i32:$dst, (and i32:$src0, i32:$src1))] 961>; 962defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", 963 [(set i32:$dst, (or i32:$src0, i32:$src1))] 964>; 965defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", 966 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 967>; 968 969} // End isCommutable = 1 970 971defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; 972defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 973defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 974defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 975//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 976defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 977defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 978 979let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC 980// No patterns so that the scalar instructions are always selected. 981// The scalar versions will be replaced with vector when needed later. 982defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", []>; 983defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", []>; 984defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">; 985 986let Uses = [VCC] in { // Carry-in comes from VCC 987defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>; 988defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>; 989defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">; 990} // End Uses = [VCC] 991} // End isCommutable = 1, Defs = [VCC] 992 993defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 994////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 995////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 996////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 997defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 998 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] 999>; 1000////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 1001////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 1002def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 1003def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 1004def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 1005def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 1006def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 1007def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 1008def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 1009def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 1010def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 1011def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 1012def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 1013def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 1014////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 1015////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 1016////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 1017////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 1018//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 1019 1020let neverHasSideEffects = 1 in { 1021 1022def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 1023def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 1024def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", 1025 [(set i32:$dst, (add (mul I24:$src0, I24:$src1), i32:$src2))] 1026>; 1027def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", 1028 [(set i32:$dst, (add (mul U24:$src0, U24:$src1), i32:$src2))] 1029>; 1030 1031} // End neverHasSideEffects 1032def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 1033def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 1034def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 1035def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 1036def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; 1037def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; 1038def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; 1039defm : BFIPatterns <V_BFI_B32>; 1040def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", 1041 [(set f32:$dst, (fma f32:$src0, f32:$src1, f32:$src2))] 1042>; 1043def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", 1044 [(set f64:$dst, (fma f64:$src0, f64:$src1, f64:$src2))] 1045>; 1046//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 1047def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 1048def : ROTRPattern <V_ALIGNBIT_B32>; 1049 1050def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 1051def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 1052////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 1053////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 1054////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 1055////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 1056////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 1057////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 1058////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 1059////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 1060////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 1061//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 1062//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 1063//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 1064def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 1065////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 1066def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 1067def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 1068 1069def V_LSHL_B64 : VOP3_64_Shift <0x00000161, "V_LSHL_B64", 1070 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1071>; 1072def V_LSHR_B64 : VOP3_64_Shift <0x00000162, "V_LSHR_B64", 1073 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1074>; 1075def V_ASHR_I64 : VOP3_64_Shift <0x00000163, "V_ASHR_I64", 1076 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1077>; 1078 1079let isCommutable = 1 in { 1080 1081def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 1082def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 1083def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 1084def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 1085 1086} // isCommutable = 1 1087 1088def : Pat < 1089 (fadd f64:$src0, f64:$src1), 1090 (V_ADD_F64 $src0, $src1, (i64 0)) 1091>; 1092 1093def : Pat < 1094 (fmul f64:$src0, f64:$src1), 1095 (V_MUL_F64 $src0, $src1, (i64 0)) 1096>; 1097 1098def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 1099 1100let isCommutable = 1 in { 1101 1102def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 1103def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 1104def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 1105def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 1106 1107} // isCommutable = 1 1108 1109def : Pat < 1110 (mul i32:$src0, i32:$src1), 1111 (V_MUL_LO_I32 $src0, $src1, (i32 0)) 1112>; 1113 1114def : Pat < 1115 (mulhu i32:$src0, i32:$src1), 1116 (V_MUL_HI_U32 $src0, $src1, (i32 0)) 1117>; 1118 1119def : Pat < 1120 (mulhs i32:$src0, i32:$src1), 1121 (V_MUL_HI_I32 $src0, $src1, (i32 0)) 1122>; 1123 1124def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 1125def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 1126def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 1127def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 1128//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 1129//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 1130//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 1131def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 1132 1133let Defs = [SCC] in { // Carry out goes to SCC 1134let isCommutable = 1 in { 1135def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 1136def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", 1137 [(set i32:$dst, (add SSrc_32:$src0, SSrc_32:$src1))] 1138>; 1139} // End isCommutable = 1 1140 1141def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 1142def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", 1143 [(set i32:$dst, (sub SSrc_32:$src0, SSrc_32:$src1))] 1144>; 1145 1146let Uses = [SCC] in { // Carry in comes from SCC 1147let isCommutable = 1 in { 1148def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", 1149 [(set i32:$dst, (adde (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 1150} // End isCommutable = 1 1151 1152def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", 1153 [(set i32:$dst, (sube (i32 SSrc_32:$src0), (i32 SSrc_32:$src1)))]>; 1154} // End Uses = [SCC] 1155} // End Defs = [SCC] 1156 1157def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; 1158def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; 1159def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; 1160def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; 1161 1162def S_CSELECT_B32 : SOP2 < 1163 0x0000000a, (outs SReg_32:$dst), 1164 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 1165 [] 1166>; 1167 1168def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 1169 1170def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; 1171 1172def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 1173 [(set i64:$dst, (and i64:$src0, i64:$src1))] 1174>; 1175 1176def : Pat < 1177 (i1 (and i1:$src0, i1:$src1)), 1178 (S_AND_B64 $src0, $src1) 1179>; 1180 1181def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; 1182def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; 1183def : Pat < 1184 (i1 (or i1:$src0, i1:$src1)), 1185 (S_OR_B64 $src0, $src1) 1186>; 1187def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; 1188def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", 1189 [(set i1:$dst, (xor i1:$src0, i1:$src1))] 1190>; 1191def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 1192def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 1193def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 1194def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 1195def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 1196def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 1197def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 1198def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 1199def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 1200def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 1201 1202// Use added complexity so these patterns are preferred to the VALU patterns. 1203let AddedComplexity = 1 in { 1204 1205def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", 1206 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 1207>; 1208def S_LSHL_B64 : SOP2_SHIFT_64 <0x0000001f, "S_LSHL_B64", 1209 [(set i64:$dst, (shl i64:$src0, i32:$src1))] 1210>; 1211def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", 1212 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 1213>; 1214def S_LSHR_B64 : SOP2_SHIFT_64 <0x00000021, "S_LSHR_B64", 1215 [(set i64:$dst, (srl i64:$src0, i32:$src1))] 1216>; 1217def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", 1218 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 1219>; 1220def S_ASHR_I64 : SOP2_SHIFT_64 <0x00000023, "S_ASHR_I64", 1221 [(set i64:$dst, (sra i64:$src0, i32:$src1))] 1222>; 1223 1224} // End AddedComplexity = 1 1225 1226def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 1227def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 1228def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 1229def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 1230def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 1231def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 1232def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 1233//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 1234def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 1235 1236let isCodeGenOnly = 1, isPseudo = 1 in { 1237 1238def LOAD_CONST : AMDGPUShaderInst < 1239 (outs GPRF32:$dst), 1240 (ins i32imm:$src), 1241 "LOAD_CONST $dst, $src", 1242 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 1243>; 1244 1245// SI pseudo instructions. These are used by the CFG structurizer pass 1246// and should be lowered to ISA instructions prior to codegen. 1247 1248let mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1249 Uses = [EXEC], Defs = [EXEC] in { 1250 1251let isBranch = 1, isTerminator = 1 in { 1252 1253def SI_IF : InstSI < 1254 (outs SReg_64:$dst), 1255 (ins SReg_64:$vcc, brtarget:$target), 1256 "SI_IF $dst, $vcc, $target", 1257 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))] 1258>; 1259 1260def SI_ELSE : InstSI < 1261 (outs SReg_64:$dst), 1262 (ins SReg_64:$src, brtarget:$target), 1263 "SI_ELSE $dst, $src, $target", 1264 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> { 1265 1266 let Constraints = "$src = $dst"; 1267} 1268 1269def SI_LOOP : InstSI < 1270 (outs), 1271 (ins SReg_64:$saved, brtarget:$target), 1272 "SI_LOOP $saved, $target", 1273 [(int_SI_loop i64:$saved, bb:$target)] 1274>; 1275 1276} // end isBranch = 1, isTerminator = 1 1277 1278def SI_BREAK : InstSI < 1279 (outs SReg_64:$dst), 1280 (ins SReg_64:$src), 1281 "SI_ELSE $dst, $src", 1282 [(set i64:$dst, (int_SI_break i64:$src))] 1283>; 1284 1285def SI_IF_BREAK : InstSI < 1286 (outs SReg_64:$dst), 1287 (ins SReg_64:$vcc, SReg_64:$src), 1288 "SI_IF_BREAK $dst, $vcc, $src", 1289 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] 1290>; 1291 1292def SI_ELSE_BREAK : InstSI < 1293 (outs SReg_64:$dst), 1294 (ins SReg_64:$src0, SReg_64:$src1), 1295 "SI_ELSE_BREAK $dst, $src0, $src1", 1296 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] 1297>; 1298 1299def SI_END_CF : InstSI < 1300 (outs), 1301 (ins SReg_64:$saved), 1302 "SI_END_CF $saved", 1303 [(int_SI_end_cf i64:$saved)] 1304>; 1305 1306def SI_KILL : InstSI < 1307 (outs), 1308 (ins VReg_32:$src), 1309 "SI_KIL $src", 1310 [(int_AMDGPU_kill f32:$src)] 1311>; 1312 1313} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1314 // Uses = [EXEC], Defs = [EXEC] 1315 1316let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1317 1318//defm SI_ : RegisterLoadStore <VReg_32, FRAMEri64, ADDRIndirect>; 1319 1320let UseNamedOperandTable = 1 in { 1321 1322def SI_RegisterLoad : AMDGPUShaderInst < 1323 (outs VReg_32:$dst, SReg_64:$temp), 1324 (ins FRAMEri64:$addr, i32imm:$chan), 1325 "", [] 1326> { 1327 let isRegisterLoad = 1; 1328 let mayLoad = 1; 1329} 1330 1331class SIRegStore<dag outs> : AMDGPUShaderInst < 1332 outs, 1333 (ins VReg_32:$val, FRAMEri64:$addr, i32imm:$chan), 1334 "", [] 1335> { 1336 let isRegisterStore = 1; 1337 let mayStore = 1; 1338} 1339 1340let usesCustomInserter = 1 in { 1341def SI_RegisterStorePseudo : SIRegStore<(outs)>; 1342} // End usesCustomInserter = 1 1343def SI_RegisterStore : SIRegStore<(outs SReg_64:$temp)>; 1344 1345 1346} // End UseNamedOperandTable = 1 1347 1348def SI_INDIRECT_SRC : InstSI < 1349 (outs VReg_32:$dst, SReg_64:$temp), 1350 (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1351 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1352 [] 1353>; 1354 1355class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1356 (outs rc:$dst, SReg_64:$temp), 1357 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1358 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1359 [] 1360> { 1361 let Constraints = "$src = $dst"; 1362} 1363 1364def SI_INDIRECT_DST_V1 : SI_INDIRECT_DST<VReg_32>; 1365def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1366def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1367def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1368def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1369 1370} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1371 1372let usesCustomInserter = 1 in { 1373 1374// This pseudo instruction takes a pointer as input and outputs a resource 1375// constant that can be used with the ADDR64 MUBUF instructions. 1376def SI_ADDR64_RSRC : InstSI < 1377 (outs SReg_128:$srsrc), 1378 (ins SReg_64:$ptr), 1379 "", [] 1380>; 1381 1382def V_SUB_F64 : InstSI < 1383 (outs VReg_64:$dst), 1384 (ins VReg_64:$src0, VReg_64:$src1), 1385 "V_SUB_F64 $dst, $src0, $src1", 1386 [] 1387>; 1388 1389} // end usesCustomInserter 1390 1391} // end IsCodeGenOnly, isPseudo 1392 1393def : Pat< 1394 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), 1395 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) 1396>; 1397 1398def : Pat < 1399 (int_AMDGPU_kilp), 1400 (SI_KILL (V_MOV_B32_e32 0xbf800000)) 1401>; 1402 1403/* int_SI_vs_load_input */ 1404def : Pat< 1405 (SIload_input i128:$tlst, IMM12bit:$attr_offset, i32:$buf_idx_vgpr), 1406 (BUFFER_LOAD_FORMAT_XYZW_IDXEN $tlst, $buf_idx_vgpr, imm:$attr_offset) 1407>; 1408 1409/* int_SI_export */ 1410def : Pat < 1411 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1412 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 1413 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1414 $src0, $src1, $src2, $src3) 1415>; 1416 1417def : Pat < 1418 (f64 (fsub f64:$src0, f64:$src1)), 1419 (V_SUB_F64 $src0, $src1) 1420>; 1421 1422/********** ======================= **********/ 1423/********** Image sampling patterns **********/ 1424/********** ======================= **********/ 1425 1426/* SIsample for simple 1D texture lookup */ 1427def : Pat < 1428 (SIsample i32:$addr, v32i8:$rsrc, i128:$sampler, imm), 1429 (IMAGE_SAMPLE_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1430>; 1431 1432class SamplePattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1433 (name vt:$addr, v32i8:$rsrc, i128:$sampler, imm), 1434 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1435>; 1436 1437class SampleRectPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1438 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_RECT), 1439 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1440>; 1441 1442class SampleArrayPattern<SDNode name, MIMG opcode, ValueType vt> : Pat < 1443 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_ARRAY), 1444 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1445>; 1446 1447class SampleShadowPattern<SDNode name, MIMG opcode, 1448 ValueType vt> : Pat < 1449 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW), 1450 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1451>; 1452 1453class SampleShadowArrayPattern<SDNode name, MIMG opcode, 1454 ValueType vt> : Pat < 1455 (name vt:$addr, v32i8:$rsrc, i128:$sampler, TEX_SHADOW_ARRAY), 1456 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1457>; 1458 1459/* SIsample* for texture lookups consuming more address parameters */ 1460multiclass SamplePatterns<MIMG sample, MIMG sample_c, MIMG sample_l, 1461 MIMG sample_c_l, MIMG sample_b, MIMG sample_c_b, 1462MIMG sample_d, MIMG sample_c_d, ValueType addr_type> { 1463 def : SamplePattern <SIsample, sample, addr_type>; 1464 def : SampleRectPattern <SIsample, sample, addr_type>; 1465 def : SampleArrayPattern <SIsample, sample, addr_type>; 1466 def : SampleShadowPattern <SIsample, sample_c, addr_type>; 1467 def : SampleShadowArrayPattern <SIsample, sample_c, addr_type>; 1468 1469 def : SamplePattern <SIsamplel, sample_l, addr_type>; 1470 def : SampleArrayPattern <SIsamplel, sample_l, addr_type>; 1471 def : SampleShadowPattern <SIsamplel, sample_c_l, addr_type>; 1472 def : SampleShadowArrayPattern <SIsamplel, sample_c_l, addr_type>; 1473 1474 def : SamplePattern <SIsampleb, sample_b, addr_type>; 1475 def : SampleArrayPattern <SIsampleb, sample_b, addr_type>; 1476 def : SampleShadowPattern <SIsampleb, sample_c_b, addr_type>; 1477 def : SampleShadowArrayPattern <SIsampleb, sample_c_b, addr_type>; 1478 1479 def : SamplePattern <SIsampled, sample_d, addr_type>; 1480 def : SampleArrayPattern <SIsampled, sample_d, addr_type>; 1481 def : SampleShadowPattern <SIsampled, sample_c_d, addr_type>; 1482 def : SampleShadowArrayPattern <SIsampled, sample_c_d, addr_type>; 1483} 1484 1485defm : SamplePatterns<IMAGE_SAMPLE_V4_V2, IMAGE_SAMPLE_C_V4_V2, 1486 IMAGE_SAMPLE_L_V4_V2, IMAGE_SAMPLE_C_L_V4_V2, 1487 IMAGE_SAMPLE_B_V4_V2, IMAGE_SAMPLE_C_B_V4_V2, 1488 IMAGE_SAMPLE_D_V4_V2, IMAGE_SAMPLE_C_D_V4_V2, 1489 v2i32>; 1490defm : SamplePatterns<IMAGE_SAMPLE_V4_V4, IMAGE_SAMPLE_C_V4_V4, 1491 IMAGE_SAMPLE_L_V4_V4, IMAGE_SAMPLE_C_L_V4_V4, 1492 IMAGE_SAMPLE_B_V4_V4, IMAGE_SAMPLE_C_B_V4_V4, 1493 IMAGE_SAMPLE_D_V4_V4, IMAGE_SAMPLE_C_D_V4_V4, 1494 v4i32>; 1495defm : SamplePatterns<IMAGE_SAMPLE_V4_V8, IMAGE_SAMPLE_C_V4_V8, 1496 IMAGE_SAMPLE_L_V4_V8, IMAGE_SAMPLE_C_L_V4_V8, 1497 IMAGE_SAMPLE_B_V4_V8, IMAGE_SAMPLE_C_B_V4_V8, 1498 IMAGE_SAMPLE_D_V4_V8, IMAGE_SAMPLE_C_D_V4_V8, 1499 v8i32>; 1500defm : SamplePatterns<IMAGE_SAMPLE_V4_V16, IMAGE_SAMPLE_C_V4_V16, 1501 IMAGE_SAMPLE_L_V4_V16, IMAGE_SAMPLE_C_L_V4_V16, 1502 IMAGE_SAMPLE_B_V4_V16, IMAGE_SAMPLE_C_B_V4_V16, 1503 IMAGE_SAMPLE_D_V4_V16, IMAGE_SAMPLE_C_D_V4_V16, 1504 v16i32>; 1505 1506/* int_SI_imageload for texture fetches consuming varying address parameters */ 1507class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1508 (name addr_type:$addr, v32i8:$rsrc, imm), 1509 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1510>; 1511 1512class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1513 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY), 1514 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1515>; 1516 1517class ImageLoadMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1518 (name addr_type:$addr, v32i8:$rsrc, TEX_MSAA), 1519 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1520>; 1521 1522class ImageLoadArrayMSAAPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1523 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY_MSAA), 1524 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1525>; 1526 1527multiclass ImageLoadPatterns<MIMG opcode, ValueType addr_type> { 1528 def : ImageLoadPattern <int_SI_imageload, opcode, addr_type>; 1529 def : ImageLoadArrayPattern <int_SI_imageload, opcode, addr_type>; 1530} 1531 1532multiclass ImageLoadMSAAPatterns<MIMG opcode, ValueType addr_type> { 1533 def : ImageLoadMSAAPattern <int_SI_imageload, opcode, addr_type>; 1534 def : ImageLoadArrayMSAAPattern <int_SI_imageload, opcode, addr_type>; 1535} 1536 1537defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V2, v2i32>; 1538defm : ImageLoadPatterns<IMAGE_LOAD_MIP_V4_V4, v4i32>; 1539 1540defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V2, v2i32>; 1541defm : ImageLoadMSAAPatterns<IMAGE_LOAD_V4_V4, v4i32>; 1542 1543/* Image resource information */ 1544def : Pat < 1545 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm), 1546 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1547>; 1548 1549def : Pat < 1550 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY), 1551 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1552>; 1553 1554def : Pat < 1555 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY_MSAA), 1556 (IMAGE_GET_RESINFO_V4_V1 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1557>; 1558 1559/********** ============================================ **********/ 1560/********** Extraction, Insertion, Building and Casting **********/ 1561/********** ============================================ **********/ 1562 1563foreach Index = 0-2 in { 1564 def Extract_Element_v2i32_#Index : Extract_Element < 1565 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1566 >; 1567 def Insert_Element_v2i32_#Index : Insert_Element < 1568 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1569 >; 1570 1571 def Extract_Element_v2f32_#Index : Extract_Element < 1572 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1573 >; 1574 def Insert_Element_v2f32_#Index : Insert_Element < 1575 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1576 >; 1577} 1578 1579foreach Index = 0-3 in { 1580 def Extract_Element_v4i32_#Index : Extract_Element < 1581 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1582 >; 1583 def Insert_Element_v4i32_#Index : Insert_Element < 1584 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1585 >; 1586 1587 def Extract_Element_v4f32_#Index : Extract_Element < 1588 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1589 >; 1590 def Insert_Element_v4f32_#Index : Insert_Element < 1591 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1592 >; 1593} 1594 1595foreach Index = 0-7 in { 1596 def Extract_Element_v8i32_#Index : Extract_Element < 1597 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1598 >; 1599 def Insert_Element_v8i32_#Index : Insert_Element < 1600 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1601 >; 1602 1603 def Extract_Element_v8f32_#Index : Extract_Element < 1604 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1605 >; 1606 def Insert_Element_v8f32_#Index : Insert_Element < 1607 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1608 >; 1609} 1610 1611foreach Index = 0-15 in { 1612 def Extract_Element_v16i32_#Index : Extract_Element < 1613 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1614 >; 1615 def Insert_Element_v16i32_#Index : Insert_Element < 1616 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1617 >; 1618 1619 def Extract_Element_v16f32_#Index : Extract_Element < 1620 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1621 >; 1622 def Insert_Element_v16f32_#Index : Insert_Element < 1623 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1624 >; 1625} 1626 1627def : BitConvert <i32, f32, SReg_32>; 1628def : BitConvert <i32, f32, VReg_32>; 1629 1630def : BitConvert <f32, i32, SReg_32>; 1631def : BitConvert <f32, i32, VReg_32>; 1632 1633def : BitConvert <i64, f64, VReg_64>; 1634 1635def : BitConvert <f64, i64, VReg_64>; 1636 1637def : BitConvert <v2f32, v2i32, VReg_64>; 1638def : BitConvert <v2i32, v2f32, VReg_64>; 1639def : BitConvert <v2i32, i64, VReg_64>; 1640 1641def : BitConvert <v4f32, v4i32, VReg_128>; 1642def : BitConvert <v4i32, v4f32, VReg_128>; 1643def : BitConvert <v4i32, i128, VReg_128>; 1644def : BitConvert <i128, v4i32, VReg_128>; 1645 1646def : BitConvert <v8i32, v32i8, SReg_256>; 1647def : BitConvert <v32i8, v8i32, SReg_256>; 1648def : BitConvert <v8i32, v32i8, VReg_256>; 1649def : BitConvert <v32i8, v8i32, VReg_256>; 1650 1651/********** =================== **********/ 1652/********** Src & Dst modifiers **********/ 1653/********** =================== **********/ 1654 1655def : Pat < 1656 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1657 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1658 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1659>; 1660 1661def : Pat < 1662 (fabs f32:$src), 1663 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1664 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1665>; 1666 1667def : Pat < 1668 (fneg f32:$src), 1669 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1670 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */) 1671>; 1672 1673/********** ================== **********/ 1674/********** Immediate Patterns **********/ 1675/********** ================== **********/ 1676 1677def : Pat < 1678 (SGPRImm<(i32 imm)>:$imm), 1679 (S_MOV_B32 imm:$imm) 1680>; 1681 1682def : Pat < 1683 (SGPRImm<(f32 fpimm)>:$imm), 1684 (S_MOV_B32 fpimm:$imm) 1685>; 1686 1687def : Pat < 1688 (i32 imm:$imm), 1689 (V_MOV_B32_e32 imm:$imm) 1690>; 1691 1692def : Pat < 1693 (f32 fpimm:$imm), 1694 (V_MOV_B32_e32 fpimm:$imm) 1695>; 1696 1697def : Pat < 1698 (i1 imm:$imm), 1699 (S_MOV_B64 imm:$imm) 1700>; 1701 1702def : Pat < 1703 (i64 InlineImm<i64>:$imm), 1704 (S_MOV_B64 InlineImm<i64>:$imm) 1705>; 1706 1707// i64 immediates aren't supported in hardware, split it into two 32bit values 1708def : Pat < 1709 (i64 imm:$imm), 1710 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1711 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0), 1712 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1) 1713>; 1714 1715def : Pat < 1716 (f64 fpimm:$imm), 1717 (INSERT_SUBREG (INSERT_SUBREG (f64 (IMPLICIT_DEF)), 1718 (V_MOV_B32_e32 (f32 (LO32f fpimm:$imm))), sub0), 1719 (V_MOV_B32_e32 (f32 (HI32f fpimm:$imm))), sub1) 1720>; 1721 1722/********** ===================== **********/ 1723/********** Interpolation Paterns **********/ 1724/********** ===================== **********/ 1725 1726def : Pat < 1727 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params), 1728 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params) 1729>; 1730 1731def : Pat < 1732 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij), 1733 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0), 1734 imm:$attr_chan, imm:$attr, i32:$params), 1735 (EXTRACT_SUBREG $ij, sub1), 1736 imm:$attr_chan, imm:$attr, $params) 1737>; 1738 1739/********** ================== **********/ 1740/********** Intrinsic Patterns **********/ 1741/********** ================== **********/ 1742 1743/* llvm.AMDGPU.pow */ 1744def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 1745 1746def : Pat < 1747 (int_AMDGPU_div f32:$src0, f32:$src1), 1748 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) 1749>; 1750 1751def : Pat< 1752 (fdiv f32:$src0, f32:$src1), 1753 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1)) 1754>; 1755 1756def : Pat< 1757 (fdiv f64:$src0, f64:$src1), 1758 (V_MUL_F64 $src0, (V_RCP_F64_e32 $src1), (i64 0)) 1759>; 1760 1761def : Pat < 1762 (fcos f32:$src0), 1763 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1764>; 1765 1766def : Pat < 1767 (fsin f32:$src0), 1768 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1769>; 1770 1771def : Pat < 1772 (int_AMDGPU_cube v4f32:$src), 1773 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 1774 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), 1775 (EXTRACT_SUBREG $src, sub1), 1776 (EXTRACT_SUBREG $src, sub2)), 1777 sub0), 1778 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), 1779 (EXTRACT_SUBREG $src, sub1), 1780 (EXTRACT_SUBREG $src, sub2)), 1781 sub1), 1782 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), 1783 (EXTRACT_SUBREG $src, sub1), 1784 (EXTRACT_SUBREG $src, sub2)), 1785 sub2), 1786 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), 1787 (EXTRACT_SUBREG $src, sub1), 1788 (EXTRACT_SUBREG $src, sub2)), 1789 sub3) 1790>; 1791 1792def : Pat < 1793 (i32 (sext i1:$src0)), 1794 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 1795>; 1796 1797// 1. Offset as 8bit DWORD immediate 1798def : Pat < 1799 (SIload_constant i128:$sbase, IMM8bitDWORD:$offset), 1800 (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset) 1801>; 1802 1803// 2. Offset loaded in an 32bit SGPR 1804def : Pat < 1805 (SIload_constant i128:$sbase, imm:$offset), 1806 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) 1807>; 1808 1809// 3. Offset in an 32Bit VGPR 1810def : Pat < 1811 (SIload_constant i128:$sbase, i32:$voff), 1812 (BUFFER_LOAD_DWORD_OFFEN $sbase, $voff) 1813>; 1814 1815// The multiplication scales from [0,1] to the unsigned integer range 1816def : Pat < 1817 (AMDGPUurecip i32:$src0), 1818 (V_CVT_U32_F32_e32 1819 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 1820 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 1821>; 1822 1823def : Pat < 1824 (int_SI_tid), 1825 (V_MBCNT_HI_U32_B32_e32 0xffffffff, 1826 (V_MBCNT_LO_U32_B32_e64 0xffffffff, 0, 0, 0, 0, 0)) 1827>; 1828 1829/********** ================== **********/ 1830/********** VOP3 Patterns **********/ 1831/********** ================== **********/ 1832 1833def : Pat < 1834 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)), 1835 (V_MAD_F32 $src0, $src1, $src2) 1836>; 1837 1838/********** ======================= **********/ 1839/********** Load/Store Patterns **********/ 1840/********** ======================= **********/ 1841 1842class DSReadPat <DS inst, ValueType vt, PatFrag frag> : Pat < 1843 (frag i32:$src0), 1844 (vt (inst 0, $src0, $src0, $src0, 0, 0)) 1845>; 1846 1847def : DSReadPat <DS_READ_I8, i32, sextloadi8_local>; 1848def : DSReadPat <DS_READ_U8, i32, az_extloadi8_local>; 1849def : DSReadPat <DS_READ_I16, i32, sextloadi16_local>; 1850def : DSReadPat <DS_READ_U16, i32, az_extloadi16_local>; 1851def : DSReadPat <DS_READ_B32, i32, local_load>; 1852def : Pat < 1853 (local_load i32:$src0), 1854 (i32 (DS_READ_B32 0, $src0, $src0, $src0, 0, 0)) 1855>; 1856 1857class DSWritePat <DS inst, ValueType vt, PatFrag frag> : Pat < 1858 (frag i32:$src1, i32:$src0), 1859 (inst 0, $src0, $src1, $src1, 0, 0) 1860>; 1861 1862def : DSWritePat <DS_WRITE_B8, i32, truncstorei8_local>; 1863def : DSWritePat <DS_WRITE_B16, i32, truncstorei16_local>; 1864def : DSWritePat <DS_WRITE_B32, i32, local_store>; 1865 1866def : Pat <(atomic_load_add_local i32:$ptr, i32:$val), 1867 (DS_ADD_U32_RTN 0, $ptr, $val, 0, 0)>; 1868 1869def : Pat <(atomic_load_sub_local i32:$ptr, i32:$val), 1870 (DS_SUB_U32_RTN 0, $ptr, $val, 0, 0)>; 1871 1872/********** ================== **********/ 1873/********** SMRD Patterns **********/ 1874/********** ================== **********/ 1875 1876multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1877 1878 // 1. Offset as 8bit DWORD immediate 1879 def : Pat < 1880 (constant_load (SIadd64bit32bit i64:$sbase, IMM8bitDWORD:$offset)), 1881 (vt (Instr_IMM $sbase, IMM8bitDWORD:$offset)) 1882 >; 1883 1884 // 2. Offset loaded in an 32bit SGPR 1885 def : Pat < 1886 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)), 1887 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset))) 1888 >; 1889 1890 // 3. No offset at all 1891 def : Pat < 1892 (constant_load i64:$sbase), 1893 (vt (Instr_IMM $sbase, 0)) 1894 >; 1895} 1896 1897defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1898defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1899defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, i64>; 1900defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>; 1901defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, i128>; 1902defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>; 1903defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1904defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>; 1905defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>; 1906 1907//===----------------------------------------------------------------------===// 1908// MUBUF Patterns 1909//===----------------------------------------------------------------------===// 1910 1911multiclass MUBUFLoad_Pattern <MUBUF Instr_ADDR64, ValueType vt, 1912 PatFrag global_ld, PatFrag constant_ld> { 1913 def : Pat < 1914 (vt (global_ld (add i64:$ptr, (i64 IMM12bit:$offset)))), 1915 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, (as_i16imm $offset)) 1916 >; 1917 1918 def : Pat < 1919 (vt (global_ld i64:$ptr)), 1920 (Instr_ADDR64 (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1921 >; 1922 1923 def : Pat < 1924 (vt (global_ld (add i64:$ptr, i64:$offset))), 1925 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1926 >; 1927 1928 def : Pat < 1929 (vt (constant_ld (add i64:$ptr, i64:$offset))), 1930 (Instr_ADDR64 (SI_ADDR64_RSRC $ptr), $offset, 0) 1931 >; 1932} 1933 1934defm : MUBUFLoad_Pattern <BUFFER_LOAD_SBYTE_ADDR64, i32, 1935 sextloadi8_global, sextloadi8_constant>; 1936defm : MUBUFLoad_Pattern <BUFFER_LOAD_UBYTE_ADDR64, i32, 1937 az_extloadi8_global, az_extloadi8_constant>; 1938defm : MUBUFLoad_Pattern <BUFFER_LOAD_SSHORT_ADDR64, i32, 1939 sextloadi16_global, sextloadi16_constant>; 1940defm : MUBUFLoad_Pattern <BUFFER_LOAD_USHORT_ADDR64, i32, 1941 az_extloadi16_global, az_extloadi16_constant>; 1942defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORD_ADDR64, i32, 1943 global_load, constant_load>; 1944defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1945 global_load, constant_load>; 1946defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, i64, 1947 az_extloadi32_global, az_extloadi32_constant>; 1948defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX2_ADDR64, v2i32, 1949 global_load, constant_load>; 1950defm : MUBUFLoad_Pattern <BUFFER_LOAD_DWORDX4_ADDR64, v4i32, 1951 global_load, constant_load>; 1952 1953multiclass MUBUFStore_Pattern <MUBUF Instr, ValueType vt, PatFrag st> { 1954 1955 def : Pat < 1956 (st vt:$value, i64:$ptr), 1957 (Instr $value, (SI_ADDR64_RSRC (i64 0)), $ptr, 0) 1958 >; 1959 1960 def : Pat < 1961 (st vt:$value, (add i64:$ptr, i64:$offset)), 1962 (Instr $value, (SI_ADDR64_RSRC $ptr), $offset, 0) 1963 >; 1964} 1965 1966defm : MUBUFStore_Pattern <BUFFER_STORE_BYTE, i32, truncstorei8_global>; 1967defm : MUBUFStore_Pattern <BUFFER_STORE_SHORT, i32, truncstorei16_global>; 1968defm : MUBUFStore_Pattern <BUFFER_STORE_DWORD, i32, global_store>; 1969defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, i64, global_store>; 1970defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX2, v2i32, global_store>; 1971defm : MUBUFStore_Pattern <BUFFER_STORE_DWORDX4, v4i32, global_store>; 1972 1973//===----------------------------------------------------------------------===// 1974// MTBUF Patterns 1975//===----------------------------------------------------------------------===// 1976 1977// TBUFFER_STORE_FORMAT_*, addr64=0 1978class MTBUF_StoreResource <ValueType vt, int num_channels, MTBUF opcode> : Pat< 1979 (SItbuffer_store i128:$rsrc, vt:$vdata, num_channels, i32:$vaddr, 1980 i32:$soffset, imm:$inst_offset, imm:$dfmt, 1981 imm:$nfmt, imm:$offen, imm:$idxen, 1982 imm:$glc, imm:$slc, imm:$tfe), 1983 (opcode 1984 $vdata, (as_i16imm $inst_offset), (as_i1imm $offen), (as_i1imm $idxen), 1985 (as_i1imm $glc), 0, (as_i8imm $dfmt), (as_i8imm $nfmt), $vaddr, $rsrc, 1986 (as_i1imm $slc), (as_i1imm $tfe), $soffset) 1987>; 1988 1989def : MTBUF_StoreResource <i32, 1, TBUFFER_STORE_FORMAT_X>; 1990def : MTBUF_StoreResource <v2i32, 2, TBUFFER_STORE_FORMAT_XY>; 1991def : MTBUF_StoreResource <v4i32, 3, TBUFFER_STORE_FORMAT_XYZ>; 1992def : MTBUF_StoreResource <v4i32, 4, TBUFFER_STORE_FORMAT_XYZW>; 1993 1994/********** ====================== **********/ 1995/********** Indirect adressing **********/ 1996/********** ====================== **********/ 1997 1998multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> { 1999 2000 // 1. Extract with offset 2001 def : Pat< 2002 (vector_extract vt:$vec, (add i32:$idx, imm:$off)), 2003 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off)) 2004 >; 2005 2006 // 2. Extract without offset 2007 def : Pat< 2008 (vector_extract vt:$vec, i32:$idx), 2009 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) 2010 >; 2011 2012 // 3. Insert with offset 2013 def : Pat< 2014 (vector_insert vt:$vec, f32:$val, (add i32:$idx, imm:$off)), 2015 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) 2016 >; 2017 2018 // 4. Insert without offset 2019 def : Pat< 2020 (vector_insert vt:$vec, f32:$val, i32:$idx), 2021 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) 2022 >; 2023} 2024 2025defm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>; 2026defm : SI_INDIRECT_Pattern <v4f32, SI_INDIRECT_DST_V4>; 2027defm : SI_INDIRECT_Pattern <v8f32, SI_INDIRECT_DST_V8>; 2028defm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>; 2029 2030/********** =============== **********/ 2031/********** Conditions **********/ 2032/********** =============== **********/ 2033 2034def : Pat< 2035 (i1 (setcc f32:$src0, f32:$src1, SETO)), 2036 (V_CMP_O_F32_e64 $src0, $src1) 2037>; 2038 2039def : Pat< 2040 (i1 (setcc f32:$src0, f32:$src1, SETUO)), 2041 (V_CMP_U_F32_e64 $src0, $src1) 2042>; 2043 2044//===----------------------------------------------------------------------===// 2045// Miscellaneous Patterns 2046//===----------------------------------------------------------------------===// 2047 2048def : Pat < 2049 (i64 (trunc i128:$x)), 2050 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 2051 (i32 (EXTRACT_SUBREG $x, sub0)), sub0), 2052 (i32 (EXTRACT_SUBREG $x, sub1)), sub1) 2053>; 2054 2055def : Pat < 2056 (i32 (trunc i64:$a)), 2057 (EXTRACT_SUBREG $a, sub0) 2058>; 2059 2060// V_ADD_I32_e32/S_ADD_I32 produces carry in VCC/SCC. For the vector 2061// case, the sgpr-copies pass will fix this to use the vector version. 2062def : Pat < 2063 (i32 (addc i32:$src0, i32:$src1)), 2064 (S_ADD_I32 $src0, $src1) 2065>; 2066 2067def : Pat < 2068 (or i64:$a, i64:$b), 2069 (INSERT_SUBREG 2070 (INSERT_SUBREG (IMPLICIT_DEF), 2071 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub0), (EXTRACT_SUBREG $b, sub0)), sub0), 2072 (V_OR_B32_e32 (EXTRACT_SUBREG $a, sub1), (EXTRACT_SUBREG $b, sub1)), sub1) 2073>; 2074 2075//============================================================================// 2076// Miscellaneous Optimization Patterns 2077//============================================================================// 2078 2079def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>; 2080 2081} // End isSI predicate 2082