SIInstructions.td revision 256281
1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This file was originally auto-generated from a GPU register header file and 10// all the instruction definitions were originally commented out. Instructions 11// that are not yet supported remain commented out. 12//===----------------------------------------------------------------------===// 13 14class InterpSlots { 15int P0 = 2; 16int P10 = 0; 17int P20 = 1; 18} 19def INTERP : InterpSlots; 20 21def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23} 24 25def isSI : Predicate<"Subtarget.device()" 26 "->getGeneration() == AMDGPUDeviceInfo::HD7XXX">; 27 28let Predicates = [isSI] in { 29 30let neverHasSideEffects = 1 in { 31 32let isMoveImm = 1 in { 33def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 34def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 35def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 36def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 37} // End isMoveImm = 1 38 39def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 40def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 41def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 42def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 43def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 44def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 45} // End neverHasSideEffects = 1 46 47////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 48////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 49////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 50////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 51////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 52////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 53////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 54////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 55//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 56//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 57def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 58//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 59//def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 60//def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 61////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 62////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 63////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 64////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 65def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 66def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 67def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 68def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 69 70let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 71 72def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 73def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 74def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 75def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 76def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 77def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 78def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 79def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 80 81} // End hasSideEffects = 1 82 83def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 84def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 85def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 86def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 87def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 88def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 89//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 90def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 91def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 92def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 93def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 94def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 95 96/* 97This instruction is disabled for now until we can figure out how to teach 98the instruction selector to correctly use the S_CMP* vs V_CMP* 99instructions. 100 101When this instruction is enabled the code generator sometimes produces this 102invalid sequence: 103 104SCC = S_CMPK_EQ_I32 SGPR0, imm 105VCC = COPY SCC 106VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 107 108def S_CMPK_EQ_I32 : SOPK < 109 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 110 "S_CMPK_EQ_I32", 111 [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))] 112>; 113*/ 114 115let isCompare = 1 in { 116def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 117def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 118def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 119def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 120def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 121def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 122def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 123def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 124def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 125def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 126def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 127} // End isCompare = 1 128 129def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 130def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 131//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 132def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 133def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 134def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 135//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 136//def EXP : EXP_ <0x00000000, "EXP", []>; 137 138let isCompare = 1 in { 139 140defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 141defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_LT>; 142defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_EQ>; 143defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_LE>; 144defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_GT>; 145defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", f32, COND_NE>; 146defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_GE>; 147defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32">; 148defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32">; 149defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 150defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 151defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 152defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 153defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_NE>; 154defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 155defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 156 157let hasSideEffects = 1, Defs = [EXEC] in { 158 159defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 160defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 161defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 162defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 163defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 164defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 165defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 166defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 167defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 168defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 169defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 170defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 171defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 172defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 173defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 174defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 175 176} // End hasSideEffects = 1, Defs = [EXEC] 177 178defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 179defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64">; 180defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64">; 181defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64">; 182defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64">; 183defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 184defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64">; 185defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64">; 186defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64">; 187defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 188defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 189defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 190defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 191defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64">; 192defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 193defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 194 195let hasSideEffects = 1, Defs = [EXEC] in { 196 197defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 198defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 199defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 200defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 201defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 202defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 203defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 204defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 205defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 206defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 207defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 208defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 209defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 210defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 211defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 212defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 213 214} // End hasSideEffects = 1, Defs = [EXEC] 215 216defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 217defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 218defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 219defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 220defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 221defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 222defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 223defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 224defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 225defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 226defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 227defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 228defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 229defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 230defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 231defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 232 233let hasSideEffects = 1, Defs = [EXEC] in { 234 235defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 236defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 237defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 238defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 239defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 240defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 241defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 242defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 243defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 244defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 245defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 246defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 247defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 248defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 249defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 250defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 251 252} // End hasSideEffects = 1, Defs = [EXEC] 253 254defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 255defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 256defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 257defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 258defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 259defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 260defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 261defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 262defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 263defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 264defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 265defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 266defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 267defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 268defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 269defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 270 271let hasSideEffects = 1, Defs = [EXEC] in { 272 273defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 274defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 275defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 276defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 277defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 278defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 279defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 280defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 281defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 282defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 283defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 284defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 285defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 286defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 287defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 288defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 289 290} // End hasSideEffects = 1, Defs = [EXEC] 291 292defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 293defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_LT>; 294defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 295defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_LE>; 296defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_GT>; 297defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 298defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_GE>; 299defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 300 301let hasSideEffects = 1, Defs = [EXEC] in { 302 303defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 304defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 305defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 306defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 307defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 308defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 309defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 310defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 311 312} // End hasSideEffects = 1, Defs = [EXEC] 313 314defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 315defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64">; 316defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64">; 317defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64">; 318defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64">; 319defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64">; 320defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64">; 321defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 322 323let hasSideEffects = 1, Defs = [EXEC] in { 324 325defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 326defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 327defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 328defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 329defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 330defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 331defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 332defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 333 334} // End hasSideEffects = 1, Defs = [EXEC] 335 336defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 337defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32">; 338defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32">; 339defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32">; 340defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32">; 341defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32">; 342defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32">; 343defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 344 345let hasSideEffects = 1, Defs = [EXEC] in { 346 347defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 348defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 349defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 350defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 351defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 352defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 353defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 354defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 355 356} // End hasSideEffects = 1, Defs = [EXEC] 357 358defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 359defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64">; 360defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64">; 361defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64">; 362defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64">; 363defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64">; 364defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64">; 365defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 366 367let hasSideEffects = 1, Defs = [EXEC] in { 368 369defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 370defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 371defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 372defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 373defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 374defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 375defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 376defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 377 378} // End hasSideEffects = 1, Defs = [EXEC] 379 380defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 381 382let hasSideEffects = 1, Defs = [EXEC] in { 383defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 384} // End hasSideEffects = 1, Defs = [EXEC] 385 386defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 387 388let hasSideEffects = 1, Defs = [EXEC] in { 389defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 390} // End hasSideEffects = 1, Defs = [EXEC] 391 392} // End isCompare = 1 393 394//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 395//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 396//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 397def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 398//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 399//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 400//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 401//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 402//def BUFFER_LOAD_UBYTE : MUBUF_ <0x00000008, "BUFFER_LOAD_UBYTE", []>; 403//def BUFFER_LOAD_SBYTE : MUBUF_ <0x00000009, "BUFFER_LOAD_SBYTE", []>; 404//def BUFFER_LOAD_USHORT : MUBUF_ <0x0000000a, "BUFFER_LOAD_USHORT", []>; 405//def BUFFER_LOAD_SSHORT : MUBUF_ <0x0000000b, "BUFFER_LOAD_SSHORT", []>; 406def BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 407def BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 408def BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 409//def BUFFER_STORE_BYTE : MUBUF_ <0x00000018, "BUFFER_STORE_BYTE", []>; 410//def BUFFER_STORE_SHORT : MUBUF_ <0x0000001a, "BUFFER_STORE_SHORT", []>; 411 412def BUFFER_STORE_DWORD : MUBUF_Store_Helper < 413 0x0000001c, "BUFFER_STORE_DWORD", VReg_32, i32 414>; 415 416def BUFFER_STORE_DWORDX2 : MUBUF_Store_Helper < 417 0x0000001d, "BUFFER_STORE_DWORDX2", VReg_64, i64 418>; 419//def BUFFER_STORE_DWORDX4 : MUBUF_DWORDX4 <0x0000001e, "BUFFER_STORE_DWORDX4", []>; 420//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 421//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 422//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 423//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 424//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 425//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 426//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 427//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 428//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 429//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 430//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 431//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 432//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 433//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 434//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 435//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 436//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 437//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 438//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 439//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 440//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 441//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 442//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 443//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 444//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 445//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 446//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 447//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 448//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 449//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 450//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 451//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 452//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 453//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 454//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 455//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 456//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 457//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 458//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 459def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 460//def TBUFFER_STORE_FORMAT_X : MTBUF_ <0x00000004, "TBUFFER_STORE_FORMAT_X", []>; 461//def TBUFFER_STORE_FORMAT_XY : MTBUF_ <0x00000005, "TBUFFER_STORE_FORMAT_XY", []>; 462//def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>; 463//def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>; 464 465let mayLoad = 1 in { 466 467defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SReg_32>; 468defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 469defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 470defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 471defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 472 473defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 474 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SReg_32 475>; 476 477defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 478 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 479>; 480 481defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 482 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 483>; 484 485defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 486 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 487>; 488 489defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 490 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 491>; 492 493} // mayLoad = 1 494 495//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 496//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 497//def IMAGE_LOAD : MIMG_NoPattern_ <"IMAGE_LOAD", 0x00000000>; 498def IMAGE_LOAD_MIP : MIMG_NoSampler_Helper <0x00000001, "IMAGE_LOAD_MIP">; 499//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 500//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 501//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 502//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 503//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 504//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 505//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 506//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 507def IMAGE_GET_RESINFO : MIMG_NoSampler_Helper <0x0000000e, "IMAGE_GET_RESINFO">; 508//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 509//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 510//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 511//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 512//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 513//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 514//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 515//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 516//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 517//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 518//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 519//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 520//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 521//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 522//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 523//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 524//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 525def IMAGE_SAMPLE : MIMG_Sampler_Helper <0x00000020, "IMAGE_SAMPLE">; 526//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 527def IMAGE_SAMPLE_D : MIMG_Sampler_Helper <0x00000022, "IMAGE_SAMPLE_D">; 528//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 529def IMAGE_SAMPLE_L : MIMG_Sampler_Helper <0x00000024, "IMAGE_SAMPLE_L">; 530def IMAGE_SAMPLE_B : MIMG_Sampler_Helper <0x00000025, "IMAGE_SAMPLE_B">; 531//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 532//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 533def IMAGE_SAMPLE_C : MIMG_Sampler_Helper <0x00000028, "IMAGE_SAMPLE_C">; 534//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 535//def IMAGE_SAMPLE_C_D : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D", 0x0000002a>; 536//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 537def IMAGE_SAMPLE_C_L : MIMG_Sampler_Helper <0x0000002c, "IMAGE_SAMPLE_C_L">; 538def IMAGE_SAMPLE_C_B : MIMG_Sampler_Helper <0x0000002d, "IMAGE_SAMPLE_C_B">; 539//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 540//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 541//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 542//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 543//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 544//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 545//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 546//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 547//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 548//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 549//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 550//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 551//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 552//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 553//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 554//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 555//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 556//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 557//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 558//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 559//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 560//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 561//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 562//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 563//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 564//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 565//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 566//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 567//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 568//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 569//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 570//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 571//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 572//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 573//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 574//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 575//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 576//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 577//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 578//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 579//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 580//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 581//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 582//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 583//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 584//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 585//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 586//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 587//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 588//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 589//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 590//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 591//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 592//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 593 594 595let neverHasSideEffects = 1, isMoveImm = 1 in { 596defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 597} // End neverHasSideEffects = 1, isMoveImm = 1 598 599defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; 600//defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>; 601//defm V_CVT_F64_I32 : VOP1_64 <0x00000004, "V_CVT_F64_I32", []>; 602defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 603 [(set f32:$dst, (sint_to_fp i32:$src0))] 604>; 605defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", 606 [(set f32:$dst, (uint_to_fp i32:$src0))] 607>; 608defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", []>; 609defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 610 [(set i32:$dst, (fp_to_sint f32:$src0))] 611>; 612defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 613////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 614//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 615//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 616//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 617//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 618//defm V_CVT_F32_F64 : VOP1_32 <0x0000000f, "V_CVT_F32_F64", []>; 619//defm V_CVT_F64_F32 : VOP1_64 <0x00000010, "V_CVT_F64_F32", []>; 620//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 621//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 622//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 623//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 624//defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 625//defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 626defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 627 [(set f32:$dst, (AMDGPUfract f32:$src0))] 628>; 629defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", 630 [(set f32:$dst, (int_AMDGPU_trunc f32:$src0))] 631>; 632defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 633 [(set f32:$dst, (fceil f32:$src0))] 634>; 635defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 636 [(set f32:$dst, (frint f32:$src0))] 637>; 638defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 639 [(set f32:$dst, (ffloor f32:$src0))] 640>; 641defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 642 [(set f32:$dst, (fexp2 f32:$src0))] 643>; 644defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 645defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 646 [(set f32:$dst, (flog2 f32:$src0))] 647>; 648defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 649defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 650defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 651 [(set f32:$dst, (fdiv FP_ONE, f32:$src0))] 652>; 653defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 654defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 655defm V_RSQ_LEGACY_F32 : VOP1_32 < 656 0x0000002d, "V_RSQ_LEGACY_F32", 657 [(set f32:$dst, (int_AMDGPU_rsq f32:$src0))] 658>; 659defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 660defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", []>; 661defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 662defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 663defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 664defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", []>; 665defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", []>; 666defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 667defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 668defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 669defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 670defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 671defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 672defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 673//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 674defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 675defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 676//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 677defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 678//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 679defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 680defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 681defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 682 683def V_INTERP_P1_F32 : VINTRP < 684 0x00000000, 685 (outs VReg_32:$dst), 686 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 687 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 688 []> { 689 let DisableEncoding = "$m0"; 690} 691 692def V_INTERP_P2_F32 : VINTRP < 693 0x00000001, 694 (outs VReg_32:$dst), 695 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 696 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 697 []> { 698 699 let Constraints = "$src0 = $dst"; 700 let DisableEncoding = "$src0,$m0"; 701 702} 703 704def V_INTERP_MOV_F32 : VINTRP < 705 0x00000002, 706 (outs VReg_32:$dst), 707 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 708 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 709 []> { 710 let DisableEncoding = "$m0"; 711} 712 713//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 714 715let isTerminator = 1 in { 716 717def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 718 [(IL_retflag)]> { 719 let SIMM16 = 0; 720 let isBarrier = 1; 721 let hasCtrlDep = 1; 722} 723 724let isBranch = 1 in { 725def S_BRANCH : SOPP < 726 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 727 [(br bb:$target)]> { 728 let isBarrier = 1; 729} 730 731let DisableEncoding = "$scc" in { 732def S_CBRANCH_SCC0 : SOPP < 733 0x00000004, (ins brtarget:$target, SCCReg:$scc), 734 "S_CBRANCH_SCC0 $target", [] 735>; 736def S_CBRANCH_SCC1 : SOPP < 737 0x00000005, (ins brtarget:$target, SCCReg:$scc), 738 "S_CBRANCH_SCC1 $target", 739 [] 740>; 741} // End DisableEncoding = "$scc" 742 743def S_CBRANCH_VCCZ : SOPP < 744 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 745 "S_CBRANCH_VCCZ $target", 746 [] 747>; 748def S_CBRANCH_VCCNZ : SOPP < 749 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 750 "S_CBRANCH_VCCNZ $target", 751 [] 752>; 753 754let DisableEncoding = "$exec" in { 755def S_CBRANCH_EXECZ : SOPP < 756 0x00000008, (ins brtarget:$target, EXECReg:$exec), 757 "S_CBRANCH_EXECZ $target", 758 [] 759>; 760def S_CBRANCH_EXECNZ : SOPP < 761 0x00000009, (ins brtarget:$target, EXECReg:$exec), 762 "S_CBRANCH_EXECNZ $target", 763 [] 764>; 765} // End DisableEncoding = "$exec" 766 767 768} // End isBranch = 1 769} // End isTerminator = 1 770 771//def S_BARRIER : SOPP_ <0x0000000a, "S_BARRIER", []>; 772let hasSideEffects = 1 in { 773def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16", 774 [] 775>; 776} // End hasSideEffects 777//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 778//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 779//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 780//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>; 781//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 782//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 783//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 784//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 785//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 786//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 787 788def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 789 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 790 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 791 [] 792>{ 793 let DisableEncoding = "$vcc"; 794} 795 796def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 797 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 798 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 799 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 800 [(set i32:$dst, (select i1:$src2, i32:$src1, i32:$src0))] 801>; 802 803//f32 pattern for V_CNDMASK_B32_e64 804def : Pat < 805 (f32 (select i1:$src2, f32:$src1, f32:$src0)), 806 (V_CNDMASK_B32_e64 $src0, $src1, $src2) 807>; 808 809defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; 810defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; 811 812let isCommutable = 1 in { 813defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 814 [(set f32:$dst, (fadd f32:$src0, f32:$src1))] 815>; 816 817defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 818 [(set f32:$dst, (fsub f32:$src0, f32:$src1))] 819>; 820defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; 821} // End isCommutable = 1 822 823defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 824 825let isCommutable = 1 in { 826 827defm V_MUL_LEGACY_F32 : VOP2_32 < 828 0x00000007, "V_MUL_LEGACY_F32", 829 [(set f32:$dst, (int_AMDGPU_mul f32:$src0, f32:$src1))] 830>; 831 832defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 833 [(set f32:$dst, (fmul f32:$src0, f32:$src1))] 834>; 835 836} // End isCommutable = 1 837 838//defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", []>; 839//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 840//defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", []>; 841//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 842 843let isCommutable = 1 in { 844 845defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 846 [(set f32:$dst, (AMDGPUfmin f32:$src0, f32:$src1))] 847>; 848 849defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 850 [(set f32:$dst, (AMDGPUfmax f32:$src0, f32:$src1))] 851>; 852 853defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 854defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 855defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", 856 [(set i32:$dst, (AMDGPUsmin i32:$src0, i32:$src1))] 857>; 858defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", 859 [(set i32:$dst, (AMDGPUsmax i32:$src0, i32:$src1))] 860>; 861defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", 862 [(set i32:$dst, (AMDGPUumin i32:$src0, i32:$src1))] 863>; 864defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", 865 [(set i32:$dst, (AMDGPUumax i32:$src0, i32:$src1))] 866>; 867 868defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", 869 [(set i32:$dst, (srl i32:$src0, i32:$src1))] 870>; 871defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; 872 873defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", 874 [(set i32:$dst, (sra i32:$src0, i32:$src1))] 875>; 876defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; 877 878defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", 879 [(set i32:$dst, (shl i32:$src0, i32:$src1))] 880>; 881defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; 882 883defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", 884 [(set i32:$dst, (and i32:$src0, i32:$src1))] 885>; 886defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", 887 [(set i32:$dst, (or i32:$src0, i32:$src1))] 888>; 889defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", 890 [(set i32:$dst, (xor i32:$src0, i32:$src1))] 891>; 892 893} // End isCommutable = 1 894 895defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; 896defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 897defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 898defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 899//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 900//defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 901//defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 902 903let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC 904defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", 905 [(set i32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))] 906>; 907 908defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", 909 [(set i32:$dst, (sub i32:$src0, i32:$src1))] 910>; 911defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">; 912 913let Uses = [VCC] in { // Carry-out comes from VCC 914defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>; 915defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>; 916defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">; 917} // End Uses = [VCC] 918} // End isCommutable = 1, Defs = [VCC] 919 920defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 921////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 922////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 923////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 924defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 925 [(set i32:$dst, (int_SI_packf16 f32:$src0, f32:$src1))] 926>; 927////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 928////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 929def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 930def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 931def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 932def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 933def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 934def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 935def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 936def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 937def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 938def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 939def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 940def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 941////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 942////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 943////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 944////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 945//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 946 947let neverHasSideEffects = 1 in { 948 949def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 950def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 951//def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", []>; 952//def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", []>; 953 954} // End neverHasSideEffects 955def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 956def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 957def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 958def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 959def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; 960def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; 961def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; 962defm : BFIPatterns <V_BFI_B32>; 963def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>; 964def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>; 965//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 966def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 967def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 968def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 969////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 970////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 971////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 972////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 973////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 974////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 975////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 976////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 977////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 978//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 979//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 980//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 981def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 982////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 983def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 984def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 985def V_LSHL_B64 : VOP3_64 <0x00000161, "V_LSHL_B64", []>; 986def V_LSHR_B64 : VOP3_64 <0x00000162, "V_LSHR_B64", []>; 987def V_ASHR_I64 : VOP3_64 <0x00000163, "V_ASHR_I64", []>; 988def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 989def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 990def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 991def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 992def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 993 994let isCommutable = 1 in { 995 996def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 997def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 998def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 999def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 1000 1001} // isCommutable = 1 1002 1003def : Pat < 1004 (mul i32:$src0, i32:$src1), 1005 (V_MUL_LO_I32 $src0, $src1, (i32 0)) 1006>; 1007 1008def : Pat < 1009 (mulhu i32:$src0, i32:$src1), 1010 (V_MUL_HI_U32 $src0, $src1, (i32 0)) 1011>; 1012 1013def : Pat < 1014 (mulhs i32:$src0, i32:$src1), 1015 (V_MUL_HI_I32 $src0, $src1, (i32 0)) 1016>; 1017 1018def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 1019def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 1020def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 1021def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 1022//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 1023//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 1024//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 1025def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 1026def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 1027def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 1028def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", []>; 1029def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", []>; 1030def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", []>; 1031def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", []>; 1032def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; 1033def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; 1034def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; 1035def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; 1036 1037def S_CSELECT_B32 : SOP2 < 1038 0x0000000a, (outs SReg_32:$dst), 1039 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 1040 [] 1041>; 1042 1043def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 1044 1045def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; 1046 1047def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 1048 [(set i64:$dst, (and i64:$src0, i64:$src1))] 1049>; 1050 1051def : Pat < 1052 (i1 (and i1:$src0, i1:$src1)), 1053 (S_AND_B64 $src0, $src1) 1054>; 1055 1056def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; 1057def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; 1058def : Pat < 1059 (i1 (or i1:$src0, i1:$src1)), 1060 (S_OR_B64 $src0, $src1) 1061>; 1062def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; 1063def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", []>; 1064def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 1065def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 1066def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 1067def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 1068def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 1069def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 1070def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 1071def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 1072def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 1073def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 1074def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", []>; 1075def S_LSHL_B64 : SOP2_64 <0x0000001f, "S_LSHL_B64", []>; 1076def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", []>; 1077def S_LSHR_B64 : SOP2_64 <0x00000021, "S_LSHR_B64", []>; 1078def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", []>; 1079def S_ASHR_I64 : SOP2_64 <0x00000023, "S_ASHR_I64", []>; 1080def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 1081def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 1082def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 1083def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 1084def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 1085def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 1086def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 1087//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 1088def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 1089 1090let isCodeGenOnly = 1, isPseudo = 1 in { 1091 1092def LOAD_CONST : AMDGPUShaderInst < 1093 (outs GPRF32:$dst), 1094 (ins i32imm:$src), 1095 "LOAD_CONST $dst, $src", 1096 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 1097>; 1098 1099// SI Psuedo instructions. These are used by the CFG structurizer pass 1100// and should be lowered to ISA instructions prior to codegen. 1101 1102let mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1103 Uses = [EXEC], Defs = [EXEC] in { 1104 1105let isBranch = 1, isTerminator = 1 in { 1106 1107def SI_IF : InstSI < 1108 (outs SReg_64:$dst), 1109 (ins SReg_64:$vcc, brtarget:$target), 1110 "SI_IF $dst, $vcc, $target", 1111 [(set i64:$dst, (int_SI_if i1:$vcc, bb:$target))] 1112>; 1113 1114def SI_ELSE : InstSI < 1115 (outs SReg_64:$dst), 1116 (ins SReg_64:$src, brtarget:$target), 1117 "SI_ELSE $dst, $src, $target", 1118 [(set i64:$dst, (int_SI_else i64:$src, bb:$target))]> { 1119 1120 let Constraints = "$src = $dst"; 1121} 1122 1123def SI_LOOP : InstSI < 1124 (outs), 1125 (ins SReg_64:$saved, brtarget:$target), 1126 "SI_LOOP $saved, $target", 1127 [(int_SI_loop i64:$saved, bb:$target)] 1128>; 1129 1130} // end isBranch = 1, isTerminator = 1 1131 1132def SI_BREAK : InstSI < 1133 (outs SReg_64:$dst), 1134 (ins SReg_64:$src), 1135 "SI_ELSE $dst, $src", 1136 [(set i64:$dst, (int_SI_break i64:$src))] 1137>; 1138 1139def SI_IF_BREAK : InstSI < 1140 (outs SReg_64:$dst), 1141 (ins SReg_64:$vcc, SReg_64:$src), 1142 "SI_IF_BREAK $dst, $vcc, $src", 1143 [(set i64:$dst, (int_SI_if_break i1:$vcc, i64:$src))] 1144>; 1145 1146def SI_ELSE_BREAK : InstSI < 1147 (outs SReg_64:$dst), 1148 (ins SReg_64:$src0, SReg_64:$src1), 1149 "SI_ELSE_BREAK $dst, $src0, $src1", 1150 [(set i64:$dst, (int_SI_else_break i64:$src0, i64:$src1))] 1151>; 1152 1153def SI_END_CF : InstSI < 1154 (outs), 1155 (ins SReg_64:$saved), 1156 "SI_END_CF $saved", 1157 [(int_SI_end_cf i64:$saved)] 1158>; 1159 1160def SI_KILL : InstSI < 1161 (outs), 1162 (ins VReg_32:$src), 1163 "SI_KIL $src", 1164 [(int_AMDGPU_kill f32:$src)] 1165>; 1166 1167} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1168 // Uses = [EXEC], Defs = [EXEC] 1169 1170let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1171 1172def SI_INDIRECT_SRC : InstSI < 1173 (outs VReg_32:$dst, SReg_64:$temp), 1174 (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1175 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1176 [] 1177>; 1178 1179class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1180 (outs rc:$dst, SReg_64:$temp), 1181 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1182 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1183 [] 1184> { 1185 let Constraints = "$src = $dst"; 1186} 1187 1188def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1189def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1190def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1191def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1192 1193} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1194 1195} // end IsCodeGenOnly, isPseudo 1196 1197def : Pat< 1198 (int_AMDGPU_cndlt f32:$src0, f32:$src1, f32:$src2), 1199 (V_CNDMASK_B32_e64 $src2, $src1, (V_CMP_GT_F32_e64 0, $src0)) 1200>; 1201 1202def : Pat < 1203 (int_AMDGPU_kilp), 1204 (SI_KILL (V_MOV_B32_e32 0xbf800000)) 1205>; 1206 1207/* int_SI_vs_load_input */ 1208def : Pat< 1209 (int_SI_vs_load_input v16i8:$tlst, IMM12bit:$attr_offset, 1210 i32:$buf_idx_vgpr), 1211 (BUFFER_LOAD_FORMAT_XYZW imm:$attr_offset, 0, 1, 0, 0, 0, 1212 $buf_idx_vgpr, $tlst, 0, 0, 0) 1213>; 1214 1215/* int_SI_export */ 1216def : Pat < 1217 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1218 f32:$src0, f32:$src1, f32:$src2, f32:$src3), 1219 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1220 $src0, $src1, $src2, $src3) 1221>; 1222 1223/********** ======================= **********/ 1224/********** Image sampling patterns **********/ 1225/********** ======================= **********/ 1226 1227/* int_SI_sample for simple 1D texture lookup */ 1228def : Pat < 1229 (int_SI_sample v1i32:$addr, v32i8:$rsrc, v16i8:$sampler, imm), 1230 (IMAGE_SAMPLE 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1231>; 1232 1233class SamplePattern<Intrinsic name, MIMG opcode, ValueType vt> : Pat < 1234 (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, imm), 1235 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1236>; 1237 1238class SampleRectPattern<Intrinsic name, MIMG opcode, ValueType vt> : Pat < 1239 (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, TEX_RECT), 1240 (opcode 0xf, 1, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1241>; 1242 1243class SampleArrayPattern<Intrinsic name, MIMG opcode, ValueType vt> : Pat < 1244 (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, TEX_ARRAY), 1245 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1246>; 1247 1248class SampleShadowPattern<Intrinsic name, MIMG opcode, 1249 ValueType vt> : Pat < 1250 (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, TEX_SHADOW), 1251 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1252>; 1253 1254class SampleShadowArrayPattern<Intrinsic name, MIMG opcode, 1255 ValueType vt> : Pat < 1256 (name vt:$addr, v32i8:$rsrc, v16i8:$sampler, TEX_SHADOW_ARRAY), 1257 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc, $sampler) 1258>; 1259 1260/* int_SI_sample* for texture lookups consuming more address parameters */ 1261multiclass SamplePatterns<ValueType addr_type> { 1262 def : SamplePattern <int_SI_sample, IMAGE_SAMPLE, addr_type>; 1263 def : SampleRectPattern <int_SI_sample, IMAGE_SAMPLE, addr_type>; 1264 def : SampleArrayPattern <int_SI_sample, IMAGE_SAMPLE, addr_type>; 1265 def : SampleShadowPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_type>; 1266 def : SampleShadowArrayPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_type>; 1267 1268 def : SamplePattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_type>; 1269 def : SampleArrayPattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_type>; 1270 def : SampleShadowPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_type>; 1271 def : SampleShadowArrayPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_type>; 1272 1273 def : SamplePattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_type>; 1274 def : SampleArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_type>; 1275 def : SampleShadowPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_type>; 1276 def : SampleShadowArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_type>; 1277} 1278 1279defm : SamplePatterns<v2i32>; 1280defm : SamplePatterns<v4i32>; 1281defm : SamplePatterns<v8i32>; 1282defm : SamplePatterns<v16i32>; 1283 1284/* int_SI_imageload for texture fetches consuming varying address parameters */ 1285class ImageLoadPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1286 (name addr_type:$addr, v32i8:$rsrc, imm), 1287 (opcode 0xf, 0, 0, 0, 0, 0, 0, 0, $addr, $rsrc) 1288>; 1289 1290class ImageLoadArrayPattern<Intrinsic name, MIMG opcode, ValueType addr_type> : Pat < 1291 (name addr_type:$addr, v32i8:$rsrc, TEX_ARRAY), 1292 (opcode 0xf, 0, 0, 1, 0, 0, 0, 0, $addr, $rsrc) 1293>; 1294 1295multiclass ImageLoadPatterns<ValueType addr_type> { 1296 def : ImageLoadPattern <int_SI_imageload, IMAGE_LOAD_MIP, addr_type>; 1297 def : ImageLoadArrayPattern <int_SI_imageload, IMAGE_LOAD_MIP, addr_type>; 1298} 1299 1300defm : ImageLoadPatterns<v2i32>; 1301defm : ImageLoadPatterns<v4i32>; 1302 1303/* Image resource information */ 1304def : Pat < 1305 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, imm), 1306 (IMAGE_GET_RESINFO 0xf, 0, 0, 0, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1307>; 1308 1309def : Pat < 1310 (int_SI_resinfo i32:$mipid, v32i8:$rsrc, TEX_ARRAY), 1311 (IMAGE_GET_RESINFO 0xf, 0, 0, 1, 0, 0, 0, 0, (V_MOV_B32_e32 $mipid), $rsrc) 1312>; 1313 1314/********** ============================================ **********/ 1315/********** Extraction, Insertion, Building and Casting **********/ 1316/********** ============================================ **********/ 1317 1318foreach Index = 0-2 in { 1319 def Extract_Element_v2i32_#Index : Extract_Element < 1320 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1321 >; 1322 def Insert_Element_v2i32_#Index : Insert_Element < 1323 i32, v2i32, Index, !cast<SubRegIndex>(sub#Index) 1324 >; 1325 1326 def Extract_Element_v2f32_#Index : Extract_Element < 1327 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1328 >; 1329 def Insert_Element_v2f32_#Index : Insert_Element < 1330 f32, v2f32, Index, !cast<SubRegIndex>(sub#Index) 1331 >; 1332} 1333 1334foreach Index = 0-3 in { 1335 def Extract_Element_v4i32_#Index : Extract_Element < 1336 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1337 >; 1338 def Insert_Element_v4i32_#Index : Insert_Element < 1339 i32, v4i32, Index, !cast<SubRegIndex>(sub#Index) 1340 >; 1341 1342 def Extract_Element_v4f32_#Index : Extract_Element < 1343 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1344 >; 1345 def Insert_Element_v4f32_#Index : Insert_Element < 1346 f32, v4f32, Index, !cast<SubRegIndex>(sub#Index) 1347 >; 1348} 1349 1350foreach Index = 0-7 in { 1351 def Extract_Element_v8i32_#Index : Extract_Element < 1352 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1353 >; 1354 def Insert_Element_v8i32_#Index : Insert_Element < 1355 i32, v8i32, Index, !cast<SubRegIndex>(sub#Index) 1356 >; 1357 1358 def Extract_Element_v8f32_#Index : Extract_Element < 1359 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1360 >; 1361 def Insert_Element_v8f32_#Index : Insert_Element < 1362 f32, v8f32, Index, !cast<SubRegIndex>(sub#Index) 1363 >; 1364} 1365 1366foreach Index = 0-15 in { 1367 def Extract_Element_v16i32_#Index : Extract_Element < 1368 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1369 >; 1370 def Insert_Element_v16i32_#Index : Insert_Element < 1371 i32, v16i32, Index, !cast<SubRegIndex>(sub#Index) 1372 >; 1373 1374 def Extract_Element_v16f32_#Index : Extract_Element < 1375 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1376 >; 1377 def Insert_Element_v16f32_#Index : Insert_Element < 1378 f32, v16f32, Index, !cast<SubRegIndex>(sub#Index) 1379 >; 1380} 1381 1382def : Vector1_Build <v1i32, i32, VReg_32>; 1383def : Vector2_Build <v2i32, i32>; 1384def : Vector2_Build <v2f32, f32>; 1385def : Vector4_Build <v4i32, i32>; 1386def : Vector4_Build <v4f32, f32>; 1387def : Vector8_Build <v8i32, i32>; 1388def : Vector8_Build <v8f32, f32>; 1389def : Vector16_Build <v16i32, i32>; 1390def : Vector16_Build <v16f32, f32>; 1391 1392def : BitConvert <i32, f32, SReg_32>; 1393def : BitConvert <i32, f32, VReg_32>; 1394 1395def : BitConvert <f32, i32, SReg_32>; 1396def : BitConvert <f32, i32, VReg_32>; 1397 1398/********** =================== **********/ 1399/********** Src & Dst modifiers **********/ 1400/********** =================== **********/ 1401 1402def : Pat < 1403 (int_AMDIL_clamp f32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1404 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1405 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1406>; 1407 1408def : Pat < 1409 (fabs f32:$src), 1410 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1411 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1412>; 1413 1414def : Pat < 1415 (fneg f32:$src), 1416 (V_ADD_F32_e64 $src, (i32 0 /* SRC1 */), 1417 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */) 1418>; 1419 1420/********** ================== **********/ 1421/********** Immediate Patterns **********/ 1422/********** ================== **********/ 1423 1424def : Pat < 1425 (i32 imm:$imm), 1426 (V_MOV_B32_e32 imm:$imm) 1427>; 1428 1429def : Pat < 1430 (f32 fpimm:$imm), 1431 (V_MOV_B32_e32 fpimm:$imm) 1432>; 1433 1434def : Pat < 1435 (i1 imm:$imm), 1436 (S_MOV_B64 imm:$imm) 1437>; 1438 1439def : Pat < 1440 (i64 InlineImm<i64>:$imm), 1441 (S_MOV_B64 InlineImm<i64>:$imm) 1442>; 1443 1444// i64 immediates aren't supported in hardware, split it into two 32bit values 1445def : Pat < 1446 (i64 imm:$imm), 1447 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1448 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0), 1449 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1) 1450>; 1451 1452/********** ===================== **********/ 1453/********** Interpolation Paterns **********/ 1454/********** ===================== **********/ 1455 1456def : Pat < 1457 (int_SI_fs_constant imm:$attr_chan, imm:$attr, i32:$params), 1458 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, $params) 1459>; 1460 1461def : Pat < 1462 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, v2i32:$ij), 1463 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG v2i32:$ij, sub0), 1464 imm:$attr_chan, imm:$attr, i32:$params), 1465 (EXTRACT_SUBREG $ij, sub1), 1466 imm:$attr_chan, imm:$attr, $params) 1467>; 1468 1469/********** ================== **********/ 1470/********** Intrinsic Patterns **********/ 1471/********** ================== **********/ 1472 1473/* llvm.AMDGPU.pow */ 1474def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32>; 1475 1476def : Pat < 1477 (int_AMDGPU_div f32:$src0, f32:$src1), 1478 (V_MUL_LEGACY_F32_e32 $src0, (V_RCP_LEGACY_F32_e32 $src1)) 1479>; 1480 1481def : Pat< 1482 (fdiv f32:$src0, f32:$src1), 1483 (V_MUL_F32_e32 $src0, (V_RCP_F32_e32 $src1)) 1484>; 1485 1486def : Pat < 1487 (fcos f32:$src0), 1488 (V_COS_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1489>; 1490 1491def : Pat < 1492 (fsin f32:$src0), 1493 (V_SIN_F32_e32 (V_MUL_F32_e32 $src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1494>; 1495 1496def : Pat < 1497 (int_AMDGPU_cube v4f32:$src), 1498 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 1499 (V_CUBETC_F32 (EXTRACT_SUBREG $src, sub0), 1500 (EXTRACT_SUBREG $src, sub1), 1501 (EXTRACT_SUBREG $src, sub2)), 1502 sub0), 1503 (V_CUBESC_F32 (EXTRACT_SUBREG $src, sub0), 1504 (EXTRACT_SUBREG $src, sub1), 1505 (EXTRACT_SUBREG $src, sub2)), 1506 sub1), 1507 (V_CUBEMA_F32 (EXTRACT_SUBREG $src, sub0), 1508 (EXTRACT_SUBREG $src, sub1), 1509 (EXTRACT_SUBREG $src, sub2)), 1510 sub2), 1511 (V_CUBEID_F32 (EXTRACT_SUBREG $src, sub0), 1512 (EXTRACT_SUBREG $src, sub1), 1513 (EXTRACT_SUBREG $src, sub2)), 1514 sub3) 1515>; 1516 1517def : Pat < 1518 (i32 (sext i1:$src0)), 1519 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src0) 1520>; 1521 1522// 1. Offset as 8bit DWORD immediate 1523def : Pat < 1524 (int_SI_load_const v16i8:$sbase, IMM8bitDWORD:$offset), 1525 (S_BUFFER_LOAD_DWORD_IMM $sbase, IMM8bitDWORD:$offset) 1526>; 1527 1528// 2. Offset loaded in an 32bit SGPR 1529def : Pat < 1530 (int_SI_load_const v16i8:$sbase, imm:$offset), 1531 (S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset)) 1532>; 1533 1534// 3. Offset in an 32Bit VGPR 1535def : Pat < 1536 (int_SI_load_const v16i8:$sbase, i32:$voff), 1537 (BUFFER_LOAD_DWORD 0, 1, 0, 0, 0, 0, $voff, $sbase, 0, 0, 0) 1538>; 1539 1540// The multiplication scales from [0,1] to the unsigned integer range 1541def : Pat < 1542 (AMDGPUurecip i32:$src0), 1543 (V_CVT_U32_F32_e32 1544 (V_MUL_F32_e32 CONST.FP_UINT_MAX_PLUS_1, 1545 (V_RCP_IFLAG_F32_e32 (V_CVT_F32_U32_e32 $src0)))) 1546>; 1547 1548/********** ================== **********/ 1549/********** VOP3 Patterns **********/ 1550/********** ================== **********/ 1551 1552def : Pat < 1553 (f32 (fadd (fmul f32:$src0, f32:$src1), f32:$src2)), 1554 (V_MAD_F32 $src0, $src1, $src2) 1555>; 1556 1557/********** ================== **********/ 1558/********** SMRD Patterns **********/ 1559/********** ================== **********/ 1560 1561multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1562 1563 // 1. Offset as 8bit DWORD immediate 1564 def : Pat < 1565 (constant_load (SIadd64bit32bit i64:$sbase, IMM8bitDWORD:$offset)), 1566 (vt (Instr_IMM $sbase, IMM8bitDWORD:$offset)) 1567 >; 1568 1569 // 2. Offset loaded in an 32bit SGPR 1570 def : Pat < 1571 (constant_load (SIadd64bit32bit i64:$sbase, imm:$offset)), 1572 (vt (Instr_SGPR $sbase, (S_MOV_B32 imm:$offset))) 1573 >; 1574 1575 // 3. No offset at all 1576 def : Pat < 1577 (constant_load i64:$sbase), 1578 (vt (Instr_IMM $sbase, 0)) 1579 >; 1580} 1581 1582defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1583defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1584defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v16i8>; 1585defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1586 1587/********** ====================== **********/ 1588/********** Indirect adressing **********/ 1589/********** ====================== **********/ 1590 1591multiclass SI_INDIRECT_Pattern <ValueType vt, SI_INDIRECT_DST IndDst> { 1592 1593 // 1. Extract with offset 1594 def : Pat< 1595 (vector_extract vt:$vec, (i64 (zext (add i32:$idx, imm:$off)))), 1596 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, imm:$off)) 1597 >; 1598 1599 // 2. Extract without offset 1600 def : Pat< 1601 (vector_extract vt:$vec, (i64 (zext i32:$idx))), 1602 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), $vec, $idx, 0)) 1603 >; 1604 1605 // 3. Insert with offset 1606 def : Pat< 1607 (vector_insert vt:$vec, f32:$val, (i64 (zext (add i32:$idx, imm:$off)))), 1608 (IndDst (IMPLICIT_DEF), $vec, $idx, imm:$off, $val) 1609 >; 1610 1611 // 4. Insert without offset 1612 def : Pat< 1613 (vector_insert vt:$vec, f32:$val, (i64 (zext i32:$idx))), 1614 (IndDst (IMPLICIT_DEF), $vec, $idx, 0, $val) 1615 >; 1616} 1617 1618defm : SI_INDIRECT_Pattern <v2f32, SI_INDIRECT_DST_V2>; 1619defm : SI_INDIRECT_Pattern <v4f32, SI_INDIRECT_DST_V4>; 1620defm : SI_INDIRECT_Pattern <v8f32, SI_INDIRECT_DST_V8>; 1621defm : SI_INDIRECT_Pattern <v16f32, SI_INDIRECT_DST_V16>; 1622 1623/********** =============== **********/ 1624/********** Conditions **********/ 1625/********** =============== **********/ 1626 1627def : Pat< 1628 (i1 (setcc f32:$src0, f32:$src1, SETO)), 1629 (V_CMP_O_F32_e64 $src0, $src1) 1630>; 1631 1632def : Pat< 1633 (i1 (setcc f32:$src0, f32:$src1, SETUO)), 1634 (V_CMP_U_F32_e64 $src0, $src1) 1635>; 1636 1637//============================================================================// 1638// Miscellaneous Optimization Patterns 1639//============================================================================// 1640 1641def : SHA256MaPattern <V_BFI_B32, V_XOR_B32_e32>; 1642 1643} // End isSI predicate 1644