SIInstructions.td revision 249423
1//===-- SIInstructions.td - SI Instruction Defintions ---------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// This file was originally auto-generated from a GPU register header file and 10// all the instruction definitions were originally commented out. Instructions 11// that are not yet supported remain commented out. 12//===----------------------------------------------------------------------===// 13 14class InterpSlots { 15int P0 = 2; 16int P10 = 0; 17int P20 = 1; 18} 19def INTERP : InterpSlots; 20 21def InterpSlot : Operand<i32> { 22 let PrintMethod = "printInterpSlot"; 23} 24 25def isSI : Predicate<"Subtarget.device()" 26 "->getGeneration() == AMDGPUDeviceInfo::HD7XXX">; 27 28let Predicates = [isSI] in { 29 30let neverHasSideEffects = 1 in { 31 32let isMoveImm = 1 in { 33def S_MOV_B32 : SOP1_32 <0x00000003, "S_MOV_B32", []>; 34def S_MOV_B64 : SOP1_64 <0x00000004, "S_MOV_B64", []>; 35def S_CMOV_B32 : SOP1_32 <0x00000005, "S_CMOV_B32", []>; 36def S_CMOV_B64 : SOP1_64 <0x00000006, "S_CMOV_B64", []>; 37} // End isMoveImm = 1 38 39def S_NOT_B32 : SOP1_32 <0x00000007, "S_NOT_B32", []>; 40def S_NOT_B64 : SOP1_64 <0x00000008, "S_NOT_B64", []>; 41def S_WQM_B32 : SOP1_32 <0x00000009, "S_WQM_B32", []>; 42def S_WQM_B64 : SOP1_64 <0x0000000a, "S_WQM_B64", []>; 43def S_BREV_B32 : SOP1_32 <0x0000000b, "S_BREV_B32", []>; 44def S_BREV_B64 : SOP1_64 <0x0000000c, "S_BREV_B64", []>; 45} // End neverHasSideEffects = 1 46 47////def S_BCNT0_I32_B32 : SOP1_BCNT0 <0x0000000d, "S_BCNT0_I32_B32", []>; 48////def S_BCNT0_I32_B64 : SOP1_BCNT0 <0x0000000e, "S_BCNT0_I32_B64", []>; 49////def S_BCNT1_I32_B32 : SOP1_BCNT1 <0x0000000f, "S_BCNT1_I32_B32", []>; 50////def S_BCNT1_I32_B64 : SOP1_BCNT1 <0x00000010, "S_BCNT1_I32_B64", []>; 51////def S_FF0_I32_B32 : SOP1_FF0 <0x00000011, "S_FF0_I32_B32", []>; 52////def S_FF0_I32_B64 : SOP1_FF0 <0x00000012, "S_FF0_I32_B64", []>; 53////def S_FF1_I32_B32 : SOP1_FF1 <0x00000013, "S_FF1_I32_B32", []>; 54////def S_FF1_I32_B64 : SOP1_FF1 <0x00000014, "S_FF1_I32_B64", []>; 55//def S_FLBIT_I32_B32 : SOP1_32 <0x00000015, "S_FLBIT_I32_B32", []>; 56//def S_FLBIT_I32_B64 : SOP1_32 <0x00000016, "S_FLBIT_I32_B64", []>; 57def S_FLBIT_I32 : SOP1_32 <0x00000017, "S_FLBIT_I32", []>; 58//def S_FLBIT_I32_I64 : SOP1_32 <0x00000018, "S_FLBIT_I32_I64", []>; 59//def S_SEXT_I32_I8 : SOP1_32 <0x00000019, "S_SEXT_I32_I8", []>; 60//def S_SEXT_I32_I16 : SOP1_32 <0x0000001a, "S_SEXT_I32_I16", []>; 61////def S_BITSET0_B32 : SOP1_BITSET0 <0x0000001b, "S_BITSET0_B32", []>; 62////def S_BITSET0_B64 : SOP1_BITSET0 <0x0000001c, "S_BITSET0_B64", []>; 63////def S_BITSET1_B32 : SOP1_BITSET1 <0x0000001d, "S_BITSET1_B32", []>; 64////def S_BITSET1_B64 : SOP1_BITSET1 <0x0000001e, "S_BITSET1_B64", []>; 65def S_GETPC_B64 : SOP1_64 <0x0000001f, "S_GETPC_B64", []>; 66def S_SETPC_B64 : SOP1_64 <0x00000020, "S_SETPC_B64", []>; 67def S_SWAPPC_B64 : SOP1_64 <0x00000021, "S_SWAPPC_B64", []>; 68def S_RFE_B64 : SOP1_64 <0x00000022, "S_RFE_B64", []>; 69 70let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC] in { 71 72def S_AND_SAVEEXEC_B64 : SOP1_64 <0x00000024, "S_AND_SAVEEXEC_B64", []>; 73def S_OR_SAVEEXEC_B64 : SOP1_64 <0x00000025, "S_OR_SAVEEXEC_B64", []>; 74def S_XOR_SAVEEXEC_B64 : SOP1_64 <0x00000026, "S_XOR_SAVEEXEC_B64", []>; 75def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <0x00000027, "S_ANDN2_SAVEEXEC_B64", []>; 76def S_ORN2_SAVEEXEC_B64 : SOP1_64 <0x00000028, "S_ORN2_SAVEEXEC_B64", []>; 77def S_NAND_SAVEEXEC_B64 : SOP1_64 <0x00000029, "S_NAND_SAVEEXEC_B64", []>; 78def S_NOR_SAVEEXEC_B64 : SOP1_64 <0x0000002a, "S_NOR_SAVEEXEC_B64", []>; 79def S_XNOR_SAVEEXEC_B64 : SOP1_64 <0x0000002b, "S_XNOR_SAVEEXEC_B64", []>; 80 81} // End hasSideEffects = 1 82 83def S_QUADMASK_B32 : SOP1_32 <0x0000002c, "S_QUADMASK_B32", []>; 84def S_QUADMASK_B64 : SOP1_64 <0x0000002d, "S_QUADMASK_B64", []>; 85def S_MOVRELS_B32 : SOP1_32 <0x0000002e, "S_MOVRELS_B32", []>; 86def S_MOVRELS_B64 : SOP1_64 <0x0000002f, "S_MOVRELS_B64", []>; 87def S_MOVRELD_B32 : SOP1_32 <0x00000030, "S_MOVRELD_B32", []>; 88def S_MOVRELD_B64 : SOP1_64 <0x00000031, "S_MOVRELD_B64", []>; 89//def S_CBRANCH_JOIN : SOP1_ <0x00000032, "S_CBRANCH_JOIN", []>; 90def S_MOV_REGRD_B32 : SOP1_32 <0x00000033, "S_MOV_REGRD_B32", []>; 91def S_ABS_I32 : SOP1_32 <0x00000034, "S_ABS_I32", []>; 92def S_MOV_FED_B32 : SOP1_32 <0x00000035, "S_MOV_FED_B32", []>; 93def S_MOVK_I32 : SOPK_32 <0x00000000, "S_MOVK_I32", []>; 94def S_CMOVK_I32 : SOPK_32 <0x00000002, "S_CMOVK_I32", []>; 95 96/* 97This instruction is disabled for now until we can figure out how to teach 98the instruction selector to correctly use the S_CMP* vs V_CMP* 99instructions. 100 101When this instruction is enabled the code generator sometimes produces this 102invalid sequence: 103 104SCC = S_CMPK_EQ_I32 SGPR0, imm 105VCC = COPY SCC 106VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1 107 108def S_CMPK_EQ_I32 : SOPK < 109 0x00000003, (outs SCCReg:$dst), (ins SReg_32:$src0, i32imm:$src1), 110 "S_CMPK_EQ_I32", 111 [(set SCCReg:$dst, (setcc SReg_32:$src0, imm:$src1, SETEQ))] 112>; 113*/ 114 115let isCompare = 1 in { 116def S_CMPK_LG_I32 : SOPK_32 <0x00000004, "S_CMPK_LG_I32", []>; 117def S_CMPK_GT_I32 : SOPK_32 <0x00000005, "S_CMPK_GT_I32", []>; 118def S_CMPK_GE_I32 : SOPK_32 <0x00000006, "S_CMPK_GE_I32", []>; 119def S_CMPK_LT_I32 : SOPK_32 <0x00000007, "S_CMPK_LT_I32", []>; 120def S_CMPK_LE_I32 : SOPK_32 <0x00000008, "S_CMPK_LE_I32", []>; 121def S_CMPK_EQ_U32 : SOPK_32 <0x00000009, "S_CMPK_EQ_U32", []>; 122def S_CMPK_LG_U32 : SOPK_32 <0x0000000a, "S_CMPK_LG_U32", []>; 123def S_CMPK_GT_U32 : SOPK_32 <0x0000000b, "S_CMPK_GT_U32", []>; 124def S_CMPK_GE_U32 : SOPK_32 <0x0000000c, "S_CMPK_GE_U32", []>; 125def S_CMPK_LT_U32 : SOPK_32 <0x0000000d, "S_CMPK_LT_U32", []>; 126def S_CMPK_LE_U32 : SOPK_32 <0x0000000e, "S_CMPK_LE_U32", []>; 127} // End isCompare = 1 128 129def S_ADDK_I32 : SOPK_32 <0x0000000f, "S_ADDK_I32", []>; 130def S_MULK_I32 : SOPK_32 <0x00000010, "S_MULK_I32", []>; 131//def S_CBRANCH_I_FORK : SOPK_ <0x00000011, "S_CBRANCH_I_FORK", []>; 132def S_GETREG_B32 : SOPK_32 <0x00000012, "S_GETREG_B32", []>; 133def S_SETREG_B32 : SOPK_32 <0x00000013, "S_SETREG_B32", []>; 134def S_GETREG_REGRD_B32 : SOPK_32 <0x00000014, "S_GETREG_REGRD_B32", []>; 135//def S_SETREG_IMM32_B32 : SOPK_32 <0x00000015, "S_SETREG_IMM32_B32", []>; 136//def EXP : EXP_ <0x00000000, "EXP", []>; 137 138let isCompare = 1 in { 139 140defm V_CMP_F_F32 : VOPC_32 <0x00000000, "V_CMP_F_F32">; 141defm V_CMP_LT_F32 : VOPC_32 <0x00000001, "V_CMP_LT_F32", f32, COND_LT>; 142defm V_CMP_EQ_F32 : VOPC_32 <0x00000002, "V_CMP_EQ_F32", f32, COND_EQ>; 143defm V_CMP_LE_F32 : VOPC_32 <0x00000003, "V_CMP_LE_F32", f32, COND_LE>; 144defm V_CMP_GT_F32 : VOPC_32 <0x00000004, "V_CMP_GT_F32", f32, COND_GT>; 145defm V_CMP_LG_F32 : VOPC_32 <0x00000005, "V_CMP_LG_F32", f32, COND_NE>; 146defm V_CMP_GE_F32 : VOPC_32 <0x00000006, "V_CMP_GE_F32", f32, COND_GE>; 147defm V_CMP_O_F32 : VOPC_32 <0x00000007, "V_CMP_O_F32">; 148defm V_CMP_U_F32 : VOPC_32 <0x00000008, "V_CMP_U_F32">; 149defm V_CMP_NGE_F32 : VOPC_32 <0x00000009, "V_CMP_NGE_F32">; 150defm V_CMP_NLG_F32 : VOPC_32 <0x0000000a, "V_CMP_NLG_F32">; 151defm V_CMP_NGT_F32 : VOPC_32 <0x0000000b, "V_CMP_NGT_F32">; 152defm V_CMP_NLE_F32 : VOPC_32 <0x0000000c, "V_CMP_NLE_F32">; 153defm V_CMP_NEQ_F32 : VOPC_32 <0x0000000d, "V_CMP_NEQ_F32", f32, COND_NE>; 154defm V_CMP_NLT_F32 : VOPC_32 <0x0000000e, "V_CMP_NLT_F32">; 155defm V_CMP_TRU_F32 : VOPC_32 <0x0000000f, "V_CMP_TRU_F32">; 156 157let hasSideEffects = 1, Defs = [EXEC] in { 158 159defm V_CMPX_F_F32 : VOPC_32 <0x00000010, "V_CMPX_F_F32">; 160defm V_CMPX_LT_F32 : VOPC_32 <0x00000011, "V_CMPX_LT_F32">; 161defm V_CMPX_EQ_F32 : VOPC_32 <0x00000012, "V_CMPX_EQ_F32">; 162defm V_CMPX_LE_F32 : VOPC_32 <0x00000013, "V_CMPX_LE_F32">; 163defm V_CMPX_GT_F32 : VOPC_32 <0x00000014, "V_CMPX_GT_F32">; 164defm V_CMPX_LG_F32 : VOPC_32 <0x00000015, "V_CMPX_LG_F32">; 165defm V_CMPX_GE_F32 : VOPC_32 <0x00000016, "V_CMPX_GE_F32">; 166defm V_CMPX_O_F32 : VOPC_32 <0x00000017, "V_CMPX_O_F32">; 167defm V_CMPX_U_F32 : VOPC_32 <0x00000018, "V_CMPX_U_F32">; 168defm V_CMPX_NGE_F32 : VOPC_32 <0x00000019, "V_CMPX_NGE_F32">; 169defm V_CMPX_NLG_F32 : VOPC_32 <0x0000001a, "V_CMPX_NLG_F32">; 170defm V_CMPX_NGT_F32 : VOPC_32 <0x0000001b, "V_CMPX_NGT_F32">; 171defm V_CMPX_NLE_F32 : VOPC_32 <0x0000001c, "V_CMPX_NLE_F32">; 172defm V_CMPX_NEQ_F32 : VOPC_32 <0x0000001d, "V_CMPX_NEQ_F32">; 173defm V_CMPX_NLT_F32 : VOPC_32 <0x0000001e, "V_CMPX_NLT_F32">; 174defm V_CMPX_TRU_F32 : VOPC_32 <0x0000001f, "V_CMPX_TRU_F32">; 175 176} // End hasSideEffects = 1, Defs = [EXEC] 177 178defm V_CMP_F_F64 : VOPC_64 <0x00000020, "V_CMP_F_F64">; 179defm V_CMP_LT_F64 : VOPC_64 <0x00000021, "V_CMP_LT_F64">; 180defm V_CMP_EQ_F64 : VOPC_64 <0x00000022, "V_CMP_EQ_F64">; 181defm V_CMP_LE_F64 : VOPC_64 <0x00000023, "V_CMP_LE_F64">; 182defm V_CMP_GT_F64 : VOPC_64 <0x00000024, "V_CMP_GT_F64">; 183defm V_CMP_LG_F64 : VOPC_64 <0x00000025, "V_CMP_LG_F64">; 184defm V_CMP_GE_F64 : VOPC_64 <0x00000026, "V_CMP_GE_F64">; 185defm V_CMP_O_F64 : VOPC_64 <0x00000027, "V_CMP_O_F64">; 186defm V_CMP_U_F64 : VOPC_64 <0x00000028, "V_CMP_U_F64">; 187defm V_CMP_NGE_F64 : VOPC_64 <0x00000029, "V_CMP_NGE_F64">; 188defm V_CMP_NLG_F64 : VOPC_64 <0x0000002a, "V_CMP_NLG_F64">; 189defm V_CMP_NGT_F64 : VOPC_64 <0x0000002b, "V_CMP_NGT_F64">; 190defm V_CMP_NLE_F64 : VOPC_64 <0x0000002c, "V_CMP_NLE_F64">; 191defm V_CMP_NEQ_F64 : VOPC_64 <0x0000002d, "V_CMP_NEQ_F64">; 192defm V_CMP_NLT_F64 : VOPC_64 <0x0000002e, "V_CMP_NLT_F64">; 193defm V_CMP_TRU_F64 : VOPC_64 <0x0000002f, "V_CMP_TRU_F64">; 194 195let hasSideEffects = 1, Defs = [EXEC] in { 196 197defm V_CMPX_F_F64 : VOPC_64 <0x00000030, "V_CMPX_F_F64">; 198defm V_CMPX_LT_F64 : VOPC_64 <0x00000031, "V_CMPX_LT_F64">; 199defm V_CMPX_EQ_F64 : VOPC_64 <0x00000032, "V_CMPX_EQ_F64">; 200defm V_CMPX_LE_F64 : VOPC_64 <0x00000033, "V_CMPX_LE_F64">; 201defm V_CMPX_GT_F64 : VOPC_64 <0x00000034, "V_CMPX_GT_F64">; 202defm V_CMPX_LG_F64 : VOPC_64 <0x00000035, "V_CMPX_LG_F64">; 203defm V_CMPX_GE_F64 : VOPC_64 <0x00000036, "V_CMPX_GE_F64">; 204defm V_CMPX_O_F64 : VOPC_64 <0x00000037, "V_CMPX_O_F64">; 205defm V_CMPX_U_F64 : VOPC_64 <0x00000038, "V_CMPX_U_F64">; 206defm V_CMPX_NGE_F64 : VOPC_64 <0x00000039, "V_CMPX_NGE_F64">; 207defm V_CMPX_NLG_F64 : VOPC_64 <0x0000003a, "V_CMPX_NLG_F64">; 208defm V_CMPX_NGT_F64 : VOPC_64 <0x0000003b, "V_CMPX_NGT_F64">; 209defm V_CMPX_NLE_F64 : VOPC_64 <0x0000003c, "V_CMPX_NLE_F64">; 210defm V_CMPX_NEQ_F64 : VOPC_64 <0x0000003d, "V_CMPX_NEQ_F64">; 211defm V_CMPX_NLT_F64 : VOPC_64 <0x0000003e, "V_CMPX_NLT_F64">; 212defm V_CMPX_TRU_F64 : VOPC_64 <0x0000003f, "V_CMPX_TRU_F64">; 213 214} // End hasSideEffects = 1, Defs = [EXEC] 215 216defm V_CMPS_F_F32 : VOPC_32 <0x00000040, "V_CMPS_F_F32">; 217defm V_CMPS_LT_F32 : VOPC_32 <0x00000041, "V_CMPS_LT_F32">; 218defm V_CMPS_EQ_F32 : VOPC_32 <0x00000042, "V_CMPS_EQ_F32">; 219defm V_CMPS_LE_F32 : VOPC_32 <0x00000043, "V_CMPS_LE_F32">; 220defm V_CMPS_GT_F32 : VOPC_32 <0x00000044, "V_CMPS_GT_F32">; 221defm V_CMPS_LG_F32 : VOPC_32 <0x00000045, "V_CMPS_LG_F32">; 222defm V_CMPS_GE_F32 : VOPC_32 <0x00000046, "V_CMPS_GE_F32">; 223defm V_CMPS_O_F32 : VOPC_32 <0x00000047, "V_CMPS_O_F32">; 224defm V_CMPS_U_F32 : VOPC_32 <0x00000048, "V_CMPS_U_F32">; 225defm V_CMPS_NGE_F32 : VOPC_32 <0x00000049, "V_CMPS_NGE_F32">; 226defm V_CMPS_NLG_F32 : VOPC_32 <0x0000004a, "V_CMPS_NLG_F32">; 227defm V_CMPS_NGT_F32 : VOPC_32 <0x0000004b, "V_CMPS_NGT_F32">; 228defm V_CMPS_NLE_F32 : VOPC_32 <0x0000004c, "V_CMPS_NLE_F32">; 229defm V_CMPS_NEQ_F32 : VOPC_32 <0x0000004d, "V_CMPS_NEQ_F32">; 230defm V_CMPS_NLT_F32 : VOPC_32 <0x0000004e, "V_CMPS_NLT_F32">; 231defm V_CMPS_TRU_F32 : VOPC_32 <0x0000004f, "V_CMPS_TRU_F32">; 232 233let hasSideEffects = 1, Defs = [EXEC] in { 234 235defm V_CMPSX_F_F32 : VOPC_32 <0x00000050, "V_CMPSX_F_F32">; 236defm V_CMPSX_LT_F32 : VOPC_32 <0x00000051, "V_CMPSX_LT_F32">; 237defm V_CMPSX_EQ_F32 : VOPC_32 <0x00000052, "V_CMPSX_EQ_F32">; 238defm V_CMPSX_LE_F32 : VOPC_32 <0x00000053, "V_CMPSX_LE_F32">; 239defm V_CMPSX_GT_F32 : VOPC_32 <0x00000054, "V_CMPSX_GT_F32">; 240defm V_CMPSX_LG_F32 : VOPC_32 <0x00000055, "V_CMPSX_LG_F32">; 241defm V_CMPSX_GE_F32 : VOPC_32 <0x00000056, "V_CMPSX_GE_F32">; 242defm V_CMPSX_O_F32 : VOPC_32 <0x00000057, "V_CMPSX_O_F32">; 243defm V_CMPSX_U_F32 : VOPC_32 <0x00000058, "V_CMPSX_U_F32">; 244defm V_CMPSX_NGE_F32 : VOPC_32 <0x00000059, "V_CMPSX_NGE_F32">; 245defm V_CMPSX_NLG_F32 : VOPC_32 <0x0000005a, "V_CMPSX_NLG_F32">; 246defm V_CMPSX_NGT_F32 : VOPC_32 <0x0000005b, "V_CMPSX_NGT_F32">; 247defm V_CMPSX_NLE_F32 : VOPC_32 <0x0000005c, "V_CMPSX_NLE_F32">; 248defm V_CMPSX_NEQ_F32 : VOPC_32 <0x0000005d, "V_CMPSX_NEQ_F32">; 249defm V_CMPSX_NLT_F32 : VOPC_32 <0x0000005e, "V_CMPSX_NLT_F32">; 250defm V_CMPSX_TRU_F32 : VOPC_32 <0x0000005f, "V_CMPSX_TRU_F32">; 251 252} // End hasSideEffects = 1, Defs = [EXEC] 253 254defm V_CMPS_F_F64 : VOPC_64 <0x00000060, "V_CMPS_F_F64">; 255defm V_CMPS_LT_F64 : VOPC_64 <0x00000061, "V_CMPS_LT_F64">; 256defm V_CMPS_EQ_F64 : VOPC_64 <0x00000062, "V_CMPS_EQ_F64">; 257defm V_CMPS_LE_F64 : VOPC_64 <0x00000063, "V_CMPS_LE_F64">; 258defm V_CMPS_GT_F64 : VOPC_64 <0x00000064, "V_CMPS_GT_F64">; 259defm V_CMPS_LG_F64 : VOPC_64 <0x00000065, "V_CMPS_LG_F64">; 260defm V_CMPS_GE_F64 : VOPC_64 <0x00000066, "V_CMPS_GE_F64">; 261defm V_CMPS_O_F64 : VOPC_64 <0x00000067, "V_CMPS_O_F64">; 262defm V_CMPS_U_F64 : VOPC_64 <0x00000068, "V_CMPS_U_F64">; 263defm V_CMPS_NGE_F64 : VOPC_64 <0x00000069, "V_CMPS_NGE_F64">; 264defm V_CMPS_NLG_F64 : VOPC_64 <0x0000006a, "V_CMPS_NLG_F64">; 265defm V_CMPS_NGT_F64 : VOPC_64 <0x0000006b, "V_CMPS_NGT_F64">; 266defm V_CMPS_NLE_F64 : VOPC_64 <0x0000006c, "V_CMPS_NLE_F64">; 267defm V_CMPS_NEQ_F64 : VOPC_64 <0x0000006d, "V_CMPS_NEQ_F64">; 268defm V_CMPS_NLT_F64 : VOPC_64 <0x0000006e, "V_CMPS_NLT_F64">; 269defm V_CMPS_TRU_F64 : VOPC_64 <0x0000006f, "V_CMPS_TRU_F64">; 270 271let hasSideEffects = 1, Defs = [EXEC] in { 272 273defm V_CMPSX_F_F64 : VOPC_64 <0x00000070, "V_CMPSX_F_F64">; 274defm V_CMPSX_LT_F64 : VOPC_64 <0x00000071, "V_CMPSX_LT_F64">; 275defm V_CMPSX_EQ_F64 : VOPC_64 <0x00000072, "V_CMPSX_EQ_F64">; 276defm V_CMPSX_LE_F64 : VOPC_64 <0x00000073, "V_CMPSX_LE_F64">; 277defm V_CMPSX_GT_F64 : VOPC_64 <0x00000074, "V_CMPSX_GT_F64">; 278defm V_CMPSX_LG_F64 : VOPC_64 <0x00000075, "V_CMPSX_LG_F64">; 279defm V_CMPSX_GE_F64 : VOPC_64 <0x00000076, "V_CMPSX_GE_F64">; 280defm V_CMPSX_O_F64 : VOPC_64 <0x00000077, "V_CMPSX_O_F64">; 281defm V_CMPSX_U_F64 : VOPC_64 <0x00000078, "V_CMPSX_U_F64">; 282defm V_CMPSX_NGE_F64 : VOPC_64 <0x00000079, "V_CMPSX_NGE_F64">; 283defm V_CMPSX_NLG_F64 : VOPC_64 <0x0000007a, "V_CMPSX_NLG_F64">; 284defm V_CMPSX_NGT_F64 : VOPC_64 <0x0000007b, "V_CMPSX_NGT_F64">; 285defm V_CMPSX_NLE_F64 : VOPC_64 <0x0000007c, "V_CMPSX_NLE_F64">; 286defm V_CMPSX_NEQ_F64 : VOPC_64 <0x0000007d, "V_CMPSX_NEQ_F64">; 287defm V_CMPSX_NLT_F64 : VOPC_64 <0x0000007e, "V_CMPSX_NLT_F64">; 288defm V_CMPSX_TRU_F64 : VOPC_64 <0x0000007f, "V_CMPSX_TRU_F64">; 289 290} // End hasSideEffects = 1, Defs = [EXEC] 291 292defm V_CMP_F_I32 : VOPC_32 <0x00000080, "V_CMP_F_I32">; 293defm V_CMP_LT_I32 : VOPC_32 <0x00000081, "V_CMP_LT_I32", i32, COND_LT>; 294defm V_CMP_EQ_I32 : VOPC_32 <0x00000082, "V_CMP_EQ_I32", i32, COND_EQ>; 295defm V_CMP_LE_I32 : VOPC_32 <0x00000083, "V_CMP_LE_I32", i32, COND_LE>; 296defm V_CMP_GT_I32 : VOPC_32 <0x00000084, "V_CMP_GT_I32", i32, COND_GT>; 297defm V_CMP_NE_I32 : VOPC_32 <0x00000085, "V_CMP_NE_I32", i32, COND_NE>; 298defm V_CMP_GE_I32 : VOPC_32 <0x00000086, "V_CMP_GE_I32", i32, COND_GE>; 299defm V_CMP_T_I32 : VOPC_32 <0x00000087, "V_CMP_T_I32">; 300 301let hasSideEffects = 1, Defs = [EXEC] in { 302 303defm V_CMPX_F_I32 : VOPC_32 <0x00000090, "V_CMPX_F_I32">; 304defm V_CMPX_LT_I32 : VOPC_32 <0x00000091, "V_CMPX_LT_I32">; 305defm V_CMPX_EQ_I32 : VOPC_32 <0x00000092, "V_CMPX_EQ_I32">; 306defm V_CMPX_LE_I32 : VOPC_32 <0x00000093, "V_CMPX_LE_I32">; 307defm V_CMPX_GT_I32 : VOPC_32 <0x00000094, "V_CMPX_GT_I32">; 308defm V_CMPX_NE_I32 : VOPC_32 <0x00000095, "V_CMPX_NE_I32">; 309defm V_CMPX_GE_I32 : VOPC_32 <0x00000096, "V_CMPX_GE_I32">; 310defm V_CMPX_T_I32 : VOPC_32 <0x00000097, "V_CMPX_T_I32">; 311 312} // End hasSideEffects = 1, Defs = [EXEC] 313 314defm V_CMP_F_I64 : VOPC_64 <0x000000a0, "V_CMP_F_I64">; 315defm V_CMP_LT_I64 : VOPC_64 <0x000000a1, "V_CMP_LT_I64">; 316defm V_CMP_EQ_I64 : VOPC_64 <0x000000a2, "V_CMP_EQ_I64">; 317defm V_CMP_LE_I64 : VOPC_64 <0x000000a3, "V_CMP_LE_I64">; 318defm V_CMP_GT_I64 : VOPC_64 <0x000000a4, "V_CMP_GT_I64">; 319defm V_CMP_NE_I64 : VOPC_64 <0x000000a5, "V_CMP_NE_I64">; 320defm V_CMP_GE_I64 : VOPC_64 <0x000000a6, "V_CMP_GE_I64">; 321defm V_CMP_T_I64 : VOPC_64 <0x000000a7, "V_CMP_T_I64">; 322 323let hasSideEffects = 1, Defs = [EXEC] in { 324 325defm V_CMPX_F_I64 : VOPC_64 <0x000000b0, "V_CMPX_F_I64">; 326defm V_CMPX_LT_I64 : VOPC_64 <0x000000b1, "V_CMPX_LT_I64">; 327defm V_CMPX_EQ_I64 : VOPC_64 <0x000000b2, "V_CMPX_EQ_I64">; 328defm V_CMPX_LE_I64 : VOPC_64 <0x000000b3, "V_CMPX_LE_I64">; 329defm V_CMPX_GT_I64 : VOPC_64 <0x000000b4, "V_CMPX_GT_I64">; 330defm V_CMPX_NE_I64 : VOPC_64 <0x000000b5, "V_CMPX_NE_I64">; 331defm V_CMPX_GE_I64 : VOPC_64 <0x000000b6, "V_CMPX_GE_I64">; 332defm V_CMPX_T_I64 : VOPC_64 <0x000000b7, "V_CMPX_T_I64">; 333 334} // End hasSideEffects = 1, Defs = [EXEC] 335 336defm V_CMP_F_U32 : VOPC_32 <0x000000c0, "V_CMP_F_U32">; 337defm V_CMP_LT_U32 : VOPC_32 <0x000000c1, "V_CMP_LT_U32">; 338defm V_CMP_EQ_U32 : VOPC_32 <0x000000c2, "V_CMP_EQ_U32">; 339defm V_CMP_LE_U32 : VOPC_32 <0x000000c3, "V_CMP_LE_U32">; 340defm V_CMP_GT_U32 : VOPC_32 <0x000000c4, "V_CMP_GT_U32">; 341defm V_CMP_NE_U32 : VOPC_32 <0x000000c5, "V_CMP_NE_U32">; 342defm V_CMP_GE_U32 : VOPC_32 <0x000000c6, "V_CMP_GE_U32">; 343defm V_CMP_T_U32 : VOPC_32 <0x000000c7, "V_CMP_T_U32">; 344 345let hasSideEffects = 1, Defs = [EXEC] in { 346 347defm V_CMPX_F_U32 : VOPC_32 <0x000000d0, "V_CMPX_F_U32">; 348defm V_CMPX_LT_U32 : VOPC_32 <0x000000d1, "V_CMPX_LT_U32">; 349defm V_CMPX_EQ_U32 : VOPC_32 <0x000000d2, "V_CMPX_EQ_U32">; 350defm V_CMPX_LE_U32 : VOPC_32 <0x000000d3, "V_CMPX_LE_U32">; 351defm V_CMPX_GT_U32 : VOPC_32 <0x000000d4, "V_CMPX_GT_U32">; 352defm V_CMPX_NE_U32 : VOPC_32 <0x000000d5, "V_CMPX_NE_U32">; 353defm V_CMPX_GE_U32 : VOPC_32 <0x000000d6, "V_CMPX_GE_U32">; 354defm V_CMPX_T_U32 : VOPC_32 <0x000000d7, "V_CMPX_T_U32">; 355 356} // End hasSideEffects = 1, Defs = [EXEC] 357 358defm V_CMP_F_U64 : VOPC_64 <0x000000e0, "V_CMP_F_U64">; 359defm V_CMP_LT_U64 : VOPC_64 <0x000000e1, "V_CMP_LT_U64">; 360defm V_CMP_EQ_U64 : VOPC_64 <0x000000e2, "V_CMP_EQ_U64">; 361defm V_CMP_LE_U64 : VOPC_64 <0x000000e3, "V_CMP_LE_U64">; 362defm V_CMP_GT_U64 : VOPC_64 <0x000000e4, "V_CMP_GT_U64">; 363defm V_CMP_NE_U64 : VOPC_64 <0x000000e5, "V_CMP_NE_U64">; 364defm V_CMP_GE_U64 : VOPC_64 <0x000000e6, "V_CMP_GE_U64">; 365defm V_CMP_T_U64 : VOPC_64 <0x000000e7, "V_CMP_T_U64">; 366 367let hasSideEffects = 1, Defs = [EXEC] in { 368 369defm V_CMPX_F_U64 : VOPC_64 <0x000000f0, "V_CMPX_F_U64">; 370defm V_CMPX_LT_U64 : VOPC_64 <0x000000f1, "V_CMPX_LT_U64">; 371defm V_CMPX_EQ_U64 : VOPC_64 <0x000000f2, "V_CMPX_EQ_U64">; 372defm V_CMPX_LE_U64 : VOPC_64 <0x000000f3, "V_CMPX_LE_U64">; 373defm V_CMPX_GT_U64 : VOPC_64 <0x000000f4, "V_CMPX_GT_U64">; 374defm V_CMPX_NE_U64 : VOPC_64 <0x000000f5, "V_CMPX_NE_U64">; 375defm V_CMPX_GE_U64 : VOPC_64 <0x000000f6, "V_CMPX_GE_U64">; 376defm V_CMPX_T_U64 : VOPC_64 <0x000000f7, "V_CMPX_T_U64">; 377 378} // End hasSideEffects = 1, Defs = [EXEC] 379 380defm V_CMP_CLASS_F32 : VOPC_32 <0x00000088, "V_CMP_CLASS_F32">; 381 382let hasSideEffects = 1, Defs = [EXEC] in { 383defm V_CMPX_CLASS_F32 : VOPC_32 <0x00000098, "V_CMPX_CLASS_F32">; 384} // End hasSideEffects = 1, Defs = [EXEC] 385 386defm V_CMP_CLASS_F64 : VOPC_64 <0x000000a8, "V_CMP_CLASS_F64">; 387 388let hasSideEffects = 1, Defs = [EXEC] in { 389defm V_CMPX_CLASS_F64 : VOPC_64 <0x000000b8, "V_CMPX_CLASS_F64">; 390} // End hasSideEffects = 1, Defs = [EXEC] 391 392} // End isCompare = 1 393 394//def BUFFER_LOAD_FORMAT_X : MUBUF_ <0x00000000, "BUFFER_LOAD_FORMAT_X", []>; 395//def BUFFER_LOAD_FORMAT_XY : MUBUF_ <0x00000001, "BUFFER_LOAD_FORMAT_XY", []>; 396//def BUFFER_LOAD_FORMAT_XYZ : MUBUF_ <0x00000002, "BUFFER_LOAD_FORMAT_XYZ", []>; 397def BUFFER_LOAD_FORMAT_XYZW : MUBUF_Load_Helper <0x00000003, "BUFFER_LOAD_FORMAT_XYZW", VReg_128>; 398//def BUFFER_STORE_FORMAT_X : MUBUF_ <0x00000004, "BUFFER_STORE_FORMAT_X", []>; 399//def BUFFER_STORE_FORMAT_XY : MUBUF_ <0x00000005, "BUFFER_STORE_FORMAT_XY", []>; 400//def BUFFER_STORE_FORMAT_XYZ : MUBUF_ <0x00000006, "BUFFER_STORE_FORMAT_XYZ", []>; 401//def BUFFER_STORE_FORMAT_XYZW : MUBUF_ <0x00000007, "BUFFER_STORE_FORMAT_XYZW", []>; 402//def BUFFER_LOAD_UBYTE : MUBUF_ <0x00000008, "BUFFER_LOAD_UBYTE", []>; 403//def BUFFER_LOAD_SBYTE : MUBUF_ <0x00000009, "BUFFER_LOAD_SBYTE", []>; 404//def BUFFER_LOAD_USHORT : MUBUF_ <0x0000000a, "BUFFER_LOAD_USHORT", []>; 405//def BUFFER_LOAD_SSHORT : MUBUF_ <0x0000000b, "BUFFER_LOAD_SSHORT", []>; 406def BUFFER_LOAD_DWORD : MUBUF_Load_Helper <0x0000000c, "BUFFER_LOAD_DWORD", VReg_32>; 407def BUFFER_LOAD_DWORDX2 : MUBUF_Load_Helper <0x0000000d, "BUFFER_LOAD_DWORDX2", VReg_64>; 408def BUFFER_LOAD_DWORDX4 : MUBUF_Load_Helper <0x0000000e, "BUFFER_LOAD_DWORDX4", VReg_128>; 409//def BUFFER_STORE_BYTE : MUBUF_ <0x00000018, "BUFFER_STORE_BYTE", []>; 410//def BUFFER_STORE_SHORT : MUBUF_ <0x0000001a, "BUFFER_STORE_SHORT", []>; 411//def BUFFER_STORE_DWORD : MUBUF_ <0x0000001c, "BUFFER_STORE_DWORD", []>; 412//def BUFFER_STORE_DWORDX2 : MUBUF_DWORDX2 <0x0000001d, "BUFFER_STORE_DWORDX2", []>; 413//def BUFFER_STORE_DWORDX4 : MUBUF_DWORDX4 <0x0000001e, "BUFFER_STORE_DWORDX4", []>; 414//def BUFFER_ATOMIC_SWAP : MUBUF_ <0x00000030, "BUFFER_ATOMIC_SWAP", []>; 415//def BUFFER_ATOMIC_CMPSWAP : MUBUF_ <0x00000031, "BUFFER_ATOMIC_CMPSWAP", []>; 416//def BUFFER_ATOMIC_ADD : MUBUF_ <0x00000032, "BUFFER_ATOMIC_ADD", []>; 417//def BUFFER_ATOMIC_SUB : MUBUF_ <0x00000033, "BUFFER_ATOMIC_SUB", []>; 418//def BUFFER_ATOMIC_RSUB : MUBUF_ <0x00000034, "BUFFER_ATOMIC_RSUB", []>; 419//def BUFFER_ATOMIC_SMIN : MUBUF_ <0x00000035, "BUFFER_ATOMIC_SMIN", []>; 420//def BUFFER_ATOMIC_UMIN : MUBUF_ <0x00000036, "BUFFER_ATOMIC_UMIN", []>; 421//def BUFFER_ATOMIC_SMAX : MUBUF_ <0x00000037, "BUFFER_ATOMIC_SMAX", []>; 422//def BUFFER_ATOMIC_UMAX : MUBUF_ <0x00000038, "BUFFER_ATOMIC_UMAX", []>; 423//def BUFFER_ATOMIC_AND : MUBUF_ <0x00000039, "BUFFER_ATOMIC_AND", []>; 424//def BUFFER_ATOMIC_OR : MUBUF_ <0x0000003a, "BUFFER_ATOMIC_OR", []>; 425//def BUFFER_ATOMIC_XOR : MUBUF_ <0x0000003b, "BUFFER_ATOMIC_XOR", []>; 426//def BUFFER_ATOMIC_INC : MUBUF_ <0x0000003c, "BUFFER_ATOMIC_INC", []>; 427//def BUFFER_ATOMIC_DEC : MUBUF_ <0x0000003d, "BUFFER_ATOMIC_DEC", []>; 428//def BUFFER_ATOMIC_FCMPSWAP : MUBUF_ <0x0000003e, "BUFFER_ATOMIC_FCMPSWAP", []>; 429//def BUFFER_ATOMIC_FMIN : MUBUF_ <0x0000003f, "BUFFER_ATOMIC_FMIN", []>; 430//def BUFFER_ATOMIC_FMAX : MUBUF_ <0x00000040, "BUFFER_ATOMIC_FMAX", []>; 431//def BUFFER_ATOMIC_SWAP_X2 : MUBUF_X2 <0x00000050, "BUFFER_ATOMIC_SWAP_X2", []>; 432//def BUFFER_ATOMIC_CMPSWAP_X2 : MUBUF_X2 <0x00000051, "BUFFER_ATOMIC_CMPSWAP_X2", []>; 433//def BUFFER_ATOMIC_ADD_X2 : MUBUF_X2 <0x00000052, "BUFFER_ATOMIC_ADD_X2", []>; 434//def BUFFER_ATOMIC_SUB_X2 : MUBUF_X2 <0x00000053, "BUFFER_ATOMIC_SUB_X2", []>; 435//def BUFFER_ATOMIC_RSUB_X2 : MUBUF_X2 <0x00000054, "BUFFER_ATOMIC_RSUB_X2", []>; 436//def BUFFER_ATOMIC_SMIN_X2 : MUBUF_X2 <0x00000055, "BUFFER_ATOMIC_SMIN_X2", []>; 437//def BUFFER_ATOMIC_UMIN_X2 : MUBUF_X2 <0x00000056, "BUFFER_ATOMIC_UMIN_X2", []>; 438//def BUFFER_ATOMIC_SMAX_X2 : MUBUF_X2 <0x00000057, "BUFFER_ATOMIC_SMAX_X2", []>; 439//def BUFFER_ATOMIC_UMAX_X2 : MUBUF_X2 <0x00000058, "BUFFER_ATOMIC_UMAX_X2", []>; 440//def BUFFER_ATOMIC_AND_X2 : MUBUF_X2 <0x00000059, "BUFFER_ATOMIC_AND_X2", []>; 441//def BUFFER_ATOMIC_OR_X2 : MUBUF_X2 <0x0000005a, "BUFFER_ATOMIC_OR_X2", []>; 442//def BUFFER_ATOMIC_XOR_X2 : MUBUF_X2 <0x0000005b, "BUFFER_ATOMIC_XOR_X2", []>; 443//def BUFFER_ATOMIC_INC_X2 : MUBUF_X2 <0x0000005c, "BUFFER_ATOMIC_INC_X2", []>; 444//def BUFFER_ATOMIC_DEC_X2 : MUBUF_X2 <0x0000005d, "BUFFER_ATOMIC_DEC_X2", []>; 445//def BUFFER_ATOMIC_FCMPSWAP_X2 : MUBUF_X2 <0x0000005e, "BUFFER_ATOMIC_FCMPSWAP_X2", []>; 446//def BUFFER_ATOMIC_FMIN_X2 : MUBUF_X2 <0x0000005f, "BUFFER_ATOMIC_FMIN_X2", []>; 447//def BUFFER_ATOMIC_FMAX_X2 : MUBUF_X2 <0x00000060, "BUFFER_ATOMIC_FMAX_X2", []>; 448//def BUFFER_WBINVL1_SC : MUBUF_WBINVL1 <0x00000070, "BUFFER_WBINVL1_SC", []>; 449//def BUFFER_WBINVL1 : MUBUF_WBINVL1 <0x00000071, "BUFFER_WBINVL1", []>; 450//def TBUFFER_LOAD_FORMAT_X : MTBUF_ <0x00000000, "TBUFFER_LOAD_FORMAT_X", []>; 451//def TBUFFER_LOAD_FORMAT_XY : MTBUF_ <0x00000001, "TBUFFER_LOAD_FORMAT_XY", []>; 452//def TBUFFER_LOAD_FORMAT_XYZ : MTBUF_ <0x00000002, "TBUFFER_LOAD_FORMAT_XYZ", []>; 453def TBUFFER_LOAD_FORMAT_XYZW : MTBUF_Load_Helper <0x00000003, "TBUFFER_LOAD_FORMAT_XYZW", VReg_128>; 454//def TBUFFER_STORE_FORMAT_X : MTBUF_ <0x00000004, "TBUFFER_STORE_FORMAT_X", []>; 455//def TBUFFER_STORE_FORMAT_XY : MTBUF_ <0x00000005, "TBUFFER_STORE_FORMAT_XY", []>; 456//def TBUFFER_STORE_FORMAT_XYZ : MTBUF_ <0x00000006, "TBUFFER_STORE_FORMAT_XYZ", []>; 457//def TBUFFER_STORE_FORMAT_XYZW : MTBUF_ <0x00000007, "TBUFFER_STORE_FORMAT_XYZW", []>; 458 459let mayLoad = 1 in { 460 461defm S_LOAD_DWORD : SMRD_Helper <0x00, "S_LOAD_DWORD", SReg_64, SReg_32>; 462defm S_LOAD_DWORDX2 : SMRD_Helper <0x01, "S_LOAD_DWORDX2", SReg_64, SReg_64>; 463defm S_LOAD_DWORDX4 : SMRD_Helper <0x02, "S_LOAD_DWORDX4", SReg_64, SReg_128>; 464defm S_LOAD_DWORDX8 : SMRD_Helper <0x03, "S_LOAD_DWORDX8", SReg_64, SReg_256>; 465defm S_LOAD_DWORDX16 : SMRD_Helper <0x04, "S_LOAD_DWORDX16", SReg_64, SReg_512>; 466 467defm S_BUFFER_LOAD_DWORD : SMRD_Helper < 468 0x08, "S_BUFFER_LOAD_DWORD", SReg_128, SReg_32 469>; 470 471defm S_BUFFER_LOAD_DWORDX2 : SMRD_Helper < 472 0x09, "S_BUFFER_LOAD_DWORDX2", SReg_128, SReg_64 473>; 474 475defm S_BUFFER_LOAD_DWORDX4 : SMRD_Helper < 476 0x0a, "S_BUFFER_LOAD_DWORDX4", SReg_128, SReg_128 477>; 478 479defm S_BUFFER_LOAD_DWORDX8 : SMRD_Helper < 480 0x0b, "S_BUFFER_LOAD_DWORDX8", SReg_128, SReg_256 481>; 482 483defm S_BUFFER_LOAD_DWORDX16 : SMRD_Helper < 484 0x0c, "S_BUFFER_LOAD_DWORDX16", SReg_128, SReg_512 485>; 486 487} // mayLoad = 1 488 489//def S_MEMTIME : SMRD_ <0x0000001e, "S_MEMTIME", []>; 490//def S_DCACHE_INV : SMRD_ <0x0000001f, "S_DCACHE_INV", []>; 491//def IMAGE_LOAD : MIMG_NoPattern_ <"IMAGE_LOAD", 0x00000000>; 492//def IMAGE_LOAD_MIP : MIMG_NoPattern_ <"IMAGE_LOAD_MIP", 0x00000001>; 493//def IMAGE_LOAD_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_PCK", 0x00000002>; 494//def IMAGE_LOAD_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_PCK_SGN", 0x00000003>; 495//def IMAGE_LOAD_MIP_PCK : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK", 0x00000004>; 496//def IMAGE_LOAD_MIP_PCK_SGN : MIMG_NoPattern_ <"IMAGE_LOAD_MIP_PCK_SGN", 0x00000005>; 497//def IMAGE_STORE : MIMG_NoPattern_ <"IMAGE_STORE", 0x00000008>; 498//def IMAGE_STORE_MIP : MIMG_NoPattern_ <"IMAGE_STORE_MIP", 0x00000009>; 499//def IMAGE_STORE_PCK : MIMG_NoPattern_ <"IMAGE_STORE_PCK", 0x0000000a>; 500//def IMAGE_STORE_MIP_PCK : MIMG_NoPattern_ <"IMAGE_STORE_MIP_PCK", 0x0000000b>; 501//def IMAGE_GET_RESINFO : MIMG_NoPattern_ <"IMAGE_GET_RESINFO", 0x0000000e>; 502//def IMAGE_ATOMIC_SWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_SWAP", 0x0000000f>; 503//def IMAGE_ATOMIC_CMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_CMPSWAP", 0x00000010>; 504//def IMAGE_ATOMIC_ADD : MIMG_NoPattern_ <"IMAGE_ATOMIC_ADD", 0x00000011>; 505//def IMAGE_ATOMIC_SUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_SUB", 0x00000012>; 506//def IMAGE_ATOMIC_RSUB : MIMG_NoPattern_ <"IMAGE_ATOMIC_RSUB", 0x00000013>; 507//def IMAGE_ATOMIC_SMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMIN", 0x00000014>; 508//def IMAGE_ATOMIC_UMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMIN", 0x00000015>; 509//def IMAGE_ATOMIC_SMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_SMAX", 0x00000016>; 510//def IMAGE_ATOMIC_UMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_UMAX", 0x00000017>; 511//def IMAGE_ATOMIC_AND : MIMG_NoPattern_ <"IMAGE_ATOMIC_AND", 0x00000018>; 512//def IMAGE_ATOMIC_OR : MIMG_NoPattern_ <"IMAGE_ATOMIC_OR", 0x00000019>; 513//def IMAGE_ATOMIC_XOR : MIMG_NoPattern_ <"IMAGE_ATOMIC_XOR", 0x0000001a>; 514//def IMAGE_ATOMIC_INC : MIMG_NoPattern_ <"IMAGE_ATOMIC_INC", 0x0000001b>; 515//def IMAGE_ATOMIC_DEC : MIMG_NoPattern_ <"IMAGE_ATOMIC_DEC", 0x0000001c>; 516//def IMAGE_ATOMIC_FCMPSWAP : MIMG_NoPattern_ <"IMAGE_ATOMIC_FCMPSWAP", 0x0000001d>; 517//def IMAGE_ATOMIC_FMIN : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMIN", 0x0000001e>; 518//def IMAGE_ATOMIC_FMAX : MIMG_NoPattern_ <"IMAGE_ATOMIC_FMAX", 0x0000001f>; 519def IMAGE_SAMPLE : MIMG_Load_Helper <0x00000020, "IMAGE_SAMPLE">; 520//def IMAGE_SAMPLE_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL", 0x00000021>; 521def IMAGE_SAMPLE_D : MIMG_Load_Helper <0x00000022, "IMAGE_SAMPLE_D">; 522//def IMAGE_SAMPLE_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL", 0x00000023>; 523def IMAGE_SAMPLE_L : MIMG_Load_Helper <0x00000024, "IMAGE_SAMPLE_L">; 524def IMAGE_SAMPLE_B : MIMG_Load_Helper <0x00000025, "IMAGE_SAMPLE_B">; 525//def IMAGE_SAMPLE_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL", 0x00000026>; 526//def IMAGE_SAMPLE_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ", 0x00000027>; 527def IMAGE_SAMPLE_C : MIMG_Load_Helper <0x00000028, "IMAGE_SAMPLE_C">; 528//def IMAGE_SAMPLE_C_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL", 0x00000029>; 529//def IMAGE_SAMPLE_C_D : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D", 0x0000002a>; 530//def IMAGE_SAMPLE_C_D_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL", 0x0000002b>; 531def IMAGE_SAMPLE_C_L : MIMG_Load_Helper <0x0000002c, "IMAGE_SAMPLE_C_L">; 532def IMAGE_SAMPLE_C_B : MIMG_Load_Helper <0x0000002d, "IMAGE_SAMPLE_C_B">; 533//def IMAGE_SAMPLE_C_B_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL", 0x0000002e>; 534//def IMAGE_SAMPLE_C_LZ : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ", 0x0000002f>; 535//def IMAGE_SAMPLE_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_O", 0x00000030>; 536//def IMAGE_SAMPLE_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CL_O", 0x00000031>; 537//def IMAGE_SAMPLE_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_O", 0x00000032>; 538//def IMAGE_SAMPLE_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_D_CL_O", 0x00000033>; 539//def IMAGE_SAMPLE_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_L_O", 0x00000034>; 540//def IMAGE_SAMPLE_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_O", 0x00000035>; 541//def IMAGE_SAMPLE_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_B_CL_O", 0x00000036>; 542//def IMAGE_SAMPLE_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_LZ_O", 0x00000037>; 543//def IMAGE_SAMPLE_C_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_O", 0x00000038>; 544//def IMAGE_SAMPLE_C_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CL_O", 0x00000039>; 545//def IMAGE_SAMPLE_C_D_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_O", 0x0000003a>; 546//def IMAGE_SAMPLE_C_D_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_D_CL_O", 0x0000003b>; 547//def IMAGE_SAMPLE_C_L_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_L_O", 0x0000003c>; 548//def IMAGE_SAMPLE_C_B_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_O", 0x0000003d>; 549//def IMAGE_SAMPLE_C_B_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_B_CL_O", 0x0000003e>; 550//def IMAGE_SAMPLE_C_LZ_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_LZ_O", 0x0000003f>; 551//def IMAGE_GATHER4 : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4", 0x00000040>; 552//def IMAGE_GATHER4_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL", 0x00000041>; 553//def IMAGE_GATHER4_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L", 0x00000044>; 554//def IMAGE_GATHER4_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B", 0x00000045>; 555//def IMAGE_GATHER4_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL", 0x00000046>; 556//def IMAGE_GATHER4_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ", 0x00000047>; 557//def IMAGE_GATHER4_C : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C", 0x00000048>; 558//def IMAGE_GATHER4_C_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL", 0x00000049>; 559//def IMAGE_GATHER4_C_L : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L", 0x0000004c>; 560//def IMAGE_GATHER4_C_B : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B", 0x0000004d>; 561//def IMAGE_GATHER4_C_B_CL : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL", 0x0000004e>; 562//def IMAGE_GATHER4_C_LZ : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ", 0x0000004f>; 563//def IMAGE_GATHER4_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_O", 0x00000050>; 564//def IMAGE_GATHER4_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_CL_O", 0x00000051>; 565//def IMAGE_GATHER4_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_L_O", 0x00000054>; 566//def IMAGE_GATHER4_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_O", 0x00000055>; 567//def IMAGE_GATHER4_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_B_CL_O", 0x00000056>; 568//def IMAGE_GATHER4_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_LZ_O", 0x00000057>; 569//def IMAGE_GATHER4_C_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_O", 0x00000058>; 570//def IMAGE_GATHER4_C_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_CL_O", 0x00000059>; 571//def IMAGE_GATHER4_C_L_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_L_O", 0x0000005c>; 572//def IMAGE_GATHER4_C_B_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_O", 0x0000005d>; 573//def IMAGE_GATHER4_C_B_CL_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_B_CL_O", 0x0000005e>; 574//def IMAGE_GATHER4_C_LZ_O : MIMG_NoPattern_GATHER4 <"IMAGE_GATHER4_C_LZ_O", 0x0000005f>; 575//def IMAGE_GET_LOD : MIMG_NoPattern_ <"IMAGE_GET_LOD", 0x00000060>; 576//def IMAGE_SAMPLE_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD", 0x00000068>; 577//def IMAGE_SAMPLE_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL", 0x00000069>; 578//def IMAGE_SAMPLE_C_CD : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD", 0x0000006a>; 579//def IMAGE_SAMPLE_C_CD_CL : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL", 0x0000006b>; 580//def IMAGE_SAMPLE_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_O", 0x0000006c>; 581//def IMAGE_SAMPLE_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_CD_CL_O", 0x0000006d>; 582//def IMAGE_SAMPLE_C_CD_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_O", 0x0000006e>; 583//def IMAGE_SAMPLE_C_CD_CL_O : MIMG_NoPattern_ <"IMAGE_SAMPLE_C_CD_CL_O", 0x0000006f>; 584//def IMAGE_RSRC256 : MIMG_NoPattern_RSRC256 <"IMAGE_RSRC256", 0x0000007e>; 585//def IMAGE_SAMPLER : MIMG_NoPattern_ <"IMAGE_SAMPLER", 0x0000007f>; 586//def V_NOP : VOP1_ <0x00000000, "V_NOP", []>; 587 588 589let neverHasSideEffects = 1, isMoveImm = 1 in { 590defm V_MOV_B32 : VOP1_32 <0x00000001, "V_MOV_B32", []>; 591} // End neverHasSideEffects = 1, isMoveImm = 1 592 593defm V_READFIRSTLANE_B32 : VOP1_32 <0x00000002, "V_READFIRSTLANE_B32", []>; 594//defm V_CVT_I32_F64 : VOP1_32 <0x00000003, "V_CVT_I32_F64", []>; 595//defm V_CVT_F64_I32 : VOP1_64 <0x00000004, "V_CVT_F64_I32", []>; 596defm V_CVT_F32_I32 : VOP1_32 <0x00000005, "V_CVT_F32_I32", 597 [(set VReg_32:$dst, (sint_to_fp VSrc_32:$src0))] 598>; 599//defm V_CVT_F32_U32 : VOP1_32 <0x00000006, "V_CVT_F32_U32", []>; 600//defm V_CVT_U32_F32 : VOP1_32 <0x00000007, "V_CVT_U32_F32", []>; 601defm V_CVT_I32_F32 : VOP1_32 <0x00000008, "V_CVT_I32_F32", 602 [(set (i32 VReg_32:$dst), (fp_to_sint VSrc_32:$src0))] 603>; 604defm V_MOV_FED_B32 : VOP1_32 <0x00000009, "V_MOV_FED_B32", []>; 605////def V_CVT_F16_F32 : VOP1_F16 <0x0000000a, "V_CVT_F16_F32", []>; 606//defm V_CVT_F32_F16 : VOP1_32 <0x0000000b, "V_CVT_F32_F16", []>; 607//defm V_CVT_RPI_I32_F32 : VOP1_32 <0x0000000c, "V_CVT_RPI_I32_F32", []>; 608//defm V_CVT_FLR_I32_F32 : VOP1_32 <0x0000000d, "V_CVT_FLR_I32_F32", []>; 609//defm V_CVT_OFF_F32_I4 : VOP1_32 <0x0000000e, "V_CVT_OFF_F32_I4", []>; 610//defm V_CVT_F32_F64 : VOP1_32 <0x0000000f, "V_CVT_F32_F64", []>; 611//defm V_CVT_F64_F32 : VOP1_64 <0x00000010, "V_CVT_F64_F32", []>; 612//defm V_CVT_F32_UBYTE0 : VOP1_32 <0x00000011, "V_CVT_F32_UBYTE0", []>; 613//defm V_CVT_F32_UBYTE1 : VOP1_32 <0x00000012, "V_CVT_F32_UBYTE1", []>; 614//defm V_CVT_F32_UBYTE2 : VOP1_32 <0x00000013, "V_CVT_F32_UBYTE2", []>; 615//defm V_CVT_F32_UBYTE3 : VOP1_32 <0x00000014, "V_CVT_F32_UBYTE3", []>; 616//defm V_CVT_U32_F64 : VOP1_32 <0x00000015, "V_CVT_U32_F64", []>; 617//defm V_CVT_F64_U32 : VOP1_64 <0x00000016, "V_CVT_F64_U32", []>; 618defm V_FRACT_F32 : VOP1_32 <0x00000020, "V_FRACT_F32", 619 [(set VReg_32:$dst, (AMDGPUfract VSrc_32:$src0))] 620>; 621defm V_TRUNC_F32 : VOP1_32 <0x00000021, "V_TRUNC_F32", []>; 622defm V_CEIL_F32 : VOP1_32 <0x00000022, "V_CEIL_F32", 623 [(set VReg_32:$dst, (fceil VSrc_32:$src0))] 624>; 625defm V_RNDNE_F32 : VOP1_32 <0x00000023, "V_RNDNE_F32", 626 [(set VReg_32:$dst, (frint VSrc_32:$src0))] 627>; 628defm V_FLOOR_F32 : VOP1_32 <0x00000024, "V_FLOOR_F32", 629 [(set VReg_32:$dst, (ffloor VSrc_32:$src0))] 630>; 631defm V_EXP_F32 : VOP1_32 <0x00000025, "V_EXP_F32", 632 [(set VReg_32:$dst, (fexp2 VSrc_32:$src0))] 633>; 634defm V_LOG_CLAMP_F32 : VOP1_32 <0x00000026, "V_LOG_CLAMP_F32", []>; 635defm V_LOG_F32 : VOP1_32 <0x00000027, "V_LOG_F32", 636 [(set VReg_32:$dst, (flog2 VSrc_32:$src0))] 637>; 638defm V_RCP_CLAMP_F32 : VOP1_32 <0x00000028, "V_RCP_CLAMP_F32", []>; 639defm V_RCP_LEGACY_F32 : VOP1_32 <0x00000029, "V_RCP_LEGACY_F32", []>; 640defm V_RCP_F32 : VOP1_32 <0x0000002a, "V_RCP_F32", 641 [(set VReg_32:$dst, (fdiv FP_ONE, VSrc_32:$src0))] 642>; 643defm V_RCP_IFLAG_F32 : VOP1_32 <0x0000002b, "V_RCP_IFLAG_F32", []>; 644defm V_RSQ_CLAMP_F32 : VOP1_32 <0x0000002c, "V_RSQ_CLAMP_F32", []>; 645defm V_RSQ_LEGACY_F32 : VOP1_32 < 646 0x0000002d, "V_RSQ_LEGACY_F32", 647 [(set VReg_32:$dst, (int_AMDGPU_rsq VSrc_32:$src0))] 648>; 649defm V_RSQ_F32 : VOP1_32 <0x0000002e, "V_RSQ_F32", []>; 650defm V_RCP_F64 : VOP1_64 <0x0000002f, "V_RCP_F64", []>; 651defm V_RCP_CLAMP_F64 : VOP1_64 <0x00000030, "V_RCP_CLAMP_F64", []>; 652defm V_RSQ_F64 : VOP1_64 <0x00000031, "V_RSQ_F64", []>; 653defm V_RSQ_CLAMP_F64 : VOP1_64 <0x00000032, "V_RSQ_CLAMP_F64", []>; 654defm V_SQRT_F32 : VOP1_32 <0x00000033, "V_SQRT_F32", []>; 655defm V_SQRT_F64 : VOP1_64 <0x00000034, "V_SQRT_F64", []>; 656defm V_SIN_F32 : VOP1_32 <0x00000035, "V_SIN_F32", []>; 657defm V_COS_F32 : VOP1_32 <0x00000036, "V_COS_F32", []>; 658defm V_NOT_B32 : VOP1_32 <0x00000037, "V_NOT_B32", []>; 659defm V_BFREV_B32 : VOP1_32 <0x00000038, "V_BFREV_B32", []>; 660defm V_FFBH_U32 : VOP1_32 <0x00000039, "V_FFBH_U32", []>; 661defm V_FFBL_B32 : VOP1_32 <0x0000003a, "V_FFBL_B32", []>; 662defm V_FFBH_I32 : VOP1_32 <0x0000003b, "V_FFBH_I32", []>; 663//defm V_FREXP_EXP_I32_F64 : VOP1_32 <0x0000003c, "V_FREXP_EXP_I32_F64", []>; 664defm V_FREXP_MANT_F64 : VOP1_64 <0x0000003d, "V_FREXP_MANT_F64", []>; 665defm V_FRACT_F64 : VOP1_64 <0x0000003e, "V_FRACT_F64", []>; 666//defm V_FREXP_EXP_I32_F32 : VOP1_32 <0x0000003f, "V_FREXP_EXP_I32_F32", []>; 667defm V_FREXP_MANT_F32 : VOP1_32 <0x00000040, "V_FREXP_MANT_F32", []>; 668//def V_CLREXCP : VOP1_ <0x00000041, "V_CLREXCP", []>; 669defm V_MOVRELD_B32 : VOP1_32 <0x00000042, "V_MOVRELD_B32", []>; 670defm V_MOVRELS_B32 : VOP1_32 <0x00000043, "V_MOVRELS_B32", []>; 671defm V_MOVRELSD_B32 : VOP1_32 <0x00000044, "V_MOVRELSD_B32", []>; 672 673def V_INTERP_P1_F32 : VINTRP < 674 0x00000000, 675 (outs VReg_32:$dst), 676 (ins VReg_32:$i, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 677 "V_INTERP_P1_F32 $dst, $i, $attr_chan, $attr, [$m0]", 678 []> { 679 let DisableEncoding = "$m0"; 680} 681 682def V_INTERP_P2_F32 : VINTRP < 683 0x00000001, 684 (outs VReg_32:$dst), 685 (ins VReg_32:$src0, VReg_32:$j, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 686 "V_INTERP_P2_F32 $dst, [$src0], $j, $attr_chan, $attr, [$m0]", 687 []> { 688 689 let Constraints = "$src0 = $dst"; 690 let DisableEncoding = "$src0,$m0"; 691 692} 693 694def V_INTERP_MOV_F32 : VINTRP < 695 0x00000002, 696 (outs VReg_32:$dst), 697 (ins InterpSlot:$src0, i32imm:$attr_chan, i32imm:$attr, M0Reg:$m0), 698 "V_INTERP_MOV_F32 $dst, $src0, $attr_chan, $attr, [$m0]", 699 []> { 700 let DisableEncoding = "$m0"; 701} 702 703//def S_NOP : SOPP_ <0x00000000, "S_NOP", []>; 704 705let isTerminator = 1 in { 706 707def S_ENDPGM : SOPP <0x00000001, (ins), "S_ENDPGM", 708 [(IL_retflag)]> { 709 let SIMM16 = 0; 710 let isBarrier = 1; 711 let hasCtrlDep = 1; 712} 713 714let isBranch = 1 in { 715def S_BRANCH : SOPP < 716 0x00000002, (ins brtarget:$target), "S_BRANCH $target", 717 [(br bb:$target)]> { 718 let isBarrier = 1; 719} 720 721let DisableEncoding = "$scc" in { 722def S_CBRANCH_SCC0 : SOPP < 723 0x00000004, (ins brtarget:$target, SCCReg:$scc), 724 "S_CBRANCH_SCC0 $target", [] 725>; 726def S_CBRANCH_SCC1 : SOPP < 727 0x00000005, (ins brtarget:$target, SCCReg:$scc), 728 "S_CBRANCH_SCC1 $target", 729 [] 730>; 731} // End DisableEncoding = "$scc" 732 733def S_CBRANCH_VCCZ : SOPP < 734 0x00000006, (ins brtarget:$target, VCCReg:$vcc), 735 "S_CBRANCH_VCCZ $target", 736 [] 737>; 738def S_CBRANCH_VCCNZ : SOPP < 739 0x00000007, (ins brtarget:$target, VCCReg:$vcc), 740 "S_CBRANCH_VCCNZ $target", 741 [] 742>; 743 744let DisableEncoding = "$exec" in { 745def S_CBRANCH_EXECZ : SOPP < 746 0x00000008, (ins brtarget:$target, EXECReg:$exec), 747 "S_CBRANCH_EXECZ $target", 748 [] 749>; 750def S_CBRANCH_EXECNZ : SOPP < 751 0x00000009, (ins brtarget:$target, EXECReg:$exec), 752 "S_CBRANCH_EXECNZ $target", 753 [] 754>; 755} // End DisableEncoding = "$exec" 756 757 758} // End isBranch = 1 759} // End isTerminator = 1 760 761//def S_BARRIER : SOPP_ <0x0000000a, "S_BARRIER", []>; 762let hasSideEffects = 1 in { 763def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16", 764 [] 765>; 766} // End hasSideEffects 767//def S_SETHALT : SOPP_ <0x0000000d, "S_SETHALT", []>; 768//def S_SLEEP : SOPP_ <0x0000000e, "S_SLEEP", []>; 769//def S_SETPRIO : SOPP_ <0x0000000f, "S_SETPRIO", []>; 770//def S_SENDMSG : SOPP_ <0x00000010, "S_SENDMSG", []>; 771//def S_SENDMSGHALT : SOPP_ <0x00000011, "S_SENDMSGHALT", []>; 772//def S_TRAP : SOPP_ <0x00000012, "S_TRAP", []>; 773//def S_ICACHE_INV : SOPP_ <0x00000013, "S_ICACHE_INV", []>; 774//def S_INCPERFLEVEL : SOPP_ <0x00000014, "S_INCPERFLEVEL", []>; 775//def S_DECPERFLEVEL : SOPP_ <0x00000015, "S_DECPERFLEVEL", []>; 776//def S_TTRACEDATA : SOPP_ <0x00000016, "S_TTRACEDATA", []>; 777 778def V_CNDMASK_B32_e32 : VOP2 <0x00000000, (outs VReg_32:$dst), 779 (ins VSrc_32:$src0, VReg_32:$src1, VCCReg:$vcc), 780 "V_CNDMASK_B32_e32 $dst, $src0, $src1, [$vcc]", 781 [] 782>{ 783 let DisableEncoding = "$vcc"; 784} 785 786def V_CNDMASK_B32_e64 : VOP3 <0x00000100, (outs VReg_32:$dst), 787 (ins VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2, 788 InstFlag:$abs, InstFlag:$clamp, InstFlag:$omod, InstFlag:$neg), 789 "V_CNDMASK_B32_e64 $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", 790 [(set (i32 VReg_32:$dst), (select (i1 SSrc_64:$src2), 791 VSrc_32:$src1, VSrc_32:$src0))] 792>; 793 794//f32 pattern for V_CNDMASK_B32_e64 795def : Pat < 796 (f32 (select (i1 SSrc_64:$src2), VSrc_32:$src1, VSrc_32:$src0)), 797 (V_CNDMASK_B32_e64 VSrc_32:$src0, VSrc_32:$src1, SSrc_64:$src2) 798>; 799 800defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>; 801defm V_WRITELANE_B32 : VOP2_32 <0x00000002, "V_WRITELANE_B32", []>; 802 803let isCommutable = 1 in { 804defm V_ADD_F32 : VOP2_32 <0x00000003, "V_ADD_F32", 805 [(set VReg_32:$dst, (fadd VSrc_32:$src0, VReg_32:$src1))] 806>; 807 808defm V_SUB_F32 : VOP2_32 <0x00000004, "V_SUB_F32", 809 [(set VReg_32:$dst, (fsub VSrc_32:$src0, VReg_32:$src1))] 810>; 811defm V_SUBREV_F32 : VOP2_32 <0x00000005, "V_SUBREV_F32", [], "V_SUB_F32">; 812} // End isCommutable = 1 813 814defm V_MAC_LEGACY_F32 : VOP2_32 <0x00000006, "V_MAC_LEGACY_F32", []>; 815 816let isCommutable = 1 in { 817 818defm V_MUL_LEGACY_F32 : VOP2_32 < 819 0x00000007, "V_MUL_LEGACY_F32", 820 [(set VReg_32:$dst, (int_AMDGPU_mul VSrc_32:$src0, VReg_32:$src1))] 821>; 822 823defm V_MUL_F32 : VOP2_32 <0x00000008, "V_MUL_F32", 824 [(set VReg_32:$dst, (fmul VSrc_32:$src0, VReg_32:$src1))] 825>; 826 827} // End isCommutable = 1 828 829//defm V_MUL_I32_I24 : VOP2_32 <0x00000009, "V_MUL_I32_I24", []>; 830//defm V_MUL_HI_I32_I24 : VOP2_32 <0x0000000a, "V_MUL_HI_I32_I24", []>; 831//defm V_MUL_U32_U24 : VOP2_32 <0x0000000b, "V_MUL_U32_U24", []>; 832//defm V_MUL_HI_U32_U24 : VOP2_32 <0x0000000c, "V_MUL_HI_U32_U24", []>; 833 834let isCommutable = 1 in { 835 836defm V_MIN_LEGACY_F32 : VOP2_32 <0x0000000d, "V_MIN_LEGACY_F32", 837 [(set VReg_32:$dst, (AMDGPUfmin VSrc_32:$src0, VReg_32:$src1))] 838>; 839 840defm V_MAX_LEGACY_F32 : VOP2_32 <0x0000000e, "V_MAX_LEGACY_F32", 841 [(set VReg_32:$dst, (AMDGPUfmax VSrc_32:$src0, VReg_32:$src1))] 842>; 843 844defm V_MIN_F32 : VOP2_32 <0x0000000f, "V_MIN_F32", []>; 845defm V_MAX_F32 : VOP2_32 <0x00000010, "V_MAX_F32", []>; 846defm V_MIN_I32 : VOP2_32 <0x00000011, "V_MIN_I32", []>; 847defm V_MAX_I32 : VOP2_32 <0x00000012, "V_MAX_I32", []>; 848defm V_MIN_U32 : VOP2_32 <0x00000013, "V_MIN_U32", []>; 849defm V_MAX_U32 : VOP2_32 <0x00000014, "V_MAX_U32", []>; 850 851defm V_LSHR_B32 : VOP2_32 <0x00000015, "V_LSHR_B32", 852 [(set VReg_32:$dst, (srl VSrc_32:$src0, (i32 VReg_32:$src1)))] 853>; 854defm V_LSHRREV_B32 : VOP2_32 <0x00000016, "V_LSHRREV_B32", [], "V_LSHR_B32">; 855 856defm V_ASHR_I32 : VOP2_32 <0x00000017, "V_ASHR_I32", 857 [(set VReg_32:$dst, (sra VSrc_32:$src0, (i32 VReg_32:$src1)))] 858>; 859defm V_ASHRREV_I32 : VOP2_32 <0x00000018, "V_ASHRREV_I32", [], "V_ASHR_I32">; 860 861defm V_LSHL_B32 : VOP2_32 <0x00000019, "V_LSHL_B32", 862 [(set VReg_32:$dst, (shl VSrc_32:$src0, (i32 VReg_32:$src1)))] 863>; 864defm V_LSHLREV_B32 : VOP2_32 <0x0000001a, "V_LSHLREV_B32", [], "V_LSHL_B32">; 865 866defm V_AND_B32 : VOP2_32 <0x0000001b, "V_AND_B32", 867 [(set VReg_32:$dst, (and VSrc_32:$src0, VReg_32:$src1))] 868>; 869defm V_OR_B32 : VOP2_32 <0x0000001c, "V_OR_B32", 870 [(set VReg_32:$dst, (or VSrc_32:$src0, VReg_32:$src1))] 871>; 872defm V_XOR_B32 : VOP2_32 <0x0000001d, "V_XOR_B32", 873 [(set VReg_32:$dst, (xor VSrc_32:$src0, VReg_32:$src1))] 874>; 875 876} // End isCommutable = 1 877 878defm V_BFM_B32 : VOP2_32 <0x0000001e, "V_BFM_B32", []>; 879defm V_MAC_F32 : VOP2_32 <0x0000001f, "V_MAC_F32", []>; 880defm V_MADMK_F32 : VOP2_32 <0x00000020, "V_MADMK_F32", []>; 881defm V_MADAK_F32 : VOP2_32 <0x00000021, "V_MADAK_F32", []>; 882//defm V_BCNT_U32_B32 : VOP2_32 <0x00000022, "V_BCNT_U32_B32", []>; 883//defm V_MBCNT_LO_U32_B32 : VOP2_32 <0x00000023, "V_MBCNT_LO_U32_B32", []>; 884//defm V_MBCNT_HI_U32_B32 : VOP2_32 <0x00000024, "V_MBCNT_HI_U32_B32", []>; 885 886let isCommutable = 1, Defs = [VCC] in { // Carry-out goes to VCC 887defm V_ADD_I32 : VOP2b_32 <0x00000025, "V_ADD_I32", 888 [(set VReg_32:$dst, (add (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))] 889>; 890 891defm V_SUB_I32 : VOP2b_32 <0x00000026, "V_SUB_I32", 892 [(set VReg_32:$dst, (sub (i32 VSrc_32:$src0), (i32 VReg_32:$src1)))] 893>; 894defm V_SUBREV_I32 : VOP2b_32 <0x00000027, "V_SUBREV_I32", [], "V_SUB_I32">; 895 896let Uses = [VCC] in { // Carry-out comes from VCC 897defm V_ADDC_U32 : VOP2b_32 <0x00000028, "V_ADDC_U32", []>; 898defm V_SUBB_U32 : VOP2b_32 <0x00000029, "V_SUBB_U32", []>; 899defm V_SUBBREV_U32 : VOP2b_32 <0x0000002a, "V_SUBBREV_U32", [], "V_SUBB_U32">; 900} // End Uses = [VCC] 901} // End isCommutable = 1, Defs = [VCC] 902 903defm V_LDEXP_F32 : VOP2_32 <0x0000002b, "V_LDEXP_F32", []>; 904////def V_CVT_PKACCUM_U8_F32 : VOP2_U8 <0x0000002c, "V_CVT_PKACCUM_U8_F32", []>; 905////def V_CVT_PKNORM_I16_F32 : VOP2_I16 <0x0000002d, "V_CVT_PKNORM_I16_F32", []>; 906////def V_CVT_PKNORM_U16_F32 : VOP2_U16 <0x0000002e, "V_CVT_PKNORM_U16_F32", []>; 907defm V_CVT_PKRTZ_F16_F32 : VOP2_32 <0x0000002f, "V_CVT_PKRTZ_F16_F32", 908 [(set VReg_32:$dst, (int_SI_packf16 VSrc_32:$src0, VReg_32:$src1))] 909>; 910////def V_CVT_PK_U16_U32 : VOP2_U16 <0x00000030, "V_CVT_PK_U16_U32", []>; 911////def V_CVT_PK_I16_I32 : VOP2_I16 <0x00000031, "V_CVT_PK_I16_I32", []>; 912def S_CMP_EQ_I32 : SOPC_32 <0x00000000, "S_CMP_EQ_I32", []>; 913def S_CMP_LG_I32 : SOPC_32 <0x00000001, "S_CMP_LG_I32", []>; 914def S_CMP_GT_I32 : SOPC_32 <0x00000002, "S_CMP_GT_I32", []>; 915def S_CMP_GE_I32 : SOPC_32 <0x00000003, "S_CMP_GE_I32", []>; 916def S_CMP_LT_I32 : SOPC_32 <0x00000004, "S_CMP_LT_I32", []>; 917def S_CMP_LE_I32 : SOPC_32 <0x00000005, "S_CMP_LE_I32", []>; 918def S_CMP_EQ_U32 : SOPC_32 <0x00000006, "S_CMP_EQ_U32", []>; 919def S_CMP_LG_U32 : SOPC_32 <0x00000007, "S_CMP_LG_U32", []>; 920def S_CMP_GT_U32 : SOPC_32 <0x00000008, "S_CMP_GT_U32", []>; 921def S_CMP_GE_U32 : SOPC_32 <0x00000009, "S_CMP_GE_U32", []>; 922def S_CMP_LT_U32 : SOPC_32 <0x0000000a, "S_CMP_LT_U32", []>; 923def S_CMP_LE_U32 : SOPC_32 <0x0000000b, "S_CMP_LE_U32", []>; 924////def S_BITCMP0_B32 : SOPC_BITCMP0 <0x0000000c, "S_BITCMP0_B32", []>; 925////def S_BITCMP1_B32 : SOPC_BITCMP1 <0x0000000d, "S_BITCMP1_B32", []>; 926////def S_BITCMP0_B64 : SOPC_BITCMP0 <0x0000000e, "S_BITCMP0_B64", []>; 927////def S_BITCMP1_B64 : SOPC_BITCMP1 <0x0000000f, "S_BITCMP1_B64", []>; 928//def S_SETVSKIP : SOPC_ <0x00000010, "S_SETVSKIP", []>; 929 930let neverHasSideEffects = 1 in { 931 932def V_MAD_LEGACY_F32 : VOP3_32 <0x00000140, "V_MAD_LEGACY_F32", []>; 933def V_MAD_F32 : VOP3_32 <0x00000141, "V_MAD_F32", []>; 934//def V_MAD_I32_I24 : VOP3_32 <0x00000142, "V_MAD_I32_I24", []>; 935//def V_MAD_U32_U24 : VOP3_32 <0x00000143, "V_MAD_U32_U24", []>; 936 937} // End neverHasSideEffects 938def V_CUBEID_F32 : VOP3_32 <0x00000144, "V_CUBEID_F32", []>; 939def V_CUBESC_F32 : VOP3_32 <0x00000145, "V_CUBESC_F32", []>; 940def V_CUBETC_F32 : VOP3_32 <0x00000146, "V_CUBETC_F32", []>; 941def V_CUBEMA_F32 : VOP3_32 <0x00000147, "V_CUBEMA_F32", []>; 942def V_BFE_U32 : VOP3_32 <0x00000148, "V_BFE_U32", []>; 943def V_BFE_I32 : VOP3_32 <0x00000149, "V_BFE_I32", []>; 944def V_BFI_B32 : VOP3_32 <0x0000014a, "V_BFI_B32", []>; 945def V_FMA_F32 : VOP3_32 <0x0000014b, "V_FMA_F32", []>; 946def V_FMA_F64 : VOP3_64 <0x0000014c, "V_FMA_F64", []>; 947//def V_LERP_U8 : VOP3_U8 <0x0000014d, "V_LERP_U8", []>; 948def V_ALIGNBIT_B32 : VOP3_32 <0x0000014e, "V_ALIGNBIT_B32", []>; 949def V_ALIGNBYTE_B32 : VOP3_32 <0x0000014f, "V_ALIGNBYTE_B32", []>; 950def V_MULLIT_F32 : VOP3_32 <0x00000150, "V_MULLIT_F32", []>; 951////def V_MIN3_F32 : VOP3_MIN3 <0x00000151, "V_MIN3_F32", []>; 952////def V_MIN3_I32 : VOP3_MIN3 <0x00000152, "V_MIN3_I32", []>; 953////def V_MIN3_U32 : VOP3_MIN3 <0x00000153, "V_MIN3_U32", []>; 954////def V_MAX3_F32 : VOP3_MAX3 <0x00000154, "V_MAX3_F32", []>; 955////def V_MAX3_I32 : VOP3_MAX3 <0x00000155, "V_MAX3_I32", []>; 956////def V_MAX3_U32 : VOP3_MAX3 <0x00000156, "V_MAX3_U32", []>; 957////def V_MED3_F32 : VOP3_MED3 <0x00000157, "V_MED3_F32", []>; 958////def V_MED3_I32 : VOP3_MED3 <0x00000158, "V_MED3_I32", []>; 959////def V_MED3_U32 : VOP3_MED3 <0x00000159, "V_MED3_U32", []>; 960//def V_SAD_U8 : VOP3_U8 <0x0000015a, "V_SAD_U8", []>; 961//def V_SAD_HI_U8 : VOP3_U8 <0x0000015b, "V_SAD_HI_U8", []>; 962//def V_SAD_U16 : VOP3_U16 <0x0000015c, "V_SAD_U16", []>; 963def V_SAD_U32 : VOP3_32 <0x0000015d, "V_SAD_U32", []>; 964////def V_CVT_PK_U8_F32 : VOP3_U8 <0x0000015e, "V_CVT_PK_U8_F32", []>; 965def V_DIV_FIXUP_F32 : VOP3_32 <0x0000015f, "V_DIV_FIXUP_F32", []>; 966def V_DIV_FIXUP_F64 : VOP3_64 <0x00000160, "V_DIV_FIXUP_F64", []>; 967def V_LSHL_B64 : VOP3_64 <0x00000161, "V_LSHL_B64", []>; 968def V_LSHR_B64 : VOP3_64 <0x00000162, "V_LSHR_B64", []>; 969def V_ASHR_I64 : VOP3_64 <0x00000163, "V_ASHR_I64", []>; 970def V_ADD_F64 : VOP3_64 <0x00000164, "V_ADD_F64", []>; 971def V_MUL_F64 : VOP3_64 <0x00000165, "V_MUL_F64", []>; 972def V_MIN_F64 : VOP3_64 <0x00000166, "V_MIN_F64", []>; 973def V_MAX_F64 : VOP3_64 <0x00000167, "V_MAX_F64", []>; 974def V_LDEXP_F64 : VOP3_64 <0x00000168, "V_LDEXP_F64", []>; 975 976let isCommutable = 1 in { 977 978def V_MUL_LO_U32 : VOP3_32 <0x00000169, "V_MUL_LO_U32", []>; 979def V_MUL_HI_U32 : VOP3_32 <0x0000016a, "V_MUL_HI_U32", []>; 980def V_MUL_LO_I32 : VOP3_32 <0x0000016b, "V_MUL_LO_I32", []>; 981def V_MUL_HI_I32 : VOP3_32 <0x0000016c, "V_MUL_HI_I32", []>; 982 983} // isCommutable = 1 984 985def : Pat < 986 (mul VSrc_32:$src0, VReg_32:$src1), 987 (V_MUL_LO_I32 VSrc_32:$src0, VReg_32:$src1, (i32 0), 0, 0, 0, 0) 988>; 989 990def : Pat < 991 (mulhu VSrc_32:$src0, VReg_32:$src1), 992 (V_MUL_HI_U32 VSrc_32:$src0, VReg_32:$src1, (i32 0), 0, 0, 0, 0) 993>; 994 995def : Pat < 996 (mulhs VSrc_32:$src0, VReg_32:$src1), 997 (V_MUL_HI_I32 VSrc_32:$src0, VReg_32:$src1, (i32 0), 0, 0, 0, 0) 998>; 999 1000def V_DIV_SCALE_F32 : VOP3_32 <0x0000016d, "V_DIV_SCALE_F32", []>; 1001def V_DIV_SCALE_F64 : VOP3_64 <0x0000016e, "V_DIV_SCALE_F64", []>; 1002def V_DIV_FMAS_F32 : VOP3_32 <0x0000016f, "V_DIV_FMAS_F32", []>; 1003def V_DIV_FMAS_F64 : VOP3_64 <0x00000170, "V_DIV_FMAS_F64", []>; 1004//def V_MSAD_U8 : VOP3_U8 <0x00000171, "V_MSAD_U8", []>; 1005//def V_QSAD_U8 : VOP3_U8 <0x00000172, "V_QSAD_U8", []>; 1006//def V_MQSAD_U8 : VOP3_U8 <0x00000173, "V_MQSAD_U8", []>; 1007def V_TRIG_PREOP_F64 : VOP3_64 <0x00000174, "V_TRIG_PREOP_F64", []>; 1008def S_ADD_U32 : SOP2_32 <0x00000000, "S_ADD_U32", []>; 1009def S_SUB_U32 : SOP2_32 <0x00000001, "S_SUB_U32", []>; 1010def S_ADD_I32 : SOP2_32 <0x00000002, "S_ADD_I32", []>; 1011def S_SUB_I32 : SOP2_32 <0x00000003, "S_SUB_I32", []>; 1012def S_ADDC_U32 : SOP2_32 <0x00000004, "S_ADDC_U32", []>; 1013def S_SUBB_U32 : SOP2_32 <0x00000005, "S_SUBB_U32", []>; 1014def S_MIN_I32 : SOP2_32 <0x00000006, "S_MIN_I32", []>; 1015def S_MIN_U32 : SOP2_32 <0x00000007, "S_MIN_U32", []>; 1016def S_MAX_I32 : SOP2_32 <0x00000008, "S_MAX_I32", []>; 1017def S_MAX_U32 : SOP2_32 <0x00000009, "S_MAX_U32", []>; 1018 1019def S_CSELECT_B32 : SOP2 < 1020 0x0000000a, (outs SReg_32:$dst), 1021 (ins SReg_32:$src0, SReg_32:$src1, SCCReg:$scc), "S_CSELECT_B32", 1022 [(set (i32 SReg_32:$dst), (select (i1 SCCReg:$scc), 1023 SReg_32:$src0, SReg_32:$src1))] 1024>; 1025 1026def S_CSELECT_B64 : SOP2_64 <0x0000000b, "S_CSELECT_B64", []>; 1027 1028// f32 pattern for S_CSELECT_B32 1029def : Pat < 1030 (f32 (select (i1 SCCReg:$scc), SReg_32:$src0, SReg_32:$src1)), 1031 (S_CSELECT_B32 SReg_32:$src0, SReg_32:$src1, SCCReg:$scc) 1032>; 1033 1034def S_AND_B32 : SOP2_32 <0x0000000e, "S_AND_B32", []>; 1035 1036def S_AND_B64 : SOP2_64 <0x0000000f, "S_AND_B64", 1037 [(set SReg_64:$dst, (i64 (and SSrc_64:$src0, SSrc_64:$src1)))] 1038>; 1039 1040def : Pat < 1041 (i1 (and SSrc_64:$src0, SSrc_64:$src1)), 1042 (S_AND_B64 SSrc_64:$src0, SSrc_64:$src1) 1043>; 1044 1045def S_OR_B32 : SOP2_32 <0x00000010, "S_OR_B32", []>; 1046def S_OR_B64 : SOP2_64 <0x00000011, "S_OR_B64", []>; 1047def : Pat < 1048 (i1 (or SSrc_64:$src0, SSrc_64:$src1)), 1049 (S_OR_B64 SSrc_64:$src0, SSrc_64:$src1) 1050>; 1051def S_XOR_B32 : SOP2_32 <0x00000012, "S_XOR_B32", []>; 1052def S_XOR_B64 : SOP2_64 <0x00000013, "S_XOR_B64", []>; 1053def S_ANDN2_B32 : SOP2_32 <0x00000014, "S_ANDN2_B32", []>; 1054def S_ANDN2_B64 : SOP2_64 <0x00000015, "S_ANDN2_B64", []>; 1055def S_ORN2_B32 : SOP2_32 <0x00000016, "S_ORN2_B32", []>; 1056def S_ORN2_B64 : SOP2_64 <0x00000017, "S_ORN2_B64", []>; 1057def S_NAND_B32 : SOP2_32 <0x00000018, "S_NAND_B32", []>; 1058def S_NAND_B64 : SOP2_64 <0x00000019, "S_NAND_B64", []>; 1059def S_NOR_B32 : SOP2_32 <0x0000001a, "S_NOR_B32", []>; 1060def S_NOR_B64 : SOP2_64 <0x0000001b, "S_NOR_B64", []>; 1061def S_XNOR_B32 : SOP2_32 <0x0000001c, "S_XNOR_B32", []>; 1062def S_XNOR_B64 : SOP2_64 <0x0000001d, "S_XNOR_B64", []>; 1063def S_LSHL_B32 : SOP2_32 <0x0000001e, "S_LSHL_B32", []>; 1064def S_LSHL_B64 : SOP2_64 <0x0000001f, "S_LSHL_B64", []>; 1065def S_LSHR_B32 : SOP2_32 <0x00000020, "S_LSHR_B32", []>; 1066def S_LSHR_B64 : SOP2_64 <0x00000021, "S_LSHR_B64", []>; 1067def S_ASHR_I32 : SOP2_32 <0x00000022, "S_ASHR_I32", []>; 1068def S_ASHR_I64 : SOP2_64 <0x00000023, "S_ASHR_I64", []>; 1069def S_BFM_B32 : SOP2_32 <0x00000024, "S_BFM_B32", []>; 1070def S_BFM_B64 : SOP2_64 <0x00000025, "S_BFM_B64", []>; 1071def S_MUL_I32 : SOP2_32 <0x00000026, "S_MUL_I32", []>; 1072def S_BFE_U32 : SOP2_32 <0x00000027, "S_BFE_U32", []>; 1073def S_BFE_I32 : SOP2_32 <0x00000028, "S_BFE_I32", []>; 1074def S_BFE_U64 : SOP2_64 <0x00000029, "S_BFE_U64", []>; 1075def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>; 1076//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>; 1077def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>; 1078 1079let isCodeGenOnly = 1, isPseudo = 1 in { 1080 1081def LOAD_CONST : AMDGPUShaderInst < 1082 (outs GPRF32:$dst), 1083 (ins i32imm:$src), 1084 "LOAD_CONST $dst, $src", 1085 [(set GPRF32:$dst, (int_AMDGPU_load_const imm:$src))] 1086>; 1087 1088// SI Psuedo instructions. These are used by the CFG structurizer pass 1089// and should be lowered to ISA instructions prior to codegen. 1090 1091let mayLoad = 1, mayStore = 1, hasSideEffects = 1, 1092 Uses = [EXEC], Defs = [EXEC] in { 1093 1094let isBranch = 1, isTerminator = 1 in { 1095 1096def SI_IF : InstSI < 1097 (outs SReg_64:$dst), 1098 (ins SReg_64:$vcc, brtarget:$target), 1099 "SI_IF $dst, $vcc, $target", 1100 [(set SReg_64:$dst, (int_SI_if SReg_64:$vcc, bb:$target))] 1101>; 1102 1103def SI_ELSE : InstSI < 1104 (outs SReg_64:$dst), 1105 (ins SReg_64:$src, brtarget:$target), 1106 "SI_ELSE $dst, $src, $target", 1107 [(set SReg_64:$dst, (int_SI_else SReg_64:$src, bb:$target))]> { 1108 1109 let Constraints = "$src = $dst"; 1110} 1111 1112def SI_LOOP : InstSI < 1113 (outs), 1114 (ins SReg_64:$saved, brtarget:$target), 1115 "SI_LOOP $saved, $target", 1116 [(int_SI_loop SReg_64:$saved, bb:$target)] 1117>; 1118 1119} // end isBranch = 1, isTerminator = 1 1120 1121def SI_BREAK : InstSI < 1122 (outs SReg_64:$dst), 1123 (ins SReg_64:$src), 1124 "SI_ELSE $dst, $src", 1125 [(set SReg_64:$dst, (int_SI_break SReg_64:$src))] 1126>; 1127 1128def SI_IF_BREAK : InstSI < 1129 (outs SReg_64:$dst), 1130 (ins SReg_64:$vcc, SReg_64:$src), 1131 "SI_IF_BREAK $dst, $vcc, $src", 1132 [(set SReg_64:$dst, (int_SI_if_break SReg_64:$vcc, SReg_64:$src))] 1133>; 1134 1135def SI_ELSE_BREAK : InstSI < 1136 (outs SReg_64:$dst), 1137 (ins SReg_64:$src0, SReg_64:$src1), 1138 "SI_ELSE_BREAK $dst, $src0, $src1", 1139 [(set SReg_64:$dst, (int_SI_else_break SReg_64:$src0, SReg_64:$src1))] 1140>; 1141 1142def SI_END_CF : InstSI < 1143 (outs), 1144 (ins SReg_64:$saved), 1145 "SI_END_CF $saved", 1146 [(int_SI_end_cf SReg_64:$saved)] 1147>; 1148 1149def SI_KILL : InstSI < 1150 (outs), 1151 (ins VReg_32:$src), 1152 "SI_KIL $src", 1153 [(int_AMDGPU_kill VReg_32:$src)] 1154>; 1155 1156} // end mayLoad = 1, mayStore = 1, hasSideEffects = 1 1157 // Uses = [EXEC], Defs = [EXEC] 1158 1159let Uses = [EXEC], Defs = [EXEC,VCC,M0] in { 1160 1161def SI_INDIRECT_SRC : InstSI < 1162 (outs VReg_32:$dst, SReg_64:$temp), 1163 (ins unknown:$src, VSrc_32:$idx, i32imm:$off), 1164 "SI_INDIRECT_SRC $dst, $temp, $src, $idx, $off", 1165 [] 1166>; 1167 1168class SI_INDIRECT_DST<RegisterClass rc> : InstSI < 1169 (outs rc:$dst, SReg_64:$temp), 1170 (ins unknown:$src, VSrc_32:$idx, i32imm:$off, VReg_32:$val), 1171 "SI_INDIRECT_DST $dst, $temp, $src, $idx, $off, $val", 1172 [] 1173> { 1174 let Constraints = "$src = $dst"; 1175} 1176 1177def SI_INDIRECT_DST_V2 : SI_INDIRECT_DST<VReg_64>; 1178def SI_INDIRECT_DST_V4 : SI_INDIRECT_DST<VReg_128>; 1179def SI_INDIRECT_DST_V8 : SI_INDIRECT_DST<VReg_256>; 1180def SI_INDIRECT_DST_V16 : SI_INDIRECT_DST<VReg_512>; 1181 1182} // Uses = [EXEC,VCC,M0], Defs = [EXEC,VCC,M0] 1183 1184} // end IsCodeGenOnly, isPseudo 1185 1186def : Pat< 1187 (int_AMDGPU_cndlt VReg_32:$src0, VReg_32:$src1, VReg_32:$src2), 1188 (V_CNDMASK_B32_e64 VReg_32:$src2, VReg_32:$src1, (V_CMP_GT_F32_e64 0, VReg_32:$src0)) 1189>; 1190 1191def : Pat < 1192 (int_AMDGPU_kilp), 1193 (SI_KILL (V_MOV_B32_e32 0xbf800000)) 1194>; 1195 1196/* int_SI_vs_load_input */ 1197def : Pat< 1198 (int_SI_vs_load_input SReg_128:$tlst, IMM12bit:$attr_offset, 1199 VReg_32:$buf_idx_vgpr), 1200 (BUFFER_LOAD_FORMAT_XYZW imm:$attr_offset, 0, 1, 0, 0, 0, 1201 VReg_32:$buf_idx_vgpr, SReg_128:$tlst, 1202 0, 0, 0) 1203>; 1204 1205/* int_SI_export */ 1206def : Pat < 1207 (int_SI_export imm:$en, imm:$vm, imm:$done, imm:$tgt, imm:$compr, 1208 VReg_32:$src0,VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), 1209 (EXP imm:$en, imm:$tgt, imm:$compr, imm:$done, imm:$vm, 1210 VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3) 1211>; 1212 1213 1214/* int_SI_sample for simple 1D texture lookup */ 1215def : Pat < 1216 (int_SI_sample imm:$writemask, VReg_32:$addr, 1217 SReg_256:$rsrc, SReg_128:$sampler, imm), 1218 (IMAGE_SAMPLE imm:$writemask, 0, 0, 0, 0, 0, 0, 0, VReg_32:$addr, 1219 SReg_256:$rsrc, SReg_128:$sampler) 1220>; 1221 1222class SamplePattern<Intrinsic name, MIMG opcode, RegisterClass addr_class, 1223 ValueType addr_type> : Pat < 1224 (name imm:$writemask, (addr_type addr_class:$addr), 1225 SReg_256:$rsrc, SReg_128:$sampler, imm), 1226 (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr, 1227 SReg_256:$rsrc, SReg_128:$sampler) 1228>; 1229 1230class SampleRectPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class, 1231 ValueType addr_type> : Pat < 1232 (name imm:$writemask, (addr_type addr_class:$addr), 1233 SReg_256:$rsrc, SReg_128:$sampler, TEX_RECT), 1234 (opcode imm:$writemask, 1, 0, 0, 0, 0, 0, 0, addr_class:$addr, 1235 SReg_256:$rsrc, SReg_128:$sampler) 1236>; 1237 1238class SampleArrayPattern<Intrinsic name, MIMG opcode, RegisterClass addr_class, 1239 ValueType addr_type> : Pat < 1240 (name imm:$writemask, (addr_type addr_class:$addr), 1241 SReg_256:$rsrc, SReg_128:$sampler, TEX_ARRAY), 1242 (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr, 1243 SReg_256:$rsrc, SReg_128:$sampler) 1244>; 1245 1246class SampleShadowPattern<Intrinsic name, MIMG opcode, 1247 RegisterClass addr_class, ValueType addr_type> : Pat < 1248 (name imm:$writemask, (addr_type addr_class:$addr), 1249 SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW), 1250 (opcode imm:$writemask, 0, 0, 0, 0, 0, 0, 0, addr_class:$addr, 1251 SReg_256:$rsrc, SReg_128:$sampler) 1252>; 1253 1254class SampleShadowArrayPattern<Intrinsic name, MIMG opcode, 1255 RegisterClass addr_class, ValueType addr_type> : Pat < 1256 (name imm:$writemask, (addr_type addr_class:$addr), 1257 SReg_256:$rsrc, SReg_128:$sampler, TEX_SHADOW_ARRAY), 1258 (opcode imm:$writemask, 0, 0, 1, 0, 0, 0, 0, addr_class:$addr, 1259 SReg_256:$rsrc, SReg_128:$sampler) 1260>; 1261 1262/* int_SI_sample* for texture lookups consuming more address parameters */ 1263multiclass SamplePatterns<RegisterClass addr_class, ValueType addr_type> { 1264 def : SamplePattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>; 1265 def : SampleRectPattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>; 1266 def : SampleArrayPattern <int_SI_sample, IMAGE_SAMPLE, addr_class, addr_type>; 1267 def : SampleShadowPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_class, addr_type>; 1268 def : SampleShadowArrayPattern <int_SI_sample, IMAGE_SAMPLE_C, addr_class, addr_type>; 1269 1270 def : SamplePattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_class, addr_type>; 1271 def : SampleArrayPattern <int_SI_samplel, IMAGE_SAMPLE_L, addr_class, addr_type>; 1272 def : SampleShadowPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_class, addr_type>; 1273 def : SampleShadowArrayPattern <int_SI_samplel, IMAGE_SAMPLE_C_L, addr_class, addr_type>; 1274 1275 def : SamplePattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_class, addr_type>; 1276 def : SampleArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_B, addr_class, addr_type>; 1277 def : SampleShadowPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_class, addr_type>; 1278 def : SampleShadowArrayPattern <int_SI_sampleb, IMAGE_SAMPLE_C_B, addr_class, addr_type>; 1279} 1280 1281defm : SamplePatterns<VReg_64, v2i32>; 1282defm : SamplePatterns<VReg_128, v4i32>; 1283defm : SamplePatterns<VReg_256, v8i32>; 1284defm : SamplePatterns<VReg_512, v16i32>; 1285 1286/********** ============================================ **********/ 1287/********** Extraction, Insertion, Building and Casting **********/ 1288/********** ============================================ **********/ 1289 1290foreach Index = 0-2 in { 1291 def Extract_Element_v2i32_#Index : Extract_Element < 1292 i32, v2i32, VReg_64, Index, !cast<SubRegIndex>(sub#Index) 1293 >; 1294 def Insert_Element_v2i32_#Index : Insert_Element < 1295 i32, v2i32, VReg_32, VReg_64, Index, !cast<SubRegIndex>(sub#Index) 1296 >; 1297 1298 def Extract_Element_v2f32_#Index : Extract_Element < 1299 f32, v2f32, VReg_64, Index, !cast<SubRegIndex>(sub#Index) 1300 >; 1301 def Insert_Element_v2f32_#Index : Insert_Element < 1302 f32, v2f32, VReg_32, VReg_64, Index, !cast<SubRegIndex>(sub#Index) 1303 >; 1304} 1305 1306foreach Index = 0-3 in { 1307 def Extract_Element_v4i32_#Index : Extract_Element < 1308 i32, v4i32, VReg_128, Index, !cast<SubRegIndex>(sub#Index) 1309 >; 1310 def Insert_Element_v4i32_#Index : Insert_Element < 1311 i32, v4i32, VReg_32, VReg_128, Index, !cast<SubRegIndex>(sub#Index) 1312 >; 1313 1314 def Extract_Element_v4f32_#Index : Extract_Element < 1315 f32, v4f32, VReg_128, Index, !cast<SubRegIndex>(sub#Index) 1316 >; 1317 def Insert_Element_v4f32_#Index : Insert_Element < 1318 f32, v4f32, VReg_32, VReg_128, Index, !cast<SubRegIndex>(sub#Index) 1319 >; 1320} 1321 1322foreach Index = 0-7 in { 1323 def Extract_Element_v8i32_#Index : Extract_Element < 1324 i32, v8i32, VReg_256, Index, !cast<SubRegIndex>(sub#Index) 1325 >; 1326 def Insert_Element_v8i32_#Index : Insert_Element < 1327 i32, v8i32, VReg_32, VReg_256, Index, !cast<SubRegIndex>(sub#Index) 1328 >; 1329 1330 def Extract_Element_v8f32_#Index : Extract_Element < 1331 f32, v8f32, VReg_256, Index, !cast<SubRegIndex>(sub#Index) 1332 >; 1333 def Insert_Element_v8f32_#Index : Insert_Element < 1334 f32, v8f32, VReg_32, VReg_256, Index, !cast<SubRegIndex>(sub#Index) 1335 >; 1336} 1337 1338foreach Index = 0-15 in { 1339 def Extract_Element_v16i32_#Index : Extract_Element < 1340 i32, v16i32, VReg_512, Index, !cast<SubRegIndex>(sub#Index) 1341 >; 1342 def Insert_Element_v16i32_#Index : Insert_Element < 1343 i32, v16i32, VReg_32, VReg_512, Index, !cast<SubRegIndex>(sub#Index) 1344 >; 1345 1346 def Extract_Element_v16f32_#Index : Extract_Element < 1347 f32, v16f32, VReg_512, Index, !cast<SubRegIndex>(sub#Index) 1348 >; 1349 def Insert_Element_v16f32_#Index : Insert_Element < 1350 f32, v16f32, VReg_32, VReg_512, Index, !cast<SubRegIndex>(sub#Index) 1351 >; 1352} 1353 1354def : Vector1_Build <v1i32, VReg_32, i32, VReg_32>; 1355def : Vector2_Build <v2i32, VReg_64, i32, VReg_32>; 1356def : Vector2_Build <v2f32, VReg_64, f32, VReg_32>; 1357def : Vector4_Build <v4i32, VReg_128, i32, VReg_32>; 1358def : Vector4_Build <v4f32, VReg_128, f32, VReg_32>; 1359def : Vector8_Build <v8i32, VReg_256, i32, VReg_32>; 1360def : Vector8_Build <v8f32, VReg_256, f32, VReg_32>; 1361def : Vector16_Build <v16i32, VReg_512, i32, VReg_32>; 1362def : Vector16_Build <v16f32, VReg_512, f32, VReg_32>; 1363 1364def : BitConvert <i32, f32, SReg_32>; 1365def : BitConvert <i32, f32, VReg_32>; 1366 1367def : BitConvert <f32, i32, SReg_32>; 1368def : BitConvert <f32, i32, VReg_32>; 1369 1370/********** =================== **********/ 1371/********** Src & Dst modifiers **********/ 1372/********** =================== **********/ 1373 1374def : Pat < 1375 (int_AMDIL_clamp VReg_32:$src, (f32 FP_ZERO), (f32 FP_ONE)), 1376 (V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */), 1377 0 /* ABS */, 1 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1378>; 1379 1380def : Pat < 1381 (fabs VReg_32:$src), 1382 (V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */), 1383 1 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 0 /* NEG */) 1384>; 1385 1386def : Pat < 1387 (fneg VReg_32:$src), 1388 (V_ADD_F32_e64 VReg_32:$src, (i32 0 /* SRC1 */), 1389 0 /* ABS */, 0 /* CLAMP */, 0 /* OMOD */, 1 /* NEG */) 1390>; 1391 1392/********** ================== **********/ 1393/********** Immediate Patterns **********/ 1394/********** ================== **********/ 1395 1396def : Pat < 1397 (i32 imm:$imm), 1398 (V_MOV_B32_e32 imm:$imm) 1399>; 1400 1401def : Pat < 1402 (f32 fpimm:$imm), 1403 (V_MOV_B32_e32 fpimm:$imm) 1404>; 1405 1406def : Pat < 1407 (i1 imm:$imm), 1408 (S_MOV_B64 imm:$imm) 1409>; 1410 1411def : Pat < 1412 (i64 InlineImm<i64>:$imm), 1413 (S_MOV_B64 InlineImm<i64>:$imm) 1414>; 1415 1416// i64 immediates aren't supported in hardware, split it into two 32bit values 1417def : Pat < 1418 (i64 imm:$imm), 1419 (INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)), 1420 (S_MOV_B32 (i32 (LO32 imm:$imm))), sub0), 1421 (S_MOV_B32 (i32 (HI32 imm:$imm))), sub1) 1422>; 1423 1424/********** ===================== **********/ 1425/********** Interpolation Paterns **********/ 1426/********** ===================== **********/ 1427 1428def : Pat < 1429 (int_SI_fs_constant imm:$attr_chan, imm:$attr, M0Reg:$params), 1430 (V_INTERP_MOV_F32 INTERP.P0, imm:$attr_chan, imm:$attr, M0Reg:$params) 1431>; 1432 1433def : Pat < 1434 (int_SI_fs_interp imm:$attr_chan, imm:$attr, M0Reg:$params, VReg_64:$ij), 1435 (V_INTERP_P2_F32 (V_INTERP_P1_F32 (EXTRACT_SUBREG VReg_64:$ij, sub0), 1436 imm:$attr_chan, imm:$attr, M0Reg:$params), 1437 (EXTRACT_SUBREG VReg_64:$ij, sub1), 1438 imm:$attr_chan, imm:$attr, M0Reg:$params) 1439>; 1440 1441/********** ================== **********/ 1442/********** Intrinsic Patterns **********/ 1443/********** ================== **********/ 1444 1445/* llvm.AMDGPU.pow */ 1446def : POW_Common <V_LOG_F32_e32, V_EXP_F32_e32, V_MUL_LEGACY_F32_e32, VReg_32>; 1447 1448def : Pat < 1449 (int_AMDGPU_div VSrc_32:$src0, VSrc_32:$src1), 1450 (V_MUL_LEGACY_F32_e32 VSrc_32:$src0, (V_RCP_LEGACY_F32_e32 VSrc_32:$src1)) 1451>; 1452 1453def : Pat< 1454 (fdiv VSrc_32:$src0, VSrc_32:$src1), 1455 (V_MUL_F32_e32 VSrc_32:$src0, (V_RCP_F32_e32 VSrc_32:$src1)) 1456>; 1457 1458def : Pat < 1459 (fcos VSrc_32:$src0), 1460 (V_COS_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1461>; 1462 1463def : Pat < 1464 (fsin VSrc_32:$src0), 1465 (V_SIN_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_B32_e32 CONST.TWO_PI_INV))) 1466>; 1467 1468def : Pat < 1469 (int_AMDGPU_cube VReg_128:$src), 1470 (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), 1471 (V_CUBETC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), 1472 (EXTRACT_SUBREG VReg_128:$src, sub1), 1473 (EXTRACT_SUBREG VReg_128:$src, sub2), 1474 0, 0, 0, 0), sub0), 1475 (V_CUBESC_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), 1476 (EXTRACT_SUBREG VReg_128:$src, sub1), 1477 (EXTRACT_SUBREG VReg_128:$src, sub2), 1478 0, 0, 0, 0), sub1), 1479 (V_CUBEMA_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), 1480 (EXTRACT_SUBREG VReg_128:$src, sub1), 1481 (EXTRACT_SUBREG VReg_128:$src, sub2), 1482 0, 0, 0, 0), sub2), 1483 (V_CUBEID_F32 (EXTRACT_SUBREG VReg_128:$src, sub0), 1484 (EXTRACT_SUBREG VReg_128:$src, sub1), 1485 (EXTRACT_SUBREG VReg_128:$src, sub2), 1486 0, 0, 0, 0), sub3) 1487>; 1488 1489def : Pat < 1490 (i32 (sext (i1 SReg_64:$src0))), 1491 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), SReg_64:$src0) 1492>; 1493 1494// 1. Offset as 8bit DWORD immediate 1495def : Pat < 1496 (int_SI_load_const SReg_128:$sbase, IMM8bitDWORD:$offset), 1497 (S_BUFFER_LOAD_DWORD_IMM SReg_128:$sbase, IMM8bitDWORD:$offset) 1498>; 1499 1500// 2. Offset loaded in an 32bit SGPR 1501def : Pat < 1502 (int_SI_load_const SReg_128:$sbase, imm:$offset), 1503 (S_BUFFER_LOAD_DWORD_SGPR SReg_128:$sbase, (S_MOV_B32 imm:$offset)) 1504>; 1505 1506// 3. Offset in an 32Bit VGPR 1507def : Pat < 1508 (int_SI_load_const SReg_128:$sbase, VReg_32:$voff), 1509 (BUFFER_LOAD_DWORD 0, 1, 0, 0, 0, 0, VReg_32:$voff, SReg_128:$sbase, 0, 0, 0) 1510>; 1511 1512/********** ================== **********/ 1513/********** VOP3 Patterns **********/ 1514/********** ================== **********/ 1515 1516def : Pat <(f32 (fadd (fmul VSrc_32:$src0, VSrc_32:$src1), VSrc_32:$src2)), 1517 (V_MAD_F32 VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2, 1518 0, 0, 0, 0)>; 1519 1520/********** ================== **********/ 1521/********** SMRD Patterns **********/ 1522/********** ================== **********/ 1523 1524multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> { 1525 // 1. Offset as 8bit DWORD immediate 1526 def : Pat < 1527 (constant_load (SIadd64bit32bit SReg_64:$sbase, IMM8bitDWORD:$offset)), 1528 (vt (Instr_IMM SReg_64:$sbase, IMM8bitDWORD:$offset)) 1529 >; 1530 1531 // 2. Offset loaded in an 32bit SGPR 1532 def : Pat < 1533 (constant_load (SIadd64bit32bit SReg_64:$sbase, imm:$offset)), 1534 (vt (Instr_SGPR SReg_64:$sbase, (S_MOV_B32 imm:$offset))) 1535 >; 1536 1537 // 3. No offset at all 1538 def : Pat < 1539 (constant_load SReg_64:$sbase), 1540 (vt (Instr_IMM SReg_64:$sbase, 0)) 1541 >; 1542} 1543 1544defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>; 1545defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>; 1546defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v16i8>; 1547defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>; 1548 1549/********** ====================== **********/ 1550/********** Indirect adressing **********/ 1551/********** ====================== **********/ 1552 1553multiclass SI_INDIRECT_Pattern <RegisterClass rc, ValueType vt, 1554 SI_INDIRECT_DST IndDst> { 1555 // 1. Extract with offset 1556 def : Pat< 1557 (vector_extract (vt rc:$vec), 1558 (i64 (zext (i32 (add VReg_32:$idx, imm:$off)))) 1559 ), 1560 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, imm:$off)) 1561 >; 1562 1563 // 2. Extract without offset 1564 def : Pat< 1565 (vector_extract (vt rc:$vec), 1566 (i64 (zext (i32 VReg_32:$idx))) 1567 ), 1568 (f32 (SI_INDIRECT_SRC (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, 0)) 1569 >; 1570 1571 // 3. Insert with offset 1572 def : Pat< 1573 (vector_insert (vt rc:$vec), (f32 VReg_32:$val), 1574 (i64 (zext (i32 (add VReg_32:$idx, imm:$off)))) 1575 ), 1576 (vt (IndDst (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, imm:$off, VReg_32:$val)) 1577 >; 1578 1579 // 4. Insert without offset 1580 def : Pat< 1581 (vector_insert (vt rc:$vec), (f32 VReg_32:$val), 1582 (i64 (zext (i32 VReg_32:$idx))) 1583 ), 1584 (vt (IndDst (IMPLICIT_DEF), rc:$vec, VReg_32:$idx, 0, VReg_32:$val)) 1585 >; 1586} 1587 1588defm : SI_INDIRECT_Pattern <VReg_64, v2f32, SI_INDIRECT_DST_V2>; 1589defm : SI_INDIRECT_Pattern <VReg_128, v4f32, SI_INDIRECT_DST_V4>; 1590defm : SI_INDIRECT_Pattern <VReg_256, v8f32, SI_INDIRECT_DST_V8>; 1591defm : SI_INDIRECT_Pattern <VReg_512, v16f32, SI_INDIRECT_DST_V16>; 1592 1593/********** =============== **********/ 1594/********** Conditions **********/ 1595/********** =============== **********/ 1596 1597def : Pat< 1598 (i1 (setcc f32:$src0, f32:$src1, SETO)), 1599 (V_CMP_O_F32_e64 f32:$src0, f32:$src1) 1600>; 1601 1602def : Pat< 1603 (i1 (setcc f32:$src0, f32:$src1, SETUO)), 1604 (V_CMP_U_F32_e64 f32:$src0, f32:$src1) 1605>; 1606 1607} // End isSI predicate 1608