SIInstrInfo.h revision 285830
1//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10/// \file 11/// \brief Interface definition for SIInstrInfo. 12// 13//===----------------------------------------------------------------------===// 14 15 16#ifndef SIINSTRINFO_H 17#define SIINSTRINFO_H 18 19#include "AMDGPUInstrInfo.h" 20#include "SIRegisterInfo.h" 21 22namespace llvm { 23 24class SIInstrInfo : public AMDGPUInstrInfo { 25private: 26 const SIRegisterInfo RI; 27 28 MachineInstrBuilder buildIndirectIndexLoop(MachineBasicBlock &MBB, 29 MachineBasicBlock::iterator I, 30 unsigned OffsetVGPR, 31 unsigned MovRelOp, 32 unsigned Dst, 33 unsigned Src0) const; 34 // If you add or remove instructions from this function, you will 35 36public: 37 explicit SIInstrInfo(AMDGPUTargetMachine &tm); 38 39 const SIRegisterInfo &getRegisterInfo() const; 40 41 virtual void copyPhysReg(MachineBasicBlock &MBB, 42 MachineBasicBlock::iterator MI, DebugLoc DL, 43 unsigned DestReg, unsigned SrcReg, 44 bool KillSrc) const; 45 46 unsigned commuteOpcode(unsigned Opcode) const; 47 48 virtual MachineInstr *commuteInstruction(MachineInstr *MI, 49 bool NewMI=false) const; 50 51 virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;} 52 MachineInstr *buildMovInstr(MachineBasicBlock *MBB, 53 MachineBasicBlock::iterator I, 54 unsigned DstReg, unsigned SrcReg) const; 55 virtual bool isMov(unsigned Opcode) const; 56 57 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 58 int isMIMG(uint16_t Opcode) const; 59 int isSMRD(uint16_t Opcode) const; 60 bool isVOP1(uint16_t Opcode) const; 61 bool isVOP2(uint16_t Opcode) const; 62 bool isVOP3(uint16_t Opcode) const; 63 bool isVOPC(uint16_t Opcode) const; 64 bool isInlineConstant(const MachineOperand &MO) const; 65 bool isLiteralConstant(const MachineOperand &MO) const; 66 67 virtual bool verifyInstruction(const MachineInstr *MI, 68 StringRef &ErrInfo) const; 69 70 bool isSALUInstr(const MachineInstr &MI) const; 71 static unsigned getVALUOp(const MachineInstr &MI); 72 bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const; 73 74 /// \brief Return the correct register class for \p OpNo. For target-specific 75 /// instructions, this will return the register class that has been defined 76 /// in tablegen. For generic instructions, like REG_SEQUENCE it will return 77 /// the register class of its machine operand. 78 /// to infer the correct register class base on the other operands. 79 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI, 80 unsigned OpNo) const;\ 81 82 /// \returns true if it is legal for the operand at index \p OpNo 83 /// to read a VGPR. 84 bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const; 85 86 /// \brief Legalize the \p OpIndex operand of this instruction by inserting 87 /// a MOV. For example: 88 /// ADD_I32_e32 VGPR0, 15 89 /// to 90 /// MOV VGPR1, 15 91 /// ADD_I32_e32 VGPR0, VGPR1 92 /// 93 /// If the operand being legalized is a register, then a COPY will be used 94 /// instead of MOV. 95 void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const; 96 97 /// \brief Legalize all operands in this instruction. This function may 98 /// create new instruction and insert them before \p MI. 99 void legalizeOperands(MachineInstr *MI) const; 100 101 /// \brief Replace this instruction's opcode with the equivalent VALU 102 /// opcode. This function will also move the users of \p MI to the 103 /// VALU if necessary. 104 void moveToVALU(MachineInstr &MI) const; 105 106 virtual unsigned calculateIndirectAddress(unsigned RegIndex, 107 unsigned Channel) const; 108 109 virtual const TargetRegisterClass *getIndirectAddrRegClass() const; 110 111 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 112 MachineBasicBlock::iterator I, 113 unsigned ValueReg, 114 unsigned Address, 115 unsigned OffsetReg) const; 116 117 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 118 MachineBasicBlock::iterator I, 119 unsigned ValueReg, 120 unsigned Address, 121 unsigned OffsetReg) const; 122 void reserveIndirectRegisters(BitVector &Reserved, 123 const MachineFunction &MF) const; 124 125 void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, 126 unsigned SavReg, unsigned IndexReg) const; 127}; 128 129namespace AMDGPU { 130 131 int getVOPe64(uint16_t Opcode); 132 int getCommuteRev(uint16_t Opcode); 133 int getCommuteOrig(uint16_t Opcode); 134 135} // End namespace AMDGPU 136 137} // End namespace llvm 138 139namespace SIInstrFlags { 140 enum Flags { 141 // First 4 bits are the instruction encoding 142 VM_CNT = 1 << 0, 143 EXP_CNT = 1 << 1, 144 LGKM_CNT = 1 << 2 145 }; 146} 147 148#endif //SIINSTRINFO_H 149