SIInstrInfo.h revision 263508
1263508Sdim//===-- SIInstrInfo.h - SI Instruction Info Interface -----------*- C++ -*-===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief Interface definition for SIInstrInfo. 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim 16249259Sdim#ifndef SIINSTRINFO_H 17249259Sdim#define SIINSTRINFO_H 18249259Sdim 19249259Sdim#include "AMDGPUInstrInfo.h" 20249259Sdim#include "SIRegisterInfo.h" 21249259Sdim 22249259Sdimnamespace llvm { 23249259Sdim 24249259Sdimclass SIInstrInfo : public AMDGPUInstrInfo { 25249259Sdimprivate: 26249259Sdim const SIRegisterInfo RI; 27249259Sdim 28263508Sdim MachineInstrBuilder buildIndirectIndexLoop(MachineBasicBlock &MBB, 29263508Sdim MachineBasicBlock::iterator I, 30263508Sdim unsigned OffsetVGPR, 31263508Sdim unsigned MovRelOp, 32263508Sdim unsigned Dst, 33263508Sdim unsigned Src0) const; 34263508Sdim // If you add or remove instructions from this function, you will 35263508Sdim 36249259Sdimpublic: 37249259Sdim explicit SIInstrInfo(AMDGPUTargetMachine &tm); 38249259Sdim 39249259Sdim const SIRegisterInfo &getRegisterInfo() const; 40249259Sdim 41249259Sdim virtual void copyPhysReg(MachineBasicBlock &MBB, 42249259Sdim MachineBasicBlock::iterator MI, DebugLoc DL, 43249259Sdim unsigned DestReg, unsigned SrcReg, 44249259Sdim bool KillSrc) const; 45249259Sdim 46249259Sdim unsigned commuteOpcode(unsigned Opcode) const; 47249259Sdim 48249259Sdim virtual MachineInstr *commuteInstruction(MachineInstr *MI, 49249259Sdim bool NewMI=false) const; 50249259Sdim 51249259Sdim virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;} 52263508Sdim MachineInstr *buildMovInstr(MachineBasicBlock *MBB, 53263508Sdim MachineBasicBlock::iterator I, 54263508Sdim unsigned DstReg, unsigned SrcReg) const; 55249259Sdim virtual bool isMov(unsigned Opcode) const; 56249259Sdim 57249259Sdim virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 58263508Sdim int isMIMG(uint16_t Opcode) const; 59263508Sdim int isSMRD(uint16_t Opcode) const; 60263508Sdim bool isVOP1(uint16_t Opcode) const; 61263508Sdim bool isVOP2(uint16_t Opcode) const; 62263508Sdim bool isVOP3(uint16_t Opcode) const; 63263508Sdim bool isVOPC(uint16_t Opcode) const; 64263508Sdim bool isInlineConstant(const MachineOperand &MO) const; 65263508Sdim bool isLiteralConstant(const MachineOperand &MO) const; 66249259Sdim 67263508Sdim virtual bool verifyInstruction(const MachineInstr *MI, 68263508Sdim StringRef &ErrInfo) const; 69249259Sdim 70263508Sdim bool isSALUInstr(const MachineInstr &MI) const; 71263508Sdim static unsigned getVALUOp(const MachineInstr &MI); 72263508Sdim bool isSALUOpSupportedOnVALU(const MachineInstr &MI) const; 73249259Sdim 74263508Sdim /// \brief Return the correct register class for \p OpNo. For target-specific 75263508Sdim /// instructions, this will return the register class that has been defined 76263508Sdim /// in tablegen. For generic instructions, like REG_SEQUENCE it will return 77263508Sdim /// the register class of its machine operand. 78263508Sdim /// to infer the correct register class base on the other operands. 79263508Sdim const TargetRegisterClass *getOpRegClass(const MachineInstr &MI, 80263508Sdim unsigned OpNo) const;\ 81263508Sdim 82263508Sdim /// \returns true if it is legal for the operand at index \p OpNo 83263508Sdim /// to read a VGPR. 84263508Sdim bool canReadVGPR(const MachineInstr &MI, unsigned OpNo) const; 85263508Sdim 86263508Sdim /// \brief Legalize the \p OpIndex operand of this instruction by inserting 87263508Sdim /// a MOV. For example: 88263508Sdim /// ADD_I32_e32 VGPR0, 15 89263508Sdim /// to 90263508Sdim /// MOV VGPR1, 15 91263508Sdim /// ADD_I32_e32 VGPR0, VGPR1 92263508Sdim /// 93263508Sdim /// If the operand being legalized is a register, then a COPY will be used 94263508Sdim /// instead of MOV. 95263508Sdim void legalizeOpWithMove(MachineInstr *MI, unsigned OpIdx) const; 96263508Sdim 97263508Sdim /// \brief Legalize all operands in this instruction. This function may 98263508Sdim /// create new instruction and insert them before \p MI. 99263508Sdim void legalizeOperands(MachineInstr *MI) const; 100263508Sdim 101263508Sdim /// \brief Replace this instruction's opcode with the equivalent VALU 102263508Sdim /// opcode. This function will also move the users of \p MI to the 103263508Sdim /// VALU if necessary. 104263508Sdim void moveToVALU(MachineInstr &MI) const; 105263508Sdim 106249259Sdim virtual unsigned calculateIndirectAddress(unsigned RegIndex, 107249259Sdim unsigned Channel) const; 108249259Sdim 109263508Sdim virtual const TargetRegisterClass *getIndirectAddrRegClass() const; 110249259Sdim 111249259Sdim virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 112249259Sdim MachineBasicBlock::iterator I, 113249259Sdim unsigned ValueReg, 114249259Sdim unsigned Address, 115249259Sdim unsigned OffsetReg) const; 116249259Sdim 117249259Sdim virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 118249259Sdim MachineBasicBlock::iterator I, 119249259Sdim unsigned ValueReg, 120249259Sdim unsigned Address, 121249259Sdim unsigned OffsetReg) const; 122263508Sdim void reserveIndirectRegisters(BitVector &Reserved, 123263508Sdim const MachineFunction &MF) const; 124249259Sdim 125263508Sdim void LoadM0(MachineInstr *MoveRel, MachineBasicBlock::iterator I, 126263508Sdim unsigned SavReg, unsigned IndexReg) const; 127263508Sdim}; 128249259Sdim 129249259Sdimnamespace AMDGPU { 130249259Sdim 131249259Sdim int getVOPe64(uint16_t Opcode); 132249259Sdim int getCommuteRev(uint16_t Opcode); 133249259Sdim int getCommuteOrig(uint16_t Opcode); 134249259Sdim 135249259Sdim} // End namespace AMDGPU 136249259Sdim 137249259Sdim} // End namespace llvm 138249259Sdim 139249259Sdimnamespace SIInstrFlags { 140249259Sdim enum Flags { 141249259Sdim // First 4 bits are the instruction encoding 142249259Sdim VM_CNT = 1 << 0, 143249259Sdim EXP_CNT = 1 << 1, 144249259Sdim LGKM_CNT = 1 << 2 145249259Sdim }; 146249259Sdim} 147249259Sdim 148249259Sdim#endif //SIINSTRINFO_H 149