SIInstrInfo.h revision 249259
1249259Sdim//===-- SIInstrInfo.h - SI Instruction Info Interface ---------------------===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief Interface definition for SIInstrInfo. 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim 16249259Sdim#ifndef SIINSTRINFO_H 17249259Sdim#define SIINSTRINFO_H 18249259Sdim 19249259Sdim#include "AMDGPUInstrInfo.h" 20249259Sdim#include "SIRegisterInfo.h" 21249259Sdim 22249259Sdimnamespace llvm { 23249259Sdim 24249259Sdimclass SIInstrInfo : public AMDGPUInstrInfo { 25249259Sdimprivate: 26249259Sdim const SIRegisterInfo RI; 27249259Sdim 28249259Sdimpublic: 29249259Sdim explicit SIInstrInfo(AMDGPUTargetMachine &tm); 30249259Sdim 31249259Sdim const SIRegisterInfo &getRegisterInfo() const; 32249259Sdim 33249259Sdim virtual void copyPhysReg(MachineBasicBlock &MBB, 34249259Sdim MachineBasicBlock::iterator MI, DebugLoc DL, 35249259Sdim unsigned DestReg, unsigned SrcReg, 36249259Sdim bool KillSrc) const; 37249259Sdim 38249259Sdim unsigned commuteOpcode(unsigned Opcode) const; 39249259Sdim 40249259Sdim virtual MachineInstr *commuteInstruction(MachineInstr *MI, 41249259Sdim bool NewMI=false) const; 42249259Sdim 43249259Sdim virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg, 44249259Sdim int64_t Imm) const; 45249259Sdim 46249259Sdim virtual unsigned getIEQOpcode() const { assert(!"Implement"); return 0;} 47249259Sdim virtual bool isMov(unsigned Opcode) const; 48249259Sdim 49249259Sdim virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const; 50249259Sdim 51249259Sdim virtual int getIndirectIndexBegin(const MachineFunction &MF) const; 52249259Sdim 53249259Sdim virtual int getIndirectIndexEnd(const MachineFunction &MF) const; 54249259Sdim 55249259Sdim virtual unsigned calculateIndirectAddress(unsigned RegIndex, 56249259Sdim unsigned Channel) const; 57249259Sdim 58249259Sdim virtual const TargetRegisterClass *getIndirectAddrStoreRegClass( 59249259Sdim unsigned SourceReg) const; 60249259Sdim 61249259Sdim virtual const TargetRegisterClass *getIndirectAddrLoadRegClass() const; 62249259Sdim 63249259Sdim virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB, 64249259Sdim MachineBasicBlock::iterator I, 65249259Sdim unsigned ValueReg, 66249259Sdim unsigned Address, 67249259Sdim unsigned OffsetReg) const; 68249259Sdim 69249259Sdim virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB, 70249259Sdim MachineBasicBlock::iterator I, 71249259Sdim unsigned ValueReg, 72249259Sdim unsigned Address, 73249259Sdim unsigned OffsetReg) const; 74249259Sdim 75249259Sdim virtual const TargetRegisterClass *getSuperIndirectRegClass() const; 76249259Sdim }; 77249259Sdim 78249259Sdimnamespace AMDGPU { 79249259Sdim 80249259Sdim int getVOPe64(uint16_t Opcode); 81249259Sdim int getCommuteRev(uint16_t Opcode); 82249259Sdim int getCommuteOrig(uint16_t Opcode); 83249259Sdim 84249259Sdim} // End namespace AMDGPU 85249259Sdim 86249259Sdim} // End namespace llvm 87249259Sdim 88249259Sdimnamespace SIInstrFlags { 89249259Sdim enum Flags { 90249259Sdim // First 4 bits are the instruction encoding 91249259Sdim VM_CNT = 1 << 0, 92249259Sdim EXP_CNT = 1 << 1, 93249259Sdim LGKM_CNT = 1 << 2 94249259Sdim }; 95249259Sdim} 96249259Sdim 97249259Sdim#endif //SIINSTRINFO_H 98