1249259Sdim//===-- SIInstrFormats.td - SI Instruction Encodings ----------------------===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim// SI Instruction format definitions. 11249259Sdim// 12249259Sdim//===----------------------------------------------------------------------===// 13249259Sdim 14249259Sdimclass InstSI <dag outs, dag ins, string asm, list<dag> pattern> : 15249259Sdim AMDGPUInst<outs, ins, asm, pattern> { 16249259Sdim 17249259Sdim field bits<1> VM_CNT = 0; 18249259Sdim field bits<1> EXP_CNT = 0; 19249259Sdim field bits<1> LGKM_CNT = 0; 20263508Sdim field bits<1> MIMG = 0; 21263508Sdim field bits<1> SMRD = 0; 22263508Sdim field bits<1> VOP1 = 0; 23263508Sdim field bits<1> VOP2 = 0; 24263508Sdim field bits<1> VOP3 = 0; 25263508Sdim field bits<1> VOPC = 0; 26263508Sdim field bits<1> SALU = 0; 27249259Sdim 28249259Sdim let TSFlags{0} = VM_CNT; 29249259Sdim let TSFlags{1} = EXP_CNT; 30249259Sdim let TSFlags{2} = LGKM_CNT; 31263508Sdim let TSFlags{3} = MIMG; 32263508Sdim let TSFlags{4} = SMRD; 33263508Sdim let TSFlags{5} = VOP1; 34263508Sdim let TSFlags{6} = VOP2; 35263508Sdim let TSFlags{7} = VOP3; 36263508Sdim let TSFlags{8} = VOPC; 37263508Sdim let TSFlags{9} = SALU; 38249259Sdim} 39249259Sdim 40249259Sdimclass Enc32 <dag outs, dag ins, string asm, list<dag> pattern> : 41249259Sdim InstSI <outs, ins, asm, pattern> { 42249259Sdim 43249259Sdim field bits<32> Inst; 44249259Sdim let Size = 4; 45249259Sdim} 46249259Sdim 47249259Sdimclass Enc64 <dag outs, dag ins, string asm, list<dag> pattern> : 48249259Sdim InstSI <outs, ins, asm, pattern> { 49249259Sdim 50249259Sdim field bits<64> Inst; 51249259Sdim let Size = 8; 52249259Sdim} 53249259Sdim 54249259Sdim//===----------------------------------------------------------------------===// 55249259Sdim// Scalar operations 56249259Sdim//===----------------------------------------------------------------------===// 57249259Sdim 58249259Sdimclass SOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 59249259Sdim Enc32<outs, ins, asm, pattern> { 60249259Sdim 61249259Sdim bits<7> SDST; 62249259Sdim bits<8> SSRC0; 63249259Sdim 64249259Sdim let Inst{7-0} = SSRC0; 65249259Sdim let Inst{15-8} = op; 66249259Sdim let Inst{22-16} = SDST; 67249259Sdim let Inst{31-23} = 0x17d; //encoding; 68249259Sdim 69249259Sdim let mayLoad = 0; 70249259Sdim let mayStore = 0; 71249259Sdim let hasSideEffects = 0; 72263508Sdim let SALU = 1; 73249259Sdim} 74249259Sdim 75249259Sdimclass SOP2 <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 76249259Sdim Enc32 <outs, ins, asm, pattern> { 77249259Sdim 78249259Sdim bits<7> SDST; 79249259Sdim bits<8> SSRC0; 80249259Sdim bits<8> SSRC1; 81249259Sdim 82249259Sdim let Inst{7-0} = SSRC0; 83249259Sdim let Inst{15-8} = SSRC1; 84249259Sdim let Inst{22-16} = SDST; 85249259Sdim let Inst{29-23} = op; 86249259Sdim let Inst{31-30} = 0x2; // encoding 87249259Sdim 88249259Sdim let mayLoad = 0; 89249259Sdim let mayStore = 0; 90249259Sdim let hasSideEffects = 0; 91263508Sdim let SALU = 1; 92249259Sdim} 93249259Sdim 94249259Sdimclass SOPC <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 95249259Sdim Enc32<outs, ins, asm, pattern> { 96249259Sdim 97249259Sdim bits<8> SSRC0; 98249259Sdim bits<8> SSRC1; 99249259Sdim 100249259Sdim let Inst{7-0} = SSRC0; 101249259Sdim let Inst{15-8} = SSRC1; 102249259Sdim let Inst{22-16} = op; 103249259Sdim let Inst{31-23} = 0x17e; 104249259Sdim 105249259Sdim let DisableEncoding = "$dst"; 106249259Sdim let mayLoad = 0; 107249259Sdim let mayStore = 0; 108249259Sdim let hasSideEffects = 0; 109263508Sdim let SALU = 1; 110249259Sdim} 111249259Sdim 112249259Sdimclass SOPK <bits<5> op, dag outs, dag ins, string asm, list<dag> pattern> : 113249259Sdim Enc32 <outs, ins , asm, pattern> { 114249259Sdim 115249259Sdim bits <7> SDST; 116249259Sdim bits <16> SIMM16; 117249259Sdim 118249259Sdim let Inst{15-0} = SIMM16; 119249259Sdim let Inst{22-16} = SDST; 120249259Sdim let Inst{27-23} = op; 121249259Sdim let Inst{31-28} = 0xb; //encoding 122249259Sdim 123249259Sdim let mayLoad = 0; 124249259Sdim let mayStore = 0; 125249259Sdim let hasSideEffects = 0; 126263508Sdim let SALU = 1; 127249259Sdim} 128249259Sdim 129249259Sdimclass SOPP <bits<7> op, dag ins, string asm, list<dag> pattern> : Enc32 < 130249259Sdim (outs), 131249259Sdim ins, 132249259Sdim asm, 133249259Sdim pattern > { 134249259Sdim 135249259Sdim bits <16> SIMM16; 136249259Sdim 137249259Sdim let Inst{15-0} = SIMM16; 138249259Sdim let Inst{22-16} = op; 139249259Sdim let Inst{31-23} = 0x17f; // encoding 140249259Sdim 141249259Sdim let mayLoad = 0; 142249259Sdim let mayStore = 0; 143249259Sdim let hasSideEffects = 0; 144263508Sdim let SALU = 1; 145249259Sdim} 146249259Sdim 147249259Sdimclass SMRD <bits<5> op, bits<1> imm, dag outs, dag ins, string asm, 148249259Sdim list<dag> pattern> : Enc32<outs, ins, asm, pattern> { 149249259Sdim 150249259Sdim bits<7> SDST; 151249259Sdim bits<7> SBASE; 152249259Sdim bits<8> OFFSET; 153249259Sdim 154249259Sdim let Inst{7-0} = OFFSET; 155249259Sdim let Inst{8} = imm; 156249259Sdim let Inst{14-9} = SBASE{6-1}; 157249259Sdim let Inst{21-15} = SDST; 158249259Sdim let Inst{26-22} = op; 159249259Sdim let Inst{31-27} = 0x18; //encoding 160249259Sdim 161249259Sdim let LGKM_CNT = 1; 162263508Sdim let SMRD = 1; 163249259Sdim} 164249259Sdim 165249259Sdim//===----------------------------------------------------------------------===// 166249259Sdim// Vector ALU operations 167249259Sdim//===----------------------------------------------------------------------===// 168249259Sdim 169249259Sdimlet Uses = [EXEC] in { 170249259Sdim 171249259Sdimclass VOP1 <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 172249259Sdim Enc32 <outs, ins, asm, pattern> { 173249259Sdim 174249259Sdim bits<8> VDST; 175249259Sdim bits<9> SRC0; 176249259Sdim 177249259Sdim let Inst{8-0} = SRC0; 178249259Sdim let Inst{16-9} = op; 179249259Sdim let Inst{24-17} = VDST; 180249259Sdim let Inst{31-25} = 0x3f; //encoding 181249259Sdim 182249259Sdim let mayLoad = 0; 183249259Sdim let mayStore = 0; 184249259Sdim let hasSideEffects = 0; 185263508Sdim let UseNamedOperandTable = 1; 186263508Sdim let VOP1 = 1; 187249259Sdim} 188249259Sdim 189249259Sdimclass VOP2 <bits<6> op, dag outs, dag ins, string asm, list<dag> pattern> : 190249259Sdim Enc32 <outs, ins, asm, pattern> { 191249259Sdim 192249259Sdim bits<8> VDST; 193249259Sdim bits<9> SRC0; 194249259Sdim bits<8> VSRC1; 195249259Sdim 196249259Sdim let Inst{8-0} = SRC0; 197249259Sdim let Inst{16-9} = VSRC1; 198249259Sdim let Inst{24-17} = VDST; 199249259Sdim let Inst{30-25} = op; 200249259Sdim let Inst{31} = 0x0; //encoding 201249259Sdim 202249259Sdim let mayLoad = 0; 203249259Sdim let mayStore = 0; 204249259Sdim let hasSideEffects = 0; 205263508Sdim let UseNamedOperandTable = 1; 206263508Sdim let VOP2 = 1; 207249259Sdim} 208249259Sdim 209249259Sdimclass VOP3 <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : 210249259Sdim Enc64 <outs, ins, asm, pattern> { 211249259Sdim 212263508Sdim bits<8> dst; 213263508Sdim bits<9> src0; 214263508Sdim bits<9> src1; 215263508Sdim bits<9> src2; 216263508Sdim bits<3> abs; 217263508Sdim bits<1> clamp; 218263508Sdim bits<2> omod; 219263508Sdim bits<3> neg; 220249259Sdim 221263508Sdim let Inst{7-0} = dst; 222263508Sdim let Inst{10-8} = abs; 223263508Sdim let Inst{11} = clamp; 224249259Sdim let Inst{25-17} = op; 225249259Sdim let Inst{31-26} = 0x34; //encoding 226263508Sdim let Inst{40-32} = src0; 227263508Sdim let Inst{49-41} = src1; 228263508Sdim let Inst{58-50} = src2; 229263508Sdim let Inst{60-59} = omod; 230263508Sdim let Inst{63-61} = neg; 231249259Sdim 232249259Sdim let mayLoad = 0; 233249259Sdim let mayStore = 0; 234249259Sdim let hasSideEffects = 0; 235263508Sdim let UseNamedOperandTable = 1; 236263508Sdim let VOP3 = 1; 237249259Sdim} 238249259Sdim 239249259Sdimclass VOP3b <bits<9> op, dag outs, dag ins, string asm, list<dag> pattern> : 240249259Sdim Enc64 <outs, ins, asm, pattern> { 241249259Sdim 242263508Sdim bits<8> dst; 243263508Sdim bits<9> src0; 244263508Sdim bits<9> src1; 245263508Sdim bits<9> src2; 246263508Sdim bits<7> sdst; 247263508Sdim bits<2> omod; 248263508Sdim bits<3> neg; 249249259Sdim 250263508Sdim let Inst{7-0} = dst; 251263508Sdim let Inst{14-8} = sdst; 252249259Sdim let Inst{25-17} = op; 253249259Sdim let Inst{31-26} = 0x34; //encoding 254263508Sdim let Inst{40-32} = src0; 255263508Sdim let Inst{49-41} = src1; 256263508Sdim let Inst{58-50} = src2; 257263508Sdim let Inst{60-59} = omod; 258263508Sdim let Inst{63-61} = neg; 259249259Sdim 260249259Sdim let mayLoad = 0; 261249259Sdim let mayStore = 0; 262249259Sdim let hasSideEffects = 0; 263263508Sdim let UseNamedOperandTable = 1; 264263508Sdim let VOP3 = 1; 265249259Sdim} 266249259Sdim 267249259Sdimclass VOPC <bits<8> op, dag ins, string asm, list<dag> pattern> : 268249259Sdim Enc32 <(outs VCCReg:$dst), ins, asm, pattern> { 269249259Sdim 270249259Sdim bits<9> SRC0; 271249259Sdim bits<8> VSRC1; 272249259Sdim 273249259Sdim let Inst{8-0} = SRC0; 274249259Sdim let Inst{16-9} = VSRC1; 275249259Sdim let Inst{24-17} = op; 276249259Sdim let Inst{31-25} = 0x3e; 277249259Sdim 278249259Sdim let DisableEncoding = "$dst"; 279249259Sdim let mayLoad = 0; 280249259Sdim let mayStore = 0; 281249259Sdim let hasSideEffects = 0; 282263508Sdim let VOPC = 1; 283249259Sdim} 284249259Sdim 285249259Sdimclass VINTRP <bits <2> op, dag outs, dag ins, string asm, list<dag> pattern> : 286249259Sdim Enc32 <outs, ins, asm, pattern> { 287249259Sdim 288249259Sdim bits<8> VDST; 289249259Sdim bits<8> VSRC; 290249259Sdim bits<2> ATTRCHAN; 291249259Sdim bits<6> ATTR; 292249259Sdim 293249259Sdim let Inst{7-0} = VSRC; 294249259Sdim let Inst{9-8} = ATTRCHAN; 295249259Sdim let Inst{15-10} = ATTR; 296249259Sdim let Inst{17-16} = op; 297249259Sdim let Inst{25-18} = VDST; 298249259Sdim let Inst{31-26} = 0x32; // encoding 299249259Sdim 300249259Sdim let neverHasSideEffects = 1; 301249259Sdim let mayLoad = 1; 302249259Sdim let mayStore = 0; 303249259Sdim} 304249259Sdim 305249259Sdim} // End Uses = [EXEC] 306249259Sdim 307249259Sdim//===----------------------------------------------------------------------===// 308249259Sdim// Vector I/O operations 309249259Sdim//===----------------------------------------------------------------------===// 310249259Sdim 311249259Sdimlet Uses = [EXEC] in { 312249259Sdim 313263508Sdimclass DS <bits<8> op, dag outs, dag ins, string asm, list<dag> pattern> : 314263508Sdim Enc64 <outs, ins, asm, pattern> { 315263508Sdim 316263508Sdim bits<8> vdst; 317263508Sdim bits<1> gds; 318263508Sdim bits<8> addr; 319263508Sdim bits<8> data0; 320263508Sdim bits<8> data1; 321263508Sdim bits<8> offset0; 322263508Sdim bits<8> offset1; 323263508Sdim 324263508Sdim let Inst{7-0} = offset0; 325263508Sdim let Inst{15-8} = offset1; 326263508Sdim let Inst{17} = gds; 327263508Sdim let Inst{25-18} = op; 328263508Sdim let Inst{31-26} = 0x36; //encoding 329263508Sdim let Inst{39-32} = addr; 330263508Sdim let Inst{47-40} = data0; 331263508Sdim let Inst{55-48} = data1; 332263508Sdim let Inst{63-56} = vdst; 333263508Sdim 334263508Sdim let LGKM_CNT = 1; 335263508Sdim} 336263508Sdim 337249259Sdimclass MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 338249259Sdim Enc64<outs, ins, asm, pattern> { 339249259Sdim 340251662Sdim bits<12> offset; 341251662Sdim bits<1> offen; 342251662Sdim bits<1> idxen; 343251662Sdim bits<1> glc; 344251662Sdim bits<1> addr64; 345251662Sdim bits<1> lds; 346251662Sdim bits<8> vaddr; 347251662Sdim bits<8> vdata; 348251662Sdim bits<7> srsrc; 349251662Sdim bits<1> slc; 350251662Sdim bits<1> tfe; 351251662Sdim bits<8> soffset; 352249259Sdim 353251662Sdim let Inst{11-0} = offset; 354251662Sdim let Inst{12} = offen; 355251662Sdim let Inst{13} = idxen; 356251662Sdim let Inst{14} = glc; 357251662Sdim let Inst{15} = addr64; 358251662Sdim let Inst{16} = lds; 359249259Sdim let Inst{24-18} = op; 360249259Sdim let Inst{31-26} = 0x38; //encoding 361251662Sdim let Inst{39-32} = vaddr; 362251662Sdim let Inst{47-40} = vdata; 363251662Sdim let Inst{52-48} = srsrc{6-2}; 364251662Sdim let Inst{54} = slc; 365251662Sdim let Inst{55} = tfe; 366251662Sdim let Inst{63-56} = soffset; 367249259Sdim 368249259Sdim let VM_CNT = 1; 369249259Sdim let EXP_CNT = 1; 370249259Sdim 371249259Sdim let neverHasSideEffects = 1; 372249259Sdim} 373249259Sdim 374249259Sdimclass MTBUF <bits<3> op, dag outs, dag ins, string asm, list<dag> pattern> : 375249259Sdim Enc64<outs, ins, asm, pattern> { 376249259Sdim 377249259Sdim bits<8> VDATA; 378249259Sdim bits<12> OFFSET; 379249259Sdim bits<1> OFFEN; 380249259Sdim bits<1> IDXEN; 381249259Sdim bits<1> GLC; 382249259Sdim bits<1> ADDR64; 383249259Sdim bits<4> DFMT; 384249259Sdim bits<3> NFMT; 385249259Sdim bits<8> VADDR; 386249259Sdim bits<7> SRSRC; 387249259Sdim bits<1> SLC; 388249259Sdim bits<1> TFE; 389249259Sdim bits<8> SOFFSET; 390249259Sdim 391249259Sdim let Inst{11-0} = OFFSET; 392249259Sdim let Inst{12} = OFFEN; 393249259Sdim let Inst{13} = IDXEN; 394249259Sdim let Inst{14} = GLC; 395249259Sdim let Inst{15} = ADDR64; 396249259Sdim let Inst{18-16} = op; 397249259Sdim let Inst{22-19} = DFMT; 398249259Sdim let Inst{25-23} = NFMT; 399249259Sdim let Inst{31-26} = 0x3a; //encoding 400249259Sdim let Inst{39-32} = VADDR; 401249259Sdim let Inst{47-40} = VDATA; 402249259Sdim let Inst{52-48} = SRSRC{6-2}; 403249259Sdim let Inst{54} = SLC; 404249259Sdim let Inst{55} = TFE; 405249259Sdim let Inst{63-56} = SOFFSET; 406249259Sdim 407249259Sdim let VM_CNT = 1; 408249259Sdim let EXP_CNT = 1; 409249259Sdim 410249259Sdim let neverHasSideEffects = 1; 411249259Sdim} 412249259Sdim 413249259Sdimclass MIMG <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> : 414249259Sdim Enc64 <outs, ins, asm, pattern> { 415249259Sdim 416249259Sdim bits<8> VDATA; 417249259Sdim bits<4> DMASK; 418249259Sdim bits<1> UNORM; 419249259Sdim bits<1> GLC; 420249259Sdim bits<1> DA; 421249259Sdim bits<1> R128; 422249259Sdim bits<1> TFE; 423249259Sdim bits<1> LWE; 424249259Sdim bits<1> SLC; 425249259Sdim bits<8> VADDR; 426249259Sdim bits<7> SRSRC; 427249259Sdim bits<7> SSAMP; 428249259Sdim 429249259Sdim let Inst{11-8} = DMASK; 430249259Sdim let Inst{12} = UNORM; 431249259Sdim let Inst{13} = GLC; 432249259Sdim let Inst{14} = DA; 433249259Sdim let Inst{15} = R128; 434249259Sdim let Inst{16} = TFE; 435249259Sdim let Inst{17} = LWE; 436249259Sdim let Inst{24-18} = op; 437249259Sdim let Inst{25} = SLC; 438249259Sdim let Inst{31-26} = 0x3c; 439249259Sdim let Inst{39-32} = VADDR; 440249259Sdim let Inst{47-40} = VDATA; 441249259Sdim let Inst{52-48} = SRSRC{6-2}; 442249259Sdim let Inst{57-53} = SSAMP{6-2}; 443249259Sdim 444249259Sdim let VM_CNT = 1; 445249259Sdim let EXP_CNT = 1; 446263508Sdim let MIMG = 1; 447249259Sdim} 448249259Sdim 449249259Sdimdef EXP : Enc64< 450249259Sdim (outs), 451249259Sdim (ins i32imm:$en, i32imm:$tgt, i32imm:$compr, i32imm:$done, i32imm:$vm, 452249259Sdim VReg_32:$src0, VReg_32:$src1, VReg_32:$src2, VReg_32:$src3), 453249259Sdim "EXP $en, $tgt, $compr, $done, $vm, $src0, $src1, $src2, $src3", 454249259Sdim [] > { 455249259Sdim 456249259Sdim bits<4> EN; 457249259Sdim bits<6> TGT; 458249259Sdim bits<1> COMPR; 459249259Sdim bits<1> DONE; 460249259Sdim bits<1> VM; 461249259Sdim bits<8> VSRC0; 462249259Sdim bits<8> VSRC1; 463249259Sdim bits<8> VSRC2; 464249259Sdim bits<8> VSRC3; 465249259Sdim 466249259Sdim let Inst{3-0} = EN; 467249259Sdim let Inst{9-4} = TGT; 468249259Sdim let Inst{10} = COMPR; 469249259Sdim let Inst{11} = DONE; 470249259Sdim let Inst{12} = VM; 471249259Sdim let Inst{31-26} = 0x3e; 472249259Sdim let Inst{39-32} = VSRC0; 473249259Sdim let Inst{47-40} = VSRC1; 474249259Sdim let Inst{55-48} = VSRC2; 475249259Sdim let Inst{63-56} = VSRC3; 476249259Sdim 477249259Sdim let EXP_CNT = 1; 478249259Sdim} 479249259Sdim 480249259Sdim} // End Uses = [EXEC] 481