R600RegisterInfo.h revision 263508
1249259Sdim//===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief Interface definition for R600RegisterInfo 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim#ifndef R600REGISTERINFO_H_ 16249259Sdim#define R600REGISTERINFO_H_ 17249259Sdim 18249259Sdim#include "AMDGPURegisterInfo.h" 19249259Sdim#include "AMDGPUTargetMachine.h" 20249259Sdim 21249259Sdimnamespace llvm { 22249259Sdim 23249259Sdimclass R600TargetMachine; 24249259Sdim 25249259Sdimstruct R600RegisterInfo : public AMDGPURegisterInfo { 26249259Sdim AMDGPUTargetMachine &TM; 27263508Sdim RegClassWeight RCW; 28249259Sdim 29263508Sdim R600RegisterInfo(AMDGPUTargetMachine &tm); 30249259Sdim 31249259Sdim virtual BitVector getReservedRegs(const MachineFunction &MF) const; 32249259Sdim 33249259Sdim /// \param RC is an AMDIL reg class. 34249259Sdim /// 35249259Sdim /// \returns the R600 reg class that is equivalent to \p RC. 36249259Sdim virtual const TargetRegisterClass *getISARegClass( 37249259Sdim const TargetRegisterClass *RC) const; 38249259Sdim 39249259Sdim /// \brief get the HW encoding for a register's channel. 40249259Sdim unsigned getHWRegChan(unsigned reg) const; 41249259Sdim 42263508Sdim virtual unsigned getHWRegIndex(unsigned Reg) const; 43263508Sdim 44249259Sdim /// \brief get the register class of the specified type to use in the 45249259Sdim /// CFGStructurizer 46249259Sdim virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const; 47249259Sdim 48263508Sdim virtual const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const; 49249259Sdim 50263508Sdim // \returns true if \p Reg can be defined in one ALU caluse and used in another. 51263508Sdim virtual bool isPhysRegLiveAcrossClauses(unsigned Reg) const; 52249259Sdim}; 53249259Sdim 54249259Sdim} // End namespace llvm 55249259Sdim 56249259Sdim#endif // AMDIDSAREGISTERINFO_H_ 57