R600RegisterInfo.cpp revision 249259
1249259Sdim//===-- R600RegisterInfo.cpp - R600 Register Information ------------------===// 2249259Sdim// 3249259Sdim// The LLVM Compiler Infrastructure 4249259Sdim// 5249259Sdim// This file is distributed under the University of Illinois Open Source 6249259Sdim// License. See LICENSE.TXT for details. 7249259Sdim// 8249259Sdim//===----------------------------------------------------------------------===// 9249259Sdim// 10249259Sdim/// \file 11249259Sdim/// \brief R600 implementation of the TargetRegisterInfo class. 12249259Sdim// 13249259Sdim//===----------------------------------------------------------------------===// 14249259Sdim 15249259Sdim#include "R600RegisterInfo.h" 16249259Sdim#include "AMDGPUTargetMachine.h" 17249259Sdim#include "R600Defines.h" 18249259Sdim#include "R600InstrInfo.h" 19249259Sdim#include "R600MachineFunctionInfo.h" 20249259Sdim 21249259Sdimusing namespace llvm; 22249259Sdim 23249259SdimR600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm, 24249259Sdim const TargetInstrInfo &tii) 25249259Sdim: AMDGPURegisterInfo(tm, tii), 26249259Sdim TM(tm), 27249259Sdim TII(tii) 28249259Sdim { } 29249259Sdim 30249259SdimBitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const { 31249259Sdim BitVector Reserved(getNumRegs()); 32249259Sdim 33249259Sdim Reserved.set(AMDGPU::ZERO); 34249259Sdim Reserved.set(AMDGPU::HALF); 35249259Sdim Reserved.set(AMDGPU::ONE); 36249259Sdim Reserved.set(AMDGPU::ONE_INT); 37249259Sdim Reserved.set(AMDGPU::NEG_HALF); 38249259Sdim Reserved.set(AMDGPU::NEG_ONE); 39249259Sdim Reserved.set(AMDGPU::PV_X); 40249259Sdim Reserved.set(AMDGPU::ALU_LITERAL_X); 41249259Sdim Reserved.set(AMDGPU::ALU_CONST); 42249259Sdim Reserved.set(AMDGPU::PREDICATE_BIT); 43249259Sdim Reserved.set(AMDGPU::PRED_SEL_OFF); 44249259Sdim Reserved.set(AMDGPU::PRED_SEL_ZERO); 45249259Sdim Reserved.set(AMDGPU::PRED_SEL_ONE); 46249259Sdim 47249259Sdim for (TargetRegisterClass::iterator I = AMDGPU::R600_AddrRegClass.begin(), 48249259Sdim E = AMDGPU::R600_AddrRegClass.end(); I != E; ++I) { 49249259Sdim Reserved.set(*I); 50249259Sdim } 51249259Sdim 52249259Sdim for (TargetRegisterClass::iterator I = AMDGPU::TRegMemRegClass.begin(), 53249259Sdim E = AMDGPU::TRegMemRegClass.end(); 54249259Sdim I != E; ++I) { 55249259Sdim Reserved.set(*I); 56249259Sdim } 57249259Sdim 58249259Sdim const R600InstrInfo *RII = static_cast<const R600InstrInfo*>(&TII); 59249259Sdim std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF); 60249259Sdim for (std::vector<unsigned>::iterator I = IndirectRegs.begin(), 61249259Sdim E = IndirectRegs.end(); 62249259Sdim I != E; ++I) { 63249259Sdim Reserved.set(*I); 64249259Sdim } 65249259Sdim return Reserved; 66249259Sdim} 67249259Sdim 68249259Sdimconst TargetRegisterClass * 69249259SdimR600RegisterInfo::getISARegClass(const TargetRegisterClass * rc) const { 70249259Sdim switch (rc->getID()) { 71249259Sdim case AMDGPU::GPRF32RegClassID: 72249259Sdim case AMDGPU::GPRI32RegClassID: 73249259Sdim return &AMDGPU::R600_Reg32RegClass; 74249259Sdim default: return rc; 75249259Sdim } 76249259Sdim} 77249259Sdim 78249259Sdimunsigned R600RegisterInfo::getHWRegChan(unsigned reg) const { 79249259Sdim return this->getEncodingValue(reg) >> HW_CHAN_SHIFT; 80249259Sdim} 81249259Sdim 82249259Sdimconst TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass( 83249259Sdim MVT VT) const { 84249259Sdim switch(VT.SimpleTy) { 85249259Sdim default: 86249259Sdim case MVT::i32: return &AMDGPU::R600_TReg32RegClass; 87249259Sdim } 88249259Sdim} 89249259Sdim 90249259Sdimunsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const { 91249259Sdim switch (Channel) { 92249259Sdim default: assert(!"Invalid channel index"); return 0; 93249259Sdim case 0: return AMDGPU::sub0; 94249259Sdim case 1: return AMDGPU::sub1; 95249259Sdim case 2: return AMDGPU::sub2; 96249259Sdim case 3: return AMDGPU::sub3; 97249259Sdim } 98249259Sdim} 99249259Sdim 100