1259698Sdim//===-- R600InstrFormats.td - R600 Instruction Encodings ------------------===// 2259698Sdim// 3259698Sdim// The LLVM Compiler Infrastructure 4259698Sdim// 5259698Sdim// This file is distributed under the University of Illinois Open Source 6259698Sdim// License. See LICENSE.TXT for details. 7259698Sdim// 8259698Sdim//===----------------------------------------------------------------------===// 9259698Sdim// 10259698Sdim// R600 Instruction format definitions. 11259698Sdim// 12259698Sdim//===----------------------------------------------------------------------===// 13259698Sdim 14259698Sdimclass InstR600 <dag outs, dag ins, string asm, list<dag> pattern, 15259698Sdim InstrItinClass itin> 16259698Sdim : AMDGPUInst <outs, ins, asm, pattern> { 17259698Sdim 18259698Sdim field bits<64> Inst; 19259698Sdim bit Trig = 0; 20259698Sdim bit Op3 = 0; 21259698Sdim bit isVector = 0; 22259698Sdim bits<2> FlagOperandIdx = 0; 23259698Sdim bit Op1 = 0; 24259698Sdim bit Op2 = 0; 25259698Sdim bit LDS_1A = 0; 26259698Sdim bit LDS_1A1D = 0; 27259698Sdim bit HasNativeOperands = 0; 28259698Sdim bit VTXInst = 0; 29259698Sdim bit TEXInst = 0; 30259698Sdim bit ALUInst = 0; 31259698Sdim bit IsExport = 0; 32259698Sdim bit LDS_1A2D = 0; 33259698Sdim 34259698Sdim let Namespace = "AMDGPU"; 35259698Sdim let OutOperandList = outs; 36259698Sdim let InOperandList = ins; 37259698Sdim let AsmString = asm; 38259698Sdim let Pattern = pattern; 39259698Sdim let Itinerary = itin; 40259698Sdim 41259698Sdim let TSFlags{4} = Trig; 42259698Sdim let TSFlags{5} = Op3; 43259698Sdim 44259698Sdim // Vector instructions are instructions that must fill all slots in an 45259698Sdim // instruction group 46259698Sdim let TSFlags{6} = isVector; 47259698Sdim let TSFlags{8-7} = FlagOperandIdx; 48259698Sdim let TSFlags{9} = HasNativeOperands; 49259698Sdim let TSFlags{10} = Op1; 50259698Sdim let TSFlags{11} = Op2; 51259698Sdim let TSFlags{12} = VTXInst; 52259698Sdim let TSFlags{13} = TEXInst; 53259698Sdim let TSFlags{14} = ALUInst; 54259698Sdim let TSFlags{15} = LDS_1A; 55259698Sdim let TSFlags{16} = LDS_1A1D; 56259698Sdim let TSFlags{17} = IsExport; 57259698Sdim let TSFlags{18} = LDS_1A2D; 58259698Sdim} 59259698Sdim 60259698Sdim//===----------------------------------------------------------------------===// 61259698Sdim// ALU instructions 62259698Sdim//===----------------------------------------------------------------------===// 63259698Sdim 64259698Sdimclass R600_ALU_LDS_Word0 { 65259698Sdim field bits<32> Word0; 66259698Sdim 67259698Sdim bits<11> src0; 68259698Sdim bits<1> src0_rel; 69259698Sdim bits<11> src1; 70259698Sdim bits<1> src1_rel; 71259698Sdim bits<3> index_mode = 0; 72259698Sdim bits<2> pred_sel; 73259698Sdim bits<1> last; 74259698Sdim 75259698Sdim bits<9> src0_sel = src0{8-0}; 76259698Sdim bits<2> src0_chan = src0{10-9}; 77259698Sdim bits<9> src1_sel = src1{8-0}; 78259698Sdim bits<2> src1_chan = src1{10-9}; 79259698Sdim 80259698Sdim let Word0{8-0} = src0_sel; 81259698Sdim let Word0{9} = src0_rel; 82259698Sdim let Word0{11-10} = src0_chan; 83259698Sdim let Word0{21-13} = src1_sel; 84259698Sdim let Word0{22} = src1_rel; 85259698Sdim let Word0{24-23} = src1_chan; 86259698Sdim let Word0{28-26} = index_mode; 87259698Sdim let Word0{30-29} = pred_sel; 88259698Sdim let Word0{31} = last; 89259698Sdim} 90259698Sdim 91259698Sdimclass R600ALU_Word0 : R600_ALU_LDS_Word0 { 92259698Sdim 93259698Sdim bits<1> src0_neg; 94259698Sdim bits<1> src1_neg; 95259698Sdim 96259698Sdim let Word0{12} = src0_neg; 97259698Sdim let Word0{25} = src1_neg; 98259698Sdim} 99259698Sdim 100259698Sdimclass R600ALU_Word1 { 101259698Sdim field bits<32> Word1; 102259698Sdim 103259698Sdim bits<11> dst; 104259698Sdim bits<3> bank_swizzle; 105259698Sdim bits<1> dst_rel; 106259698Sdim bits<1> clamp; 107259698Sdim 108259698Sdim bits<7> dst_sel = dst{6-0}; 109259698Sdim bits<2> dst_chan = dst{10-9}; 110259698Sdim 111259698Sdim let Word1{20-18} = bank_swizzle; 112259698Sdim let Word1{27-21} = dst_sel; 113259698Sdim let Word1{28} = dst_rel; 114259698Sdim let Word1{30-29} = dst_chan; 115259698Sdim let Word1{31} = clamp; 116259698Sdim} 117259698Sdim 118259698Sdimclass R600ALU_Word1_OP2 <bits<11> alu_inst> : R600ALU_Word1{ 119259698Sdim 120259698Sdim bits<1> src0_abs; 121259698Sdim bits<1> src1_abs; 122259698Sdim bits<1> update_exec_mask; 123259698Sdim bits<1> update_pred; 124259698Sdim bits<1> write; 125259698Sdim bits<2> omod; 126259698Sdim 127259698Sdim let Word1{0} = src0_abs; 128259698Sdim let Word1{1} = src1_abs; 129259698Sdim let Word1{2} = update_exec_mask; 130259698Sdim let Word1{3} = update_pred; 131259698Sdim let Word1{4} = write; 132259698Sdim let Word1{6-5} = omod; 133259698Sdim let Word1{17-7} = alu_inst; 134259698Sdim} 135259698Sdim 136259698Sdimclass R600ALU_Word1_OP3 <bits<5> alu_inst> : R600ALU_Word1{ 137259698Sdim 138259698Sdim bits<11> src2; 139259698Sdim bits<1> src2_rel; 140259698Sdim bits<1> src2_neg; 141259698Sdim 142259698Sdim bits<9> src2_sel = src2{8-0}; 143259698Sdim bits<2> src2_chan = src2{10-9}; 144259698Sdim 145259698Sdim let Word1{8-0} = src2_sel; 146259698Sdim let Word1{9} = src2_rel; 147259698Sdim let Word1{11-10} = src2_chan; 148259698Sdim let Word1{12} = src2_neg; 149259698Sdim let Word1{17-13} = alu_inst; 150259698Sdim} 151259698Sdim 152259698Sdimclass R600LDS_Word1 { 153259698Sdim field bits<32> Word1; 154259698Sdim 155259698Sdim bits<11> src2; 156259698Sdim bits<9> src2_sel = src2{8-0}; 157259698Sdim bits<2> src2_chan = src2{10-9}; 158259698Sdim bits<1> src2_rel; 159259698Sdim // offset specifies the stride offset to the second set of data to be read 160259698Sdim // from. This is a dword offset. 161259698Sdim bits<5> alu_inst = 17; // OP3_INST_LDS_IDX_OP 162259698Sdim bits<3> bank_swizzle; 163259698Sdim bits<6> lds_op; 164259698Sdim bits<2> dst_chan = 0; 165259698Sdim 166259698Sdim let Word1{8-0} = src2_sel; 167259698Sdim let Word1{9} = src2_rel; 168259698Sdim let Word1{11-10} = src2_chan; 169259698Sdim let Word1{17-13} = alu_inst; 170259698Sdim let Word1{20-18} = bank_swizzle; 171259698Sdim let Word1{26-21} = lds_op; 172259698Sdim let Word1{30-29} = dst_chan; 173259698Sdim} 174259698Sdim 175259698Sdim 176259698Sdim/* 177259698SdimXXX: R600 subtarget uses a slightly different encoding than the other 178259698Sdimsubtargets. We currently handle this in R600MCCodeEmitter, but we may 179259698Sdimwant to use these instruction classes in the future. 180259698Sdim 181259698Sdimclass R600ALU_Word1_OP2_r600 : R600ALU_Word1_OP2 { 182259698Sdim 183259698Sdim bits<1> fog_merge; 184259698Sdim bits<10> alu_inst; 185259698Sdim 186259698Sdim let Inst{37} = fog_merge; 187259698Sdim let Inst{39-38} = omod; 188259698Sdim let Inst{49-40} = alu_inst; 189259698Sdim} 190259698Sdim 191259698Sdimclass R600ALU_Word1_OP2_r700 : R600ALU_Word1_OP2 { 192259698Sdim 193259698Sdim bits<11> alu_inst; 194259698Sdim 195259698Sdim let Inst{38-37} = omod; 196259698Sdim let Inst{49-39} = alu_inst; 197259698Sdim} 198259698Sdim*/ 199259698Sdim 200259698Sdim//===----------------------------------------------------------------------===// 201259698Sdim// Vertex Fetch instructions 202259698Sdim//===----------------------------------------------------------------------===// 203259698Sdim 204259698Sdimclass VTX_WORD0 { 205259698Sdim field bits<32> Word0; 206259698Sdim bits<7> src_gpr; 207259698Sdim bits<5> VC_INST; 208259698Sdim bits<2> FETCH_TYPE; 209259698Sdim bits<1> FETCH_WHOLE_QUAD; 210259698Sdim bits<8> BUFFER_ID; 211259698Sdim bits<1> SRC_REL; 212259698Sdim bits<2> SRC_SEL_X; 213259698Sdim 214259698Sdim let Word0{4-0} = VC_INST; 215259698Sdim let Word0{6-5} = FETCH_TYPE; 216259698Sdim let Word0{7} = FETCH_WHOLE_QUAD; 217259698Sdim let Word0{15-8} = BUFFER_ID; 218259698Sdim let Word0{22-16} = src_gpr; 219259698Sdim let Word0{23} = SRC_REL; 220259698Sdim let Word0{25-24} = SRC_SEL_X; 221259698Sdim} 222259698Sdim 223259698Sdimclass VTX_WORD0_eg : VTX_WORD0 { 224259698Sdim 225259698Sdim bits<6> MEGA_FETCH_COUNT; 226259698Sdim 227259698Sdim let Word0{31-26} = MEGA_FETCH_COUNT; 228259698Sdim} 229259698Sdim 230259698Sdimclass VTX_WORD0_cm : VTX_WORD0 { 231259698Sdim 232259698Sdim bits<2> SRC_SEL_Y; 233259698Sdim bits<2> STRUCTURED_READ; 234259698Sdim bits<1> LDS_REQ; 235259698Sdim bits<1> COALESCED_READ; 236259698Sdim 237259698Sdim let Word0{27-26} = SRC_SEL_Y; 238259698Sdim let Word0{29-28} = STRUCTURED_READ; 239259698Sdim let Word0{30} = LDS_REQ; 240259698Sdim let Word0{31} = COALESCED_READ; 241259698Sdim} 242259698Sdim 243259698Sdimclass VTX_WORD1_GPR { 244259698Sdim field bits<32> Word1; 245259698Sdim bits<7> dst_gpr; 246259698Sdim bits<1> DST_REL; 247259698Sdim bits<3> DST_SEL_X; 248259698Sdim bits<3> DST_SEL_Y; 249259698Sdim bits<3> DST_SEL_Z; 250259698Sdim bits<3> DST_SEL_W; 251259698Sdim bits<1> USE_CONST_FIELDS; 252259698Sdim bits<6> DATA_FORMAT; 253259698Sdim bits<2> NUM_FORMAT_ALL; 254259698Sdim bits<1> FORMAT_COMP_ALL; 255259698Sdim bits<1> SRF_MODE_ALL; 256259698Sdim 257259698Sdim let Word1{6-0} = dst_gpr; 258259698Sdim let Word1{7} = DST_REL; 259259698Sdim let Word1{8} = 0; // Reserved 260259698Sdim let Word1{11-9} = DST_SEL_X; 261259698Sdim let Word1{14-12} = DST_SEL_Y; 262259698Sdim let Word1{17-15} = DST_SEL_Z; 263259698Sdim let Word1{20-18} = DST_SEL_W; 264259698Sdim let Word1{21} = USE_CONST_FIELDS; 265259698Sdim let Word1{27-22} = DATA_FORMAT; 266259698Sdim let Word1{29-28} = NUM_FORMAT_ALL; 267259698Sdim let Word1{30} = FORMAT_COMP_ALL; 268259698Sdim let Word1{31} = SRF_MODE_ALL; 269259698Sdim} 270259698Sdim 271259698Sdim//===----------------------------------------------------------------------===// 272259698Sdim// Texture fetch instructions 273259698Sdim//===----------------------------------------------------------------------===// 274259698Sdim 275259698Sdimclass TEX_WORD0 { 276259698Sdim field bits<32> Word0; 277259698Sdim 278259698Sdim bits<5> TEX_INST; 279259698Sdim bits<2> INST_MOD; 280259698Sdim bits<1> FETCH_WHOLE_QUAD; 281259698Sdim bits<8> RESOURCE_ID; 282259698Sdim bits<7> SRC_GPR; 283259698Sdim bits<1> SRC_REL; 284259698Sdim bits<1> ALT_CONST; 285259698Sdim bits<2> RESOURCE_INDEX_MODE; 286259698Sdim bits<2> SAMPLER_INDEX_MODE; 287259698Sdim 288259698Sdim let Word0{4-0} = TEX_INST; 289259698Sdim let Word0{6-5} = INST_MOD; 290259698Sdim let Word0{7} = FETCH_WHOLE_QUAD; 291259698Sdim let Word0{15-8} = RESOURCE_ID; 292259698Sdim let Word0{22-16} = SRC_GPR; 293259698Sdim let Word0{23} = SRC_REL; 294259698Sdim let Word0{24} = ALT_CONST; 295259698Sdim let Word0{26-25} = RESOURCE_INDEX_MODE; 296259698Sdim let Word0{28-27} = SAMPLER_INDEX_MODE; 297259698Sdim} 298259698Sdim 299259698Sdimclass TEX_WORD1 { 300259698Sdim field bits<32> Word1; 301259698Sdim 302259698Sdim bits<7> DST_GPR; 303259698Sdim bits<1> DST_REL; 304259698Sdim bits<3> DST_SEL_X; 305259698Sdim bits<3> DST_SEL_Y; 306259698Sdim bits<3> DST_SEL_Z; 307259698Sdim bits<3> DST_SEL_W; 308259698Sdim bits<7> LOD_BIAS; 309259698Sdim bits<1> COORD_TYPE_X; 310259698Sdim bits<1> COORD_TYPE_Y; 311259698Sdim bits<1> COORD_TYPE_Z; 312259698Sdim bits<1> COORD_TYPE_W; 313259698Sdim 314259698Sdim let Word1{6-0} = DST_GPR; 315259698Sdim let Word1{7} = DST_REL; 316259698Sdim let Word1{11-9} = DST_SEL_X; 317259698Sdim let Word1{14-12} = DST_SEL_Y; 318259698Sdim let Word1{17-15} = DST_SEL_Z; 319259698Sdim let Word1{20-18} = DST_SEL_W; 320259698Sdim let Word1{27-21} = LOD_BIAS; 321259698Sdim let Word1{28} = COORD_TYPE_X; 322259698Sdim let Word1{29} = COORD_TYPE_Y; 323259698Sdim let Word1{30} = COORD_TYPE_Z; 324259698Sdim let Word1{31} = COORD_TYPE_W; 325259698Sdim} 326259698Sdim 327259698Sdimclass TEX_WORD2 { 328259698Sdim field bits<32> Word2; 329259698Sdim 330259698Sdim bits<5> OFFSET_X; 331259698Sdim bits<5> OFFSET_Y; 332259698Sdim bits<5> OFFSET_Z; 333259698Sdim bits<5> SAMPLER_ID; 334259698Sdim bits<3> SRC_SEL_X; 335259698Sdim bits<3> SRC_SEL_Y; 336259698Sdim bits<3> SRC_SEL_Z; 337259698Sdim bits<3> SRC_SEL_W; 338259698Sdim 339259698Sdim let Word2{4-0} = OFFSET_X; 340259698Sdim let Word2{9-5} = OFFSET_Y; 341259698Sdim let Word2{14-10} = OFFSET_Z; 342259698Sdim let Word2{19-15} = SAMPLER_ID; 343259698Sdim let Word2{22-20} = SRC_SEL_X; 344259698Sdim let Word2{25-23} = SRC_SEL_Y; 345259698Sdim let Word2{28-26} = SRC_SEL_Z; 346259698Sdim let Word2{31-29} = SRC_SEL_W; 347259698Sdim} 348259698Sdim 349259698Sdim//===----------------------------------------------------------------------===// 350259698Sdim// Control Flow Instructions 351259698Sdim//===----------------------------------------------------------------------===// 352259698Sdim 353259698Sdimclass CF_WORD1_R600 { 354259698Sdim field bits<32> Word1; 355259698Sdim 356259698Sdim bits<3> POP_COUNT; 357259698Sdim bits<5> CF_CONST; 358259698Sdim bits<2> COND; 359259698Sdim bits<3> COUNT; 360259698Sdim bits<6> CALL_COUNT; 361259698Sdim bits<1> COUNT_3; 362259698Sdim bits<1> END_OF_PROGRAM; 363259698Sdim bits<1> VALID_PIXEL_MODE; 364259698Sdim bits<7> CF_INST; 365259698Sdim bits<1> WHOLE_QUAD_MODE; 366259698Sdim bits<1> BARRIER; 367259698Sdim 368259698Sdim let Word1{2-0} = POP_COUNT; 369259698Sdim let Word1{7-3} = CF_CONST; 370259698Sdim let Word1{9-8} = COND; 371259698Sdim let Word1{12-10} = COUNT; 372259698Sdim let Word1{18-13} = CALL_COUNT; 373259698Sdim let Word1{19} = COUNT_3; 374259698Sdim let Word1{21} = END_OF_PROGRAM; 375259698Sdim let Word1{22} = VALID_PIXEL_MODE; 376259698Sdim let Word1{29-23} = CF_INST; 377259698Sdim let Word1{30} = WHOLE_QUAD_MODE; 378259698Sdim let Word1{31} = BARRIER; 379259698Sdim} 380259698Sdim 381259698Sdimclass CF_WORD0_EG { 382259698Sdim field bits<32> Word0; 383259698Sdim 384259698Sdim bits<24> ADDR; 385259698Sdim bits<3> JUMPTABLE_SEL; 386259698Sdim 387259698Sdim let Word0{23-0} = ADDR; 388259698Sdim let Word0{26-24} = JUMPTABLE_SEL; 389259698Sdim} 390259698Sdim 391259698Sdimclass CF_WORD1_EG { 392259698Sdim field bits<32> Word1; 393259698Sdim 394259698Sdim bits<3> POP_COUNT; 395259698Sdim bits<5> CF_CONST; 396259698Sdim bits<2> COND; 397259698Sdim bits<6> COUNT; 398259698Sdim bits<1> VALID_PIXEL_MODE; 399259698Sdim bits<1> END_OF_PROGRAM; 400259698Sdim bits<8> CF_INST; 401259698Sdim bits<1> BARRIER; 402259698Sdim 403259698Sdim let Word1{2-0} = POP_COUNT; 404259698Sdim let Word1{7-3} = CF_CONST; 405259698Sdim let Word1{9-8} = COND; 406259698Sdim let Word1{15-10} = COUNT; 407259698Sdim let Word1{20} = VALID_PIXEL_MODE; 408259698Sdim let Word1{21} = END_OF_PROGRAM; 409259698Sdim let Word1{29-22} = CF_INST; 410259698Sdim let Word1{31} = BARRIER; 411259698Sdim} 412259698Sdim 413259698Sdimclass CF_ALU_WORD0 { 414259698Sdim field bits<32> Word0; 415259698Sdim 416259698Sdim bits<22> ADDR; 417259698Sdim bits<4> KCACHE_BANK0; 418259698Sdim bits<4> KCACHE_BANK1; 419259698Sdim bits<2> KCACHE_MODE0; 420259698Sdim 421259698Sdim let Word0{21-0} = ADDR; 422259698Sdim let Word0{25-22} = KCACHE_BANK0; 423259698Sdim let Word0{29-26} = KCACHE_BANK1; 424259698Sdim let Word0{31-30} = KCACHE_MODE0; 425259698Sdim} 426259698Sdim 427259698Sdimclass CF_ALU_WORD1 { 428259698Sdim field bits<32> Word1; 429259698Sdim 430259698Sdim bits<2> KCACHE_MODE1; 431259698Sdim bits<8> KCACHE_ADDR0; 432259698Sdim bits<8> KCACHE_ADDR1; 433259698Sdim bits<7> COUNT; 434259698Sdim bits<1> ALT_CONST; 435259698Sdim bits<4> CF_INST; 436259698Sdim bits<1> WHOLE_QUAD_MODE; 437259698Sdim bits<1> BARRIER; 438259698Sdim 439259698Sdim let Word1{1-0} = KCACHE_MODE1; 440259698Sdim let Word1{9-2} = KCACHE_ADDR0; 441259698Sdim let Word1{17-10} = KCACHE_ADDR1; 442259698Sdim let Word1{24-18} = COUNT; 443259698Sdim let Word1{25} = ALT_CONST; 444259698Sdim let Word1{29-26} = CF_INST; 445259698Sdim let Word1{30} = WHOLE_QUAD_MODE; 446259698Sdim let Word1{31} = BARRIER; 447259698Sdim} 448259698Sdim 449259698Sdimclass CF_ALLOC_EXPORT_WORD0_RAT { 450259698Sdim field bits<32> Word0; 451259698Sdim 452259698Sdim bits<4> rat_id; 453259698Sdim bits<6> rat_inst; 454259698Sdim bits<2> rim; 455259698Sdim bits<2> type; 456259698Sdim bits<7> rw_gpr; 457259698Sdim bits<1> rw_rel; 458259698Sdim bits<7> index_gpr; 459259698Sdim bits<2> elem_size; 460259698Sdim 461259698Sdim let Word0{3-0} = rat_id; 462259698Sdim let Word0{9-4} = rat_inst; 463259698Sdim let Word0{10} = 0; // Reserved 464259698Sdim let Word0{12-11} = rim; 465259698Sdim let Word0{14-13} = type; 466259698Sdim let Word0{21-15} = rw_gpr; 467259698Sdim let Word0{22} = rw_rel; 468259698Sdim let Word0{29-23} = index_gpr; 469259698Sdim let Word0{31-30} = elem_size; 470259698Sdim} 471259698Sdim 472259698Sdimclass CF_ALLOC_EXPORT_WORD1_BUF { 473259698Sdim field bits<32> Word1; 474259698Sdim 475259698Sdim bits<12> array_size; 476259698Sdim bits<4> comp_mask; 477259698Sdim bits<4> burst_count; 478259698Sdim bits<1> vpm; 479259698Sdim bits<1> eop; 480259698Sdim bits<8> cf_inst; 481259698Sdim bits<1> mark; 482259698Sdim bits<1> barrier; 483259698Sdim 484259698Sdim let Word1{11-0} = array_size; 485259698Sdim let Word1{15-12} = comp_mask; 486259698Sdim let Word1{19-16} = burst_count; 487259698Sdim let Word1{20} = vpm; 488259698Sdim let Word1{21} = eop; 489259698Sdim let Word1{29-22} = cf_inst; 490259698Sdim let Word1{30} = mark; 491259698Sdim let Word1{31} = barrier; 492259698Sdim} 493