PPCScheduleG5.td revision 256281
1173143Srwatson//===-- PPCScheduleG5.td - PPC G5 Scheduling Definitions ---*- tablegen -*-===// 2156283Srwatson// 3156283Srwatson// The LLVM Compiler Infrastructure 4156283Srwatson// 5173143Srwatson// This file is distributed under the University of Illinois Open Source 6156283Srwatson// License. See LICENSE.TXT for details. 7156283Srwatson// 8156283Srwatson//===----------------------------------------------------------------------===// 9156283Srwatson// 10156283Srwatson// This file defines the itinerary class data for the G5 (970) processor. 11156283Srwatson// 12156283Srwatson//===----------------------------------------------------------------------===// 13156283Srwatson 14156283Srwatsondef G5Itineraries : ProcessorItineraries< 15156283Srwatson [IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [], [ 16156283Srwatson InstrItinData<IntSimple , [InstrStage<2, [IU1, IU2]>]>, 17156283Srwatson InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>, 18186647Srwatson InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>, 19156283Srwatson InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>, 20156283Srwatson InstrItinData<IntDivW , [InstrStage<36, [IU1]>]>, 21156283Srwatson InstrItinData<IntMFFS , [InstrStage<6, [IU2]>]>, 22156283Srwatson InstrItinData<IntMFVSCR , [InstrStage<1, [VFPU]>]>, 23156283Srwatson InstrItinData<IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>, 24156283Srwatson InstrItinData<IntMulHD , [InstrStage<7, [IU1, IU2]>]>, 25156283Srwatson InstrItinData<IntMulHW , [InstrStage<5, [IU1, IU2]>]>, 26156283Srwatson InstrItinData<IntMulHWU , [InstrStage<5, [IU1, IU2]>]>, 27156283Srwatson InstrItinData<IntMulLI , [InstrStage<4, [IU1, IU2]>]>, 28156283Srwatson InstrItinData<IntRFID , [InstrStage<1, [IU2]>]>, 29156283Srwatson InstrItinData<IntRotateD , [InstrStage<2, [IU1, IU2]>]>, 30156283Srwatson InstrItinData<IntRotateDI , [InstrStage<2, [IU1, IU2]>]>, 31156283Srwatson InstrItinData<IntRotate , [InstrStage<4, [IU1, IU2]>]>, 32156283Srwatson InstrItinData<IntShift , [InstrStage<2, [IU1, IU2]>]>, 33156283Srwatson InstrItinData<IntTrapD , [InstrStage<1, [IU1, IU2]>]>, 34156283Srwatson InstrItinData<IntTrapW , [InstrStage<1, [IU1, IU2]>]>, 35156283Srwatson InstrItinData<BrB , [InstrStage<1, [BPU]>]>, 36156283Srwatson InstrItinData<BrCR , [InstrStage<4, [BPU]>]>, 37156283Srwatson InstrItinData<BrMCR , [InstrStage<2, [BPU]>]>, 38156283Srwatson InstrItinData<BrMCRX , [InstrStage<3, [BPU]>]>, 39156283Srwatson InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, 40156283Srwatson InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>, 41156283Srwatson InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>, 42156283Srwatson InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>, 43156283Srwatson InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>, 44156283Srwatson InstrItinData<LdStDSS , [InstrStage<10, [SLU]>]>, 45156283Srwatson InstrItinData<LdStICBI , [InstrStage<40, [SLU]>]>, 46156283Srwatson InstrItinData<LdStSTFD , [InstrStage<4, [SLU]>]>, 47156283Srwatson InstrItinData<LdStSTFDU , [InstrStage<4, [SLU]>]>, 48156283Srwatson InstrItinData<LdStLD , [InstrStage<3, [SLU]>]>, 49156283Srwatson InstrItinData<LdStLDU , [InstrStage<3, [SLU]>]>, 50156283Srwatson InstrItinData<LdStLDARX , [InstrStage<11, [SLU]>]>, 51156283Srwatson InstrItinData<LdStLFD , [InstrStage<3, [SLU]>]>, 52156283Srwatson InstrItinData<LdStLFDU , [InstrStage<5, [SLU]>]>, 53156283Srwatson InstrItinData<LdStLHA , [InstrStage<5, [SLU]>]>, 54156283Srwatson InstrItinData<LdStLHAU , [InstrStage<5, [SLU]>]>, 55156283Srwatson InstrItinData<LdStLMW , [InstrStage<64, [SLU]>]>, 56156283Srwatson InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>, 57156283Srwatson InstrItinData<LdStLWA , [InstrStage<5, [SLU]>]>, 58156283Srwatson InstrItinData<LdStLWARX , [InstrStage<11, [SLU]>]>, 59156283Srwatson InstrItinData<LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work 60156283Srwatson InstrItinData<LdStSLBIE , [InstrStage<2, [SLU]>]>, 61156283Srwatson InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>, 62156283Srwatson InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>, 63186647Srwatson InstrItinData<LdStSTDCX , [InstrStage<11, [SLU]>]>, 64186647Srwatson InstrItinData<LdStSTVEBX , [InstrStage<5, [SLU]>]>, 65156283Srwatson InstrItinData<LdStSTWCX , [InstrStage<11, [SLU]>]>, 66156283Srwatson InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>, 67156283Srwatson InstrItinData<SprISYNC , [InstrStage<40, [SLU]>]>, // needs work 68186647Srwatson InstrItinData<SprMFSR , [InstrStage<3, [SLU]>]>, 69186647Srwatson InstrItinData<SprMTMSR , [InstrStage<3, [SLU]>]>, 70156283Srwatson InstrItinData<SprMTSR , [InstrStage<3, [SLU]>]>, 71173143Srwatson InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>, 72156283Srwatson InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>, 73156283Srwatson InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>, 74156283Srwatson InstrItinData<SprMFSPR , [InstrStage<3, [IU2]>]>, 75156283Srwatson InstrItinData<SprMFTB , [InstrStage<10, [IU2]>]>, 76173143Srwatson InstrItinData<SprMTSPR , [InstrStage<8, [IU2]>]>, 77173143Srwatson InstrItinData<SprSC , [InstrStage<1, [IU2]>]>, 78173143Srwatson InstrItinData<FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>, 79156283Srwatson InstrItinData<FPAddSub , [InstrStage<6, [FPU1, FPU2]>]>, 80173143Srwatson InstrItinData<FPCompare , [InstrStage<8, [FPU1, FPU2]>]>, 81173143Srwatson InstrItinData<FPDivD , [InstrStage<33, [FPU1, FPU2]>]>, 82173143Srwatson InstrItinData<FPDivS , [InstrStage<33, [FPU1, FPU2]>]>, 83156283Srwatson InstrItinData<FPFused , [InstrStage<6, [FPU1, FPU2]>]>, 84156283Srwatson InstrItinData<FPRes , [InstrStage<6, [FPU1, FPU2]>]>, 85156283Srwatson InstrItinData<FPSqrt , [InstrStage<40, [FPU1, FPU2]>]>, 86156283Srwatson InstrItinData<VecGeneral , [InstrStage<2, [VIU1]>]>, 87156283Srwatson InstrItinData<VecFP , [InstrStage<8, [VFPU]>]>, 88156283Srwatson InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>, 89156283Srwatson InstrItinData<VecComplex , [InstrStage<5, [VIU2]>]>, 90156283Srwatson InstrItinData<VecPerm , [InstrStage<3, [VPU]>]>, 91156283Srwatson InstrItinData<VecFPRound , [InstrStage<8, [VFPU]>]>, 92156283Srwatson InstrItinData<VecVSL , [InstrStage<2, [VIU1]>]>, 93156283Srwatson InstrItinData<VecVSR , [InstrStage<3, [VPU]>]> 94156283Srwatson]>; 95156283Srwatson 96156283Srwatson// ===---------------------------------------------------------------------===// 97156283Srwatson// e5500 machine model for scheduling and other instruction cost heuristics. 98156283Srwatson 99156283Srwatsondef G5Model : SchedMachineModel { 100156283Srwatson let IssueWidth = 4; // 4 (non-branch) instructions are dispatched per cycle. 101156283Srwatson let MinLatency = 0; // Out-of-order dispatch. 102156283Srwatson let LoadLatency = 3; // Optimistic load latency assuming bypass. 103156283Srwatson // This is overriden by OperandCycles if the 104156283Srwatson // Itineraries are queried instead. 105156283Srwatson let MispredictPenalty = 16; 106156283Srwatson 107156283Srwatson let Itineraries = G5Itineraries; 108156283Srwatson} 109156283Srwatson 110156283Srwatson