PPCScheduleG5.td revision 218893 
1//===- PPCScheduleG5.td - PPC G5 Scheduling Definitions ----*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file defines the itinerary class data for the G5 (970) processor.
11//
12//===----------------------------------------------------------------------===//
13
14def G5Itineraries : ProcessorItineraries<
15  [IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [], [
16  InstrItinData<IntGeneral  , [InstrStage<2, [IU1, IU2]>]>,
17  InstrItinData<IntCompare  , [InstrStage<3, [IU1, IU2]>]>,
18  InstrItinData<IntDivD     , [InstrStage<68, [IU1]>]>,
19  InstrItinData<IntDivW     , [InstrStage<36, [IU1]>]>,
20  InstrItinData<IntMFFS     , [InstrStage<6, [IU2]>]>,
21  InstrItinData<IntMFVSCR   , [InstrStage<1, [VFPU]>]>,
22  InstrItinData<IntMTFSB0   , [InstrStage<6, [FPU1, FPU2]>]>,
23  InstrItinData<IntMulHD    , [InstrStage<7, [IU1, IU2]>]>,
24  InstrItinData<IntMulHW    , [InstrStage<5, [IU1, IU2]>]>,
25  InstrItinData<IntMulHWU   , [InstrStage<5, [IU1, IU2]>]>,
26  InstrItinData<IntMulLI    , [InstrStage<4, [IU1, IU2]>]>,
27  InstrItinData<IntRFID     , [InstrStage<1, [IU2]>]>,
28  InstrItinData<IntRotateD  , [InstrStage<2, [IU1, IU2]>]>,
29  InstrItinData<IntRotate   , [InstrStage<4, [IU1, IU2]>]>,
30  InstrItinData<IntShift    , [InstrStage<2, [IU1, IU2]>]>,
31  InstrItinData<IntTrapD    , [InstrStage<1, [IU1, IU2]>]>,
32  InstrItinData<IntTrapW    , [InstrStage<1, [IU1, IU2]>]>,
33  InstrItinData<BrB         , [InstrStage<1, [BPU]>]>,
34  InstrItinData<BrCR        , [InstrStage<4, [BPU]>]>,
35  InstrItinData<BrMCR       , [InstrStage<2, [BPU]>]>,
36  InstrItinData<BrMCRX      , [InstrStage<3, [BPU]>]>,
37  InstrItinData<LdStDCBF    , [InstrStage<3, [SLU]>]>,
38  InstrItinData<LdStGeneral , [InstrStage<3, [SLU]>]>,
39  InstrItinData<LdStDSS     , [InstrStage<10, [SLU]>]>,
40  InstrItinData<LdStICBI    , [InstrStage<40, [SLU]>]>,
41  InstrItinData<LdStUX      , [InstrStage<4, [SLU]>]>,
42  InstrItinData<LdStLD      , [InstrStage<3, [SLU]>]>,
43  InstrItinData<LdStLDARX   , [InstrStage<11, [SLU]>]>,
44  InstrItinData<LdStLFD     , [InstrStage<3, [SLU]>]>,
45  InstrItinData<LdStLFDU    , [InstrStage<5, [SLU]>]>,
46  InstrItinData<LdStLHA     , [InstrStage<5, [SLU]>]>,
47  InstrItinData<LdStLMW     , [InstrStage<64, [SLU]>]>,
48  InstrItinData<LdStLVecX   , [InstrStage<3, [SLU]>]>,
49  InstrItinData<LdStLWA     , [InstrStage<5, [SLU]>]>,
50  InstrItinData<LdStLWARX   , [InstrStage<11, [SLU]>]>,
51  InstrItinData<LdStSLBIA   , [InstrStage<40, [SLU]>]>, // needs work
52  InstrItinData<LdStSLBIE   , [InstrStage<2, [SLU]>]>,
53  InstrItinData<LdStSTD     , [InstrStage<3, [SLU]>]>,
54  InstrItinData<LdStSTDCX   , [InstrStage<11, [SLU]>]>,
55  InstrItinData<LdStSTVEBX  , [InstrStage<5, [SLU]>]>,
56  InstrItinData<LdStSTWCX   , [InstrStage<11, [SLU]>]>,
57  InstrItinData<LdStSync    , [InstrStage<35, [SLU]>]>,
58  InstrItinData<SprISYNC    , [InstrStage<40, [SLU]>]>, // needs work
59  InstrItinData<SprMFSR     , [InstrStage<3, [SLU]>]>,
60  InstrItinData<SprMTMSR    , [InstrStage<3, [SLU]>]>,
61  InstrItinData<SprMTSR     , [InstrStage<3, [SLU]>]>,
62  InstrItinData<SprTLBSYNC  , [InstrStage<3, [SLU]>]>,
63  InstrItinData<SprMFCR     , [InstrStage<2, [IU2]>]>,
64  InstrItinData<SprMFMSR    , [InstrStage<3, [IU2]>]>,
65  InstrItinData<SprMFSPR    , [InstrStage<3, [IU2]>]>,
66  InstrItinData<SprMFTB     , [InstrStage<10, [IU2]>]>,
67  InstrItinData<SprMTSPR    , [InstrStage<8, [IU2]>]>,
68  InstrItinData<SprSC       , [InstrStage<1, [IU2]>]>,
69  InstrItinData<FPGeneral   , [InstrStage<6, [FPU1, FPU2]>]>,
70  InstrItinData<FPCompare   , [InstrStage<8, [FPU1, FPU2]>]>,
71  InstrItinData<FPDivD      , [InstrStage<33, [FPU1, FPU2]>]>,
72  InstrItinData<FPDivS      , [InstrStage<33, [FPU1, FPU2]>]>,
73  InstrItinData<FPFused     , [InstrStage<6, [FPU1, FPU2]>]>,
74  InstrItinData<FPRes       , [InstrStage<6, [FPU1, FPU2]>]>,
75  InstrItinData<FPSqrt      , [InstrStage<40, [FPU1, FPU2]>]>,
76  InstrItinData<VecGeneral  , [InstrStage<2, [VIU1]>]>,
77  InstrItinData<VecFP       , [InstrStage<8, [VFPU]>]>,
78  InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,
79  InstrItinData<VecComplex  , [InstrStage<5, [VIU2]>]>,
80  InstrItinData<VecPerm     , [InstrStage<3, [VPU]>]>,
81  InstrItinData<VecFPRound  , [InstrStage<8, [VFPU]>]>,
82  InstrItinData<VecVSL      , [InstrStage<2, [VIU1]>]>,
83  InstrItinData<VecVSR      , [InstrStage<3, [VPU]>]>
84]>;
85