PPCScheduleG5.td revision 208954
1158795Sdelphij//===- PPCScheduleG5.td - PPC G5 Scheduling Definitions ----*- tablegen -*-===// 2141261Sdelphij// 3141261Sdelphij// The LLVM Compiler Infrastructure 4141261Sdelphij// 5158795Sdelphij// This file is distributed under the University of Illinois Open Source 6141261Sdelphij// License. See LICENSE.TXT for details. 7141261Sdelphij// 8141261Sdelphij//===----------------------------------------------------------------------===// 9141261Sdelphij// 10141261Sdelphij// This file defines the itinerary class data for the G5 (970) processor. 11141261Sdelphij// 12141261Sdelphij//===----------------------------------------------------------------------===// 13141261Sdelphij 14141261Sdelphijdef G5Itineraries : ProcessorItineraries< 15141261Sdelphij [IU1, IU2, SLU, BPU, FPU1, FPU2, VFPU, VIU1, VIU2, VPU], [ 16141261Sdelphij InstrItinData<IntGeneral , [InstrStage<2, [IU1, IU2]>]>, 17141261Sdelphij InstrItinData<IntCompare , [InstrStage<3, [IU1, IU2]>]>, 18141261Sdelphij InstrItinData<IntDivD , [InstrStage<68, [IU1]>]>, 19141261Sdelphij InstrItinData<IntDivW , [InstrStage<36, [IU1]>]>, 20141261Sdelphij InstrItinData<IntMFFS , [InstrStage<6, [IU2]>]>, 21141261Sdelphij InstrItinData<IntMFVSCR , [InstrStage<1, [VFPU]>]>, 22141261Sdelphij InstrItinData<IntMTFSB0 , [InstrStage<6, [FPU1, FPU2]>]>, 23141261Sdelphij InstrItinData<IntMulHD , [InstrStage<7, [IU1, IU2]>]>, 24141261Sdelphij InstrItinData<IntMulHW , [InstrStage<5, [IU1, IU2]>]>, 25141261Sdelphij InstrItinData<IntMulHWU , [InstrStage<5, [IU1, IU2]>]>, 26141261Sdelphij InstrItinData<IntMulLI , [InstrStage<4, [IU1, IU2]>]>, 27141261Sdelphij InstrItinData<IntRFID , [InstrStage<1, [IU2]>]>, 28141261Sdelphij InstrItinData<IntRotateD , [InstrStage<2, [IU1, IU2]>]>, 29141261Sdelphij InstrItinData<IntRotate , [InstrStage<4, [IU1, IU2]>]>, 30141261Sdelphij InstrItinData<IntShift , [InstrStage<2, [IU1, IU2]>]>, 31141261Sdelphij InstrItinData<IntTrapD , [InstrStage<1, [IU1, IU2]>]>, 32141261Sdelphij InstrItinData<IntTrapW , [InstrStage<1, [IU1, IU2]>]>, 33141261Sdelphij InstrItinData<BrB , [InstrStage<1, [BPU]>]>, 34141261Sdelphij InstrItinData<BrCR , [InstrStage<4, [BPU]>]>, 35141261Sdelphij InstrItinData<BrMCR , [InstrStage<2, [BPU]>]>, 36141261Sdelphij InstrItinData<BrMCRX , [InstrStage<3, [BPU]>]>, 37141261Sdelphij InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>, 38141261Sdelphij InstrItinData<LdStGeneral , [InstrStage<3, [SLU]>]>, 39141261Sdelphij InstrItinData<LdStDSS , [InstrStage<10, [SLU]>]>, 40158795Sdelphij InstrItinData<LdStICBI , [InstrStage<40, [SLU]>]>, 41158795Sdelphij InstrItinData<LdStUX , [InstrStage<4, [SLU]>]>, 42158795Sdelphij InstrItinData<LdStLD , [InstrStage<3, [SLU]>]>, 43141261Sdelphij InstrItinData<LdStLDARX , [InstrStage<11, [SLU]>]>, 44141261Sdelphij InstrItinData<LdStLFD , [InstrStage<3, [SLU]>]>, 45141261Sdelphij InstrItinData<LdStLFDU , [InstrStage<5, [SLU]>]>, 46141261Sdelphij InstrItinData<LdStLHA , [InstrStage<5, [SLU]>]>, 47141261Sdelphij InstrItinData<LdStLMW , [InstrStage<64, [SLU]>]>, 48141261Sdelphij InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>, 49141261Sdelphij InstrItinData<LdStLWA , [InstrStage<5, [SLU]>]>, 50141261Sdelphij InstrItinData<LdStLWARX , [InstrStage<11, [SLU]>]>, 51141261Sdelphij InstrItinData<LdStSLBIA , [InstrStage<40, [SLU]>]>, // needs work 52141261Sdelphij InstrItinData<LdStSLBIE , [InstrStage<2, [SLU]>]>, 53158795Sdelphij InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>, 54158795Sdelphij InstrItinData<LdStSTDCX , [InstrStage<11, [SLU]>]>, 55141261Sdelphij InstrItinData<LdStSTVEBX , [InstrStage<5, [SLU]>]>, 56158795Sdelphij InstrItinData<LdStSTWCX , [InstrStage<11, [SLU]>]>, 57158795Sdelphij InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>, 58158795Sdelphij InstrItinData<SprISYNC , [InstrStage<40, [SLU]>]>, // needs work 59158795Sdelphij InstrItinData<SprMFSR , [InstrStage<3, [SLU]>]>, 60141261Sdelphij InstrItinData<SprMTMSR , [InstrStage<3, [SLU]>]>, 61158795Sdelphij InstrItinData<SprMTSR , [InstrStage<3, [SLU]>]>, 62158795Sdelphij InstrItinData<SprTLBSYNC , [InstrStage<3, [SLU]>]>, 63158795Sdelphij InstrItinData<SprMFCR , [InstrStage<2, [IU2]>]>, 64141261Sdelphij InstrItinData<SprMFMSR , [InstrStage<3, [IU2]>]>, 65158795Sdelphij InstrItinData<SprMFSPR , [InstrStage<3, [IU2]>]>, 66158795Sdelphij InstrItinData<SprMFTB , [InstrStage<10, [IU2]>]>, 67141261Sdelphij InstrItinData<SprMTSPR , [InstrStage<8, [IU2]>]>, 68158795Sdelphij InstrItinData<SprSC , [InstrStage<1, [IU2]>]>, 69158795Sdelphij InstrItinData<FPGeneral , [InstrStage<6, [FPU1, FPU2]>]>, 70158795Sdelphij InstrItinData<FPCompare , [InstrStage<8, [FPU1, FPU2]>]>, 71158795Sdelphij InstrItinData<FPDivD , [InstrStage<33, [FPU1, FPU2]>]>, 72158795Sdelphij InstrItinData<FPDivS , [InstrStage<33, [FPU1, FPU2]>]>, 73158795Sdelphij InstrItinData<FPFused , [InstrStage<6, [FPU1, FPU2]>]>, 74158795Sdelphij InstrItinData<FPRes , [InstrStage<6, [FPU1, FPU2]>]>, 75158795Sdelphij InstrItinData<FPSqrt , [InstrStage<40, [FPU1, FPU2]>]>, 76158795Sdelphij InstrItinData<VecGeneral , [InstrStage<2, [VIU1]>]>, 77158795Sdelphij InstrItinData<VecFP , [InstrStage<8, [VFPU]>]>, 78158795Sdelphij InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>, 79158795Sdelphij InstrItinData<VecComplex , [InstrStage<5, [VIU2]>]>, 80141261Sdelphij InstrItinData<VecPerm , [InstrStage<3, [VPU]>]>, 81158795Sdelphij InstrItinData<VecFPRound , [InstrStage<8, [VFPU]>]>, 82158795Sdelphij InstrItinData<VecVSL , [InstrStage<2, [VIU1]>]>, 83158795Sdelphij InstrItinData<VecVSR , [InstrStage<3, [VPU]>]> 84158795Sdelphij]>; 85158795Sdelphij