1234353Sdim//===-- PPCRegisterInfo.h - PowerPC Register Information Impl ---*- C++ -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed// 10193323Sed// This file contains the PowerPC implementation of the TargetRegisterInfo 11193323Sed// class. 12193323Sed// 13193323Sed//===----------------------------------------------------------------------===// 14193323Sed 15193323Sed#ifndef POWERPC32_REGISTERINFO_H 16193323Sed#define POWERPC32_REGISTERINFO_H 17193323Sed 18249423Sdim#include "llvm/ADT/DenseMap.h" 19193323Sed#include "PPC.h" 20193323Sed 21224145Sdim#define GET_REGINFO_HEADER 22224145Sdim#include "PPCGenRegisterInfo.inc" 23224145Sdim 24193323Sednamespace llvm { 25193323Sedclass PPCSubtarget; 26193323Sedclass TargetInstrInfo; 27193323Sedclass Type; 28193323Sed 29193323Sedclass PPCRegisterInfo : public PPCGenRegisterInfo { 30249423Sdim DenseMap<unsigned, unsigned> ImmToIdxMap; 31193323Sed const PPCSubtarget &Subtarget; 32193323Sedpublic: 33263508Sdim PPCRegisterInfo(const PPCSubtarget &SubTarget); 34193323Sed 35193323Sed /// getPointerRegClass - Return the register class to use to hold pointers. 36193323Sed /// This is used for addressing modes. 37239462Sdim virtual const TargetRegisterClass * 38239462Sdim getPointerRegClass(const MachineFunction &MF, unsigned Kind=0) const; 39193323Sed 40234353Sdim unsigned getRegPressureLimit(const TargetRegisterClass *RC, 41234353Sdim MachineFunction &MF) const; 42234353Sdim 43193323Sed /// Code Generation virtual methods... 44234353Sdim const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const; 45243830Sdim const uint32_t *getCallPreservedMask(CallingConv::ID CC) const; 46249423Sdim const uint32_t *getNoPreservedMask() const; 47193323Sed 48193323Sed BitVector getReservedRegs(const MachineFunction &MF) const; 49193323Sed 50249423Sdim /// We require the register scavenger. 51249423Sdim bool requiresRegisterScavenging(const MachineFunction &MF) const { 52249423Sdim return true; 53249423Sdim } 54239462Sdim 55249423Sdim bool requiresFrameIndexScavenging(const MachineFunction &MF) const { 56249423Sdim return true; 57249423Sdim } 58193323Sed 59249423Sdim bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const { 60249423Sdim return true; 61249423Sdim } 62239462Sdim 63251662Sdim virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const { 64251662Sdim return true; 65251662Sdim } 66251662Sdim 67249423Sdim void lowerDynamicAlloc(MachineBasicBlock::iterator II) const; 68249423Sdim void lowerCRSpilling(MachineBasicBlock::iterator II, 69249423Sdim unsigned FrameIndex) const; 70249423Sdim void lowerCRRestore(MachineBasicBlock::iterator II, 71249423Sdim unsigned FrameIndex) const; 72249423Sdim void lowerVRSAVESpilling(MachineBasicBlock::iterator II, 73249423Sdim unsigned FrameIndex) const; 74249423Sdim void lowerVRSAVERestore(MachineBasicBlock::iterator II, 75249423Sdim unsigned FrameIndex) const; 76193323Sed 77243830Sdim bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg, 78243830Sdim int &FrameIdx) const; 79212904Sdim void eliminateFrameIndex(MachineBasicBlock::iterator II, 80249423Sdim int SPAdj, unsigned FIOperandNum, 81249423Sdim RegScavenger *RS = NULL) const; 82193323Sed 83251662Sdim // Support for virtual base registers. 84251662Sdim bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const; 85251662Sdim void materializeFrameBaseRegister(MachineBasicBlock *MBB, 86251662Sdim unsigned BaseReg, int FrameIdx, 87251662Sdim int64_t Offset) const; 88251662Sdim void resolveFrameIndex(MachineBasicBlock::iterator I, 89251662Sdim unsigned BaseReg, int64_t Offset) const; 90251662Sdim bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const; 91251662Sdim 92193323Sed // Debug information queries. 93199481Srdivacky unsigned getFrameRegister(const MachineFunction &MF) const; 94193323Sed 95263508Sdim // Base pointer (stack realignment) support. 96263508Sdim unsigned getBaseRegister(const MachineFunction &MF) const; 97263508Sdim bool hasBasePointer(const MachineFunction &MF) const; 98263508Sdim bool canRealignStack(const MachineFunction &MF) const; 99263508Sdim bool needsStackRealignment(const MachineFunction &MF) const; 100193323Sed}; 101193323Sed 102193323Sed} // end namespace llvm 103193323Sed 104193323Sed#endif 105