PPCInstr64Bit.td revision 221345
1171169Smlaier//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===// 2171169Smlaier// 3171169Smlaier// The LLVM Compiler Infrastructure 4171169Smlaier// 5171169Smlaier// This file is distributed under the University of Illinois Open Source 6171169Smlaier// License. See LICENSE.TXT for details. 7171169Smlaier// 8171169Smlaier//===----------------------------------------------------------------------===// 9171169Smlaier// 10171169Smlaier// This file describes the PowerPC 64-bit instructions. These patterns are used 11171169Smlaier// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12171169Smlaier// 13171169Smlaier//===----------------------------------------------------------------------===// 14171169Smlaier 15171169Smlaier//===----------------------------------------------------------------------===// 16171169Smlaier// 64-bit operands. 17171169Smlaier// 18171169Smlaierdef s16imm64 : Operand<i64> { 19171169Smlaier let PrintMethod = "printS16ImmOperand"; 20171169Smlaier} 21171169Smlaierdef u16imm64 : Operand<i64> { 22171169Smlaier let PrintMethod = "printU16ImmOperand"; 23171169Smlaier} 24171169Smlaierdef symbolHi64 : Operand<i64> { 25171169Smlaier let PrintMethod = "printSymbolHi"; 26171169Smlaier let EncoderMethod = "getHA16Encoding"; 27171169Smlaier} 28171169Smlaierdef symbolLo64 : Operand<i64> { 29171169Smlaier let PrintMethod = "printSymbolLo"; 30171169Smlaier let EncoderMethod = "getLO16Encoding"; 31171169Smlaier} 32171169Smlaier 33171169Smlaier//===----------------------------------------------------------------------===// 34171169Smlaier// 64-bit transformation functions. 35171169Smlaier// 36171169Smlaier 37171169Smlaierdef SHL64 : SDNodeXForm<imm, [{ 38171169Smlaier // Transformation function: 63 - imm 39171169Smlaier return getI32Imm(63 - N->getZExtValue()); 40171169Smlaier}]>; 41171169Smlaier 42171169Smlaierdef SRL64 : SDNodeXForm<imm, [{ 43171169Smlaier // Transformation function: 64 - imm 44 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 45}]>; 46 47def HI32_48 : SDNodeXForm<imm, [{ 48 // Transformation function: shift the immediate value down into the low bits. 49 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 50}]>; 51 52def HI48_64 : SDNodeXForm<imm, [{ 53 // Transformation function: shift the immediate value down into the low bits. 54 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 55}]>; 56 57 58//===----------------------------------------------------------------------===// 59// Calls. 60// 61 62let Defs = [LR8] in 63 def MovePCtoLR8 : Pseudo<(outs), (ins piclabel:$label), "", []>, 64 PPC970_Unit_BRU; 65 66// Darwin ABI Calls. 67let isCall = 1, PPC970_Unit = 7, 68 // All calls clobber the PPC64 non-callee saved registers. 69 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 70 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 71 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 72 LR8,CTR8, 73 CR0,CR1,CR5,CR6,CR7,CARRY] in { 74 // Convenient aliases for call instructions 75 let Uses = [RM] in { 76 def BL8_Darwin : IForm<18, 0, 1, 77 (outs), (ins calltarget:$func, variable_ops), 78 "bl $func", BrB, []>; // See Pat patterns below. 79 def BLA8_Darwin : IForm<18, 1, 1, 80 (outs), (ins aaddr:$func, variable_ops), 81 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 82 } 83 let Uses = [CTR8, RM] in { 84 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 85 (outs), (ins variable_ops), 86 "bctrl", BrB, 87 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 88 } 89} 90 91// ELF 64 ABI Calls = Darwin ABI Calls 92// Used to define BL8_ELF and BLA8_ELF 93let isCall = 1, PPC970_Unit = 7, 94 // All calls clobber the PPC64 non-callee saved registers. 95 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12, 96 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, 97 V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, 98 LR8,CTR8, 99 CR0,CR1,CR5,CR6,CR7,CARRY] in { 100 // Convenient aliases for call instructions 101 let Uses = [RM] in { 102 def BL8_ELF : IForm<18, 0, 1, 103 (outs), (ins calltarget:$func, variable_ops), 104 "bl $func", BrB, []>; // See Pat patterns below. 105 def BLA8_ELF : IForm<18, 1, 1, 106 (outs), (ins aaddr:$func, variable_ops), 107 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 108 } 109 let Uses = [CTR8, RM] in { 110 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 111 (outs), (ins variable_ops), 112 "bctrl", BrB, 113 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 114 } 115} 116 117 118// Calls 119def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 120 (BL8_Darwin tglobaladdr:$dst)>; 121def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 122 (BL8_Darwin texternalsym:$dst)>; 123 124def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 125 (BL8_ELF tglobaladdr:$dst)>; 126def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 127 (BL8_ELF texternalsym:$dst)>; 128def : Pat<(PPCnop), 129 (NOP)>; 130 131// Atomic operations 132let usesCustomInserter = 1 in { 133 let Defs = [CR0] in { 134 def ATOMIC_LOAD_ADD_I64 : Pseudo< 135 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 136 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 137 def ATOMIC_LOAD_SUB_I64 : Pseudo< 138 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 139 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 140 def ATOMIC_LOAD_OR_I64 : Pseudo< 141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 142 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 143 def ATOMIC_LOAD_XOR_I64 : Pseudo< 144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 145 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 146 def ATOMIC_LOAD_AND_I64 : Pseudo< 147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 148 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 149 def ATOMIC_LOAD_NAND_I64 : Pseudo< 150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 151 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 152 153 def ATOMIC_CMP_SWAP_I64 : Pseudo< 154 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "", 155 [(set G8RC:$dst, 156 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 157 158 def ATOMIC_SWAP_I64 : Pseudo< 159 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "", 160 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 161 } 162} 163 164// Instructions to support atomic operations 165def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 166 "ldarx $rD, $ptr", LdStLDARX, 167 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 168 169let Defs = [CR0] in 170def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 171 "stdcx. $rS, $dst", LdStSTDCX, 172 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 173 isDOT; 174 175let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 176def TCRETURNdi8 :Pseudo< (outs), 177 (ins calltarget:$dst, i32imm:$offset, variable_ops), 178 "#TC_RETURNd8 $dst $offset", 179 []>; 180 181let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 182def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 183 "#TC_RETURNa8 $func $offset", 184 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 185 186let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 187def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops), 188 "#TC_RETURNr8 $dst $offset", 189 []>; 190 191 192let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 193 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR, RM] in 194def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 195 Requires<[In64BitMode]>; 196 197 198 199let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 200 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 201def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 202 "b $dst", BrB, 203 []>; 204 205 206let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 207 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 208def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 209 "ba $dst", BrB, 210 []>; 211 212def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 213 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 214 215def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 216 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 217 218def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 219 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 220 221 222//===----------------------------------------------------------------------===// 223// 64-bit SPR manipulation instrs. 224 225let Uses = [CTR8] in { 226def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 227 "mfctr $rT", SprMFSPR>, 228 PPC970_DGroup_First, PPC970_Unit_FXU; 229} 230let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 231def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 232 "mtctr $rS", SprMTSPR>, 233 PPC970_DGroup_First, PPC970_Unit_FXU; 234} 235 236let Defs = [X1], Uses = [X1] in 237def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"", 238 [(set G8RC:$result, 239 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 240 241let Defs = [LR8] in { 242def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 243 "mtlr $rS", SprMTSPR>, 244 PPC970_DGroup_First, PPC970_Unit_FXU; 245} 246let Uses = [LR8] in { 247def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 248 "mflr $rT", SprMFSPR>, 249 PPC970_DGroup_First, PPC970_Unit_FXU; 250} 251 252//===----------------------------------------------------------------------===// 253// Fixed point instructions. 254// 255 256let PPC970_Unit = 1 in { // FXU Operations. 257 258// Copies, extends, truncates. 259def OR4To8 : XForm_6<31, 444, (outs G8RC:$rA), (ins GPRC:$rS, GPRC:$rB), 260 "or $rA, $rS, $rB", IntGeneral, 261 []>; 262def OR8To4 : XForm_6<31, 444, (outs GPRC:$rA), (ins G8RC:$rS, G8RC:$rB), 263 "or $rA, $rS, $rB", IntGeneral, 264 []>; 265 266def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 267 "li $rD, $imm", IntGeneral, 268 [(set G8RC:$rD, immSExt16:$imm)]>; 269def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 270 "lis $rD, $imm", IntGeneral, 271 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 272 273// Logical ops. 274def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 275 "nand $rA, $rS, $rB", IntGeneral, 276 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 277def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 278 "and $rA, $rS, $rB", IntGeneral, 279 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 280def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 281 "andc $rA, $rS, $rB", IntGeneral, 282 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 283def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 284 "or $rA, $rS, $rB", IntGeneral, 285 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 286def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 287 "nor $rA, $rS, $rB", IntGeneral, 288 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 289def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 290 "orc $rA, $rS, $rB", IntGeneral, 291 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 292def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 293 "eqv $rA, $rS, $rB", IntGeneral, 294 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 295def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 296 "xor $rA, $rS, $rB", IntGeneral, 297 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 298 299// Logical ops with immediate. 300def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 301 "andi. $dst, $src1, $src2", IntGeneral, 302 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 303 isDOT; 304def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 305 "andis. $dst, $src1, $src2", IntGeneral, 306 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 307 isDOT; 308def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 309 "ori $dst, $src1, $src2", IntGeneral, 310 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 311def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 312 "oris $dst, $src1, $src2", IntGeneral, 313 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 314def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 315 "xori $dst, $src1, $src2", IntGeneral, 316 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 317def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 318 "xoris $dst, $src1, $src2", IntGeneral, 319 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 320 321def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 322 "add $rT, $rA, $rB", IntGeneral, 323 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 324 325let Defs = [CARRY] in { 326def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 327 "addc $rT, $rA, $rB", IntGeneral, 328 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 329 PPC970_DGroup_Cracked; 330def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 331 "addic $rD, $rA, $imm", IntGeneral, 332 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 333} 334def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 335 "addi $rD, $rA, $imm", IntGeneral, 336 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 337def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 338 "addis $rD, $rA, $imm", IntGeneral, 339 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 340 341let Defs = [CARRY] in { 342def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 343 "subfic $rD, $rA, $imm", IntGeneral, 344 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 345def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 346 "subfc $rT, $rA, $rB", IntGeneral, 347 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 348 PPC970_DGroup_Cracked; 349} 350def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 351 "subf $rT, $rA, $rB", IntGeneral, 352 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 353def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 354 "neg $rT, $rA", IntGeneral, 355 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 356let Uses = [CARRY], Defs = [CARRY] in { 357def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 358 "adde $rT, $rA, $rB", IntGeneral, 359 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 360def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 361 "addme $rT, $rA", IntGeneral, 362 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 363def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 364 "addze $rT, $rA", IntGeneral, 365 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 366def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 367 "subfe $rT, $rA, $rB", IntGeneral, 368 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 369def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 370 "subfme $rT, $rA", IntGeneral, 371 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 372def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 373 "subfze $rT, $rA", IntGeneral, 374 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 375} 376 377 378def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 379 "mulhd $rT, $rA, $rB", IntMulHW, 380 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 381def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 382 "mulhdu $rT, $rA, $rB", IntMulHWU, 383 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 384 385def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 386 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 387def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 388 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 389def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 390 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 391def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 392 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 393 394def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 395 "sld $rA, $rS, $rB", IntRotateD, 396 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 397def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 398 "srd $rA, $rS, $rB", IntRotateD, 399 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 400let Defs = [CARRY] in { 401def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 402 "srad $rA, $rS, $rB", IntRotateD, 403 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 404} 405 406def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 407 "extsb $rA, $rS", IntGeneral, 408 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 409def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 410 "extsh $rA, $rS", IntGeneral, 411 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 412 413def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 414 "extsw $rA, $rS", IntGeneral, 415 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 416/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 417def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 418 "extsw $rA, $rS", IntGeneral, 419 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 420def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 421 "extsw $rA, $rS", IntGeneral, 422 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 423 424let Defs = [CARRY] in { 425def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 426 "sradi $rA, $rS, $SH", IntRotateD, 427 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 428} 429def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 430 "cntlzd $rA, $rS", IntGeneral, 431 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 432 433def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 434 "divd $rT, $rA, $rB", IntDivD, 435 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 436 PPC970_DGroup_First, PPC970_DGroup_Cracked; 437def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 438 "divdu $rT, $rA, $rB", IntDivD, 439 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 440 PPC970_DGroup_First, PPC970_DGroup_Cracked; 441def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 442 "mulld $rT, $rA, $rB", IntMulHD, 443 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 444 445 446let isCommutable = 1 in { 447def RLDIMI : MDForm_1<30, 3, 448 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 449 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 450 []>, isPPC64, RegConstraint<"$rSi = $rA">, 451 NoEncode<"$rSi">; 452} 453 454// Rotate instructions. 455def RLDCL : MDForm_1<30, 0, 456 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB), 457 "rldcl $rA, $rS, $rB, $MB", IntRotateD, 458 []>, isPPC64; 459def RLDICL : MDForm_1<30, 0, 460 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), 461 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 462 []>, isPPC64; 463def RLDICR : MDForm_1<30, 1, 464 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), 465 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 466 []>, isPPC64; 467} // End FXU Operations. 468 469 470//===----------------------------------------------------------------------===// 471// Load/Store instructions. 472// 473 474 475// Sign extending loads. 476let canFoldAsLoad = 1, PPC970_Unit = 2 in { 477def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 478 "lha $rD, $src", LdStLHA, 479 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 480 PPC970_DGroup_Cracked; 481def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 482 "lwa $rD, $src", LdStLWA, 483 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 484 PPC970_DGroup_Cracked; 485def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 486 "lhax $rD, $src", LdStLHA, 487 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 488 PPC970_DGroup_Cracked; 489def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 490 "lwax $rD, $src", LdStLHA, 491 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 492 PPC970_DGroup_Cracked; 493 494// Update forms. 495let mayLoad = 1 in 496def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 497 ptr_rc:$rA), 498 "lhau $rD, $disp($rA)", LdStGeneral, 499 []>, RegConstraint<"$rA = $ea_result">, 500 NoEncode<"$ea_result">; 501// NO LWAU! 502 503} 504 505// Zero extending loads. 506let canFoldAsLoad = 1, PPC970_Unit = 2 in { 507def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 508 "lbz $rD, $src", LdStGeneral, 509 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 510def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 511 "lhz $rD, $src", LdStGeneral, 512 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 513def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 514 "lwz $rD, $src", LdStGeneral, 515 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 516 517def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 518 "lbzx $rD, $src", LdStGeneral, 519 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 520def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 521 "lhzx $rD, $src", LdStGeneral, 522 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 523def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 524 "lwzx $rD, $src", LdStGeneral, 525 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 526 527 528// Update forms. 529let mayLoad = 1 in { 530def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 531 "lbzu $rD, $addr", LdStGeneral, 532 []>, RegConstraint<"$addr.reg = $ea_result">, 533 NoEncode<"$ea_result">; 534def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 535 "lhzu $rD, $addr", LdStGeneral, 536 []>, RegConstraint<"$addr.reg = $ea_result">, 537 NoEncode<"$ea_result">; 538def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 539 "lwzu $rD, $addr", LdStGeneral, 540 []>, RegConstraint<"$addr.reg = $ea_result">, 541 NoEncode<"$ea_result">; 542} 543} 544 545 546// Full 8-byte loads. 547let canFoldAsLoad = 1, PPC970_Unit = 2 in { 548def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 549 "ld $rD, $src", LdStLD, 550 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 551def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 552 "", 553 [(set G8RC:$rD, 554 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 555 556let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 557def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg), 558 "ld 2, 8($reg)", LdStLD, 559 [(PPCload_toc G8RC:$reg)]>, isPPC64; 560 561let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 562def LDtoc_restore : DSForm_1<58, 0, (outs), (ins), 563 "ld 2, 40(1)", LdStLD, 564 [(PPCtoc_restore)]>, isPPC64; 565def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 566 "ldx $rD, $src", LdStLD, 567 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 568 569let mayLoad = 1 in 570def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 571 "ldu $rD, $addr", LdStLD, 572 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 573 NoEncode<"$ea_result">; 574 575} 576 577def : Pat<(PPCload ixaddr:$src), 578 (LD ixaddr:$src)>; 579def : Pat<(PPCload xaddr:$src), 580 (LDX xaddr:$src)>; 581 582let PPC970_Unit = 2 in { 583// Truncating stores. 584def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 585 "stb $rS, $src", LdStGeneral, 586 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 587def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 588 "sth $rS, $src", LdStGeneral, 589 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 590def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 591 "stw $rS, $src", LdStGeneral, 592 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 593def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 594 "stbx $rS, $dst", LdStGeneral, 595 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 596 PPC970_DGroup_Cracked; 597def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 598 "sthx $rS, $dst", LdStGeneral, 599 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 600 PPC970_DGroup_Cracked; 601def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 602 "stwx $rS, $dst", LdStGeneral, 603 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 604 PPC970_DGroup_Cracked; 605// Normal 8-byte stores. 606def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 607 "std $rS, $dst", LdStSTD, 608 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 609def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 610 "stdx $rS, $dst", LdStSTD, 611 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 612 PPC970_DGroup_Cracked; 613} 614 615let PPC970_Unit = 2 in { 616 617def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 618 symbolLo:$ptroff, ptr_rc:$ptrreg), 619 "stbu $rS, $ptroff($ptrreg)", LdStGeneral, 620 [(set ptr_rc:$ea_res, 621 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 622 iaddroff:$ptroff))]>, 623 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 624def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 625 symbolLo:$ptroff, ptr_rc:$ptrreg), 626 "sthu $rS, $ptroff($ptrreg)", LdStGeneral, 627 [(set ptr_rc:$ea_res, 628 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 629 iaddroff:$ptroff))]>, 630 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 631 632def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 633 s16immX4:$ptroff, ptr_rc:$ptrreg), 634 "stdu $rS, $ptroff($ptrreg)", LdStSTD, 635 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 636 iaddroff:$ptroff))]>, 637 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 638 isPPC64; 639 640let mayStore = 1 in 641def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst), 642 "stdux $rS, $dst", LdStSTD, 643 []>, isPPC64; 644 645// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 646def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 647 "std $rT, $dst", LdStSTD, 648 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 649def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 650 "stdx $rT, $dst", LdStSTD, 651 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 652 PPC970_DGroup_Cracked; 653} 654 655 656 657//===----------------------------------------------------------------------===// 658// Floating point instructions. 659// 660 661 662let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 663def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 664 "fcfid $frD, $frB", FPGeneral, 665 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 666def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 667 "fctidz $frD, $frB", FPGeneral, 668 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 669} 670 671 672//===----------------------------------------------------------------------===// 673// Instruction Patterns 674// 675 676// Extensions and truncates to/from 32-bit regs. 677def : Pat<(i64 (zext GPRC:$in)), 678 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 679def : Pat<(i64 (anyext GPRC:$in)), 680 (OR4To8 GPRC:$in, GPRC:$in)>; 681def : Pat<(i32 (trunc G8RC:$in)), 682 (OR8To4 G8RC:$in, G8RC:$in)>; 683 684// Extending loads with i64 targets. 685def : Pat<(zextloadi1 iaddr:$src), 686 (LBZ8 iaddr:$src)>; 687def : Pat<(zextloadi1 xaddr:$src), 688 (LBZX8 xaddr:$src)>; 689def : Pat<(extloadi1 iaddr:$src), 690 (LBZ8 iaddr:$src)>; 691def : Pat<(extloadi1 xaddr:$src), 692 (LBZX8 xaddr:$src)>; 693def : Pat<(extloadi8 iaddr:$src), 694 (LBZ8 iaddr:$src)>; 695def : Pat<(extloadi8 xaddr:$src), 696 (LBZX8 xaddr:$src)>; 697def : Pat<(extloadi16 iaddr:$src), 698 (LHZ8 iaddr:$src)>; 699def : Pat<(extloadi16 xaddr:$src), 700 (LHZX8 xaddr:$src)>; 701def : Pat<(extloadi32 iaddr:$src), 702 (LWZ8 iaddr:$src)>; 703def : Pat<(extloadi32 xaddr:$src), 704 (LWZX8 xaddr:$src)>; 705 706// Standard shifts. These are represented separately from the real shifts above 707// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 708// amounts. 709def : Pat<(sra G8RC:$rS, GPRC:$rB), 710 (SRAD G8RC:$rS, GPRC:$rB)>; 711def : Pat<(srl G8RC:$rS, GPRC:$rB), 712 (SRD G8RC:$rS, GPRC:$rB)>; 713def : Pat<(shl G8RC:$rS, GPRC:$rB), 714 (SLD G8RC:$rS, GPRC:$rB)>; 715 716// SHL/SRL 717def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 718 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 719def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 720 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 721 722// ROTL 723def : Pat<(rotl G8RC:$in, GPRC:$sh), 724 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 725def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 726 (RLDICL G8RC:$in, imm:$imm, 0)>; 727 728// Hi and Lo for Darwin Global Addresses. 729def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 730def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 731def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 732def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 733def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 734def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 735def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 736def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 737def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 738 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 739def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 740 (ADDIS8 G8RC:$in, tconstpool:$g)>; 741def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 742 (ADDIS8 G8RC:$in, tjumptable:$g)>; 743def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 744 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 745