PPCFrameLowering.cpp revision 249423
1234353Sdim//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2218885Sdim// 3218885Sdim// The LLVM Compiler Infrastructure 4218885Sdim// 5218885Sdim// This file is distributed under the University of Illinois Open Source 6218885Sdim// License. See LICENSE.TXT for details. 7218885Sdim// 8218885Sdim//===----------------------------------------------------------------------===// 9218885Sdim// 10218885Sdim// This file contains the PPC implementation of TargetFrameLowering class. 11218885Sdim// 12218885Sdim//===----------------------------------------------------------------------===// 13218885Sdim 14218885Sdim#include "PPCFrameLowering.h" 15249423Sdim#include "PPCInstrBuilder.h" 16218885Sdim#include "PPCInstrInfo.h" 17218885Sdim#include "PPCMachineFunctionInfo.h" 18218885Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 19218885Sdim#include "llvm/CodeGen/MachineFunction.h" 20218885Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 21218885Sdim#include "llvm/CodeGen/MachineModuleInfo.h" 22218885Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 23218885Sdim#include "llvm/CodeGen/RegisterScavenging.h" 24249423Sdim#include "llvm/IR/Function.h" 25218885Sdim#include "llvm/Target/TargetOptions.h" 26218885Sdim 27218885Sdimusing namespace llvm; 28218885Sdim 29218885Sdim// FIXME This disables some code that aligns the stack to a boundary bigger than 30218885Sdim// the default (16 bytes on Darwin) when there is a stack local of greater 31218885Sdim// alignment. This does not currently work, because the delta between old and 32218885Sdim// new stack pointers is added to offsets that reference incoming parameters 33218885Sdim// after the prolog is generated, and the code that does that doesn't handle a 34218885Sdim// variable delta. You don't want to do that anyway; a better approach is to 35218885Sdim// reserve another register that retains to the incoming stack pointer, and 36218885Sdim// reference parameters relative to that. 37218885Sdim#define ALIGN_STACK 0 38218885Sdim 39218885Sdim 40218885Sdim/// VRRegNo - Map from a numbered VR register to its enum value. 41218885Sdim/// 42234353Sdimstatic const uint16_t VRRegNo[] = { 43218885Sdim PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 44218885Sdim PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 45218885Sdim PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 46218885Sdim PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 47218885Sdim}; 48218885Sdim 49218885Sdim/// RemoveVRSaveCode - We have found that this function does not need any code 50218885Sdim/// to manipulate the VRSAVE register, even though it uses vector registers. 51218885Sdim/// This can happen when the only registers used are known to be live in or out 52218885Sdim/// of the function. Remove all of the VRSAVE related code from the function. 53243830Sdim/// FIXME: The removal of the code results in a compile failure at -O0 when the 54243830Sdim/// function contains a function call, as the GPR containing original VRSAVE 55243830Sdim/// contents is spilled and reloaded around the call. Without the prolog code, 56243830Sdim/// the spill instruction refers to an undefined register. This code needs 57243830Sdim/// to account for all uses of that GPR. 58218885Sdimstatic void RemoveVRSaveCode(MachineInstr *MI) { 59218885Sdim MachineBasicBlock *Entry = MI->getParent(); 60218885Sdim MachineFunction *MF = Entry->getParent(); 61218885Sdim 62218885Sdim // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 63218885Sdim MachineBasicBlock::iterator MBBI = MI; 64218885Sdim ++MBBI; 65218885Sdim assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 66218885Sdim MBBI->eraseFromParent(); 67218885Sdim 68218885Sdim bool RemovedAllMTVRSAVEs = true; 69218885Sdim // See if we can find and remove the MTVRSAVE instruction from all of the 70218885Sdim // epilog blocks. 71218885Sdim for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 72218885Sdim // If last instruction is a return instruction, add an epilogue 73234353Sdim if (!I->empty() && I->back().isReturn()) { 74218885Sdim bool FoundIt = false; 75218885Sdim for (MBBI = I->end(); MBBI != I->begin(); ) { 76218885Sdim --MBBI; 77218885Sdim if (MBBI->getOpcode() == PPC::MTVRSAVE) { 78218885Sdim MBBI->eraseFromParent(); // remove it. 79218885Sdim FoundIt = true; 80218885Sdim break; 81218885Sdim } 82218885Sdim } 83218885Sdim RemovedAllMTVRSAVEs &= FoundIt; 84218885Sdim } 85218885Sdim } 86218885Sdim 87218885Sdim // If we found and removed all MTVRSAVE instructions, remove the read of 88218885Sdim // VRSAVE as well. 89218885Sdim if (RemovedAllMTVRSAVEs) { 90218885Sdim MBBI = MI; 91218885Sdim assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 92218885Sdim --MBBI; 93218885Sdim assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 94218885Sdim MBBI->eraseFromParent(); 95218885Sdim } 96218885Sdim 97218885Sdim // Finally, nuke the UPDATE_VRSAVE. 98218885Sdim MI->eraseFromParent(); 99218885Sdim} 100218885Sdim 101218885Sdim// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 102218885Sdim// instruction selector. Based on the vector registers that have been used, 103218885Sdim// transform this into the appropriate ORI instruction. 104218885Sdimstatic void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 105218885Sdim MachineFunction *MF = MI->getParent()->getParent(); 106249423Sdim const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo(); 107218885Sdim DebugLoc dl = MI->getDebugLoc(); 108218885Sdim 109218885Sdim unsigned UsedRegMask = 0; 110218885Sdim for (unsigned i = 0; i != 32; ++i) 111218885Sdim if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 112218885Sdim UsedRegMask |= 1 << (31-i); 113218885Sdim 114218885Sdim // Live in and live out values already must be in the mask, so don't bother 115218885Sdim // marking them. 116218885Sdim for (MachineRegisterInfo::livein_iterator 117218885Sdim I = MF->getRegInfo().livein_begin(), 118218885Sdim E = MF->getRegInfo().livein_end(); I != E; ++I) { 119249423Sdim unsigned RegNo = TRI->getEncodingValue(I->first); 120218885Sdim if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 121218885Sdim UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 122218885Sdim } 123249423Sdim 124249423Sdim // Live out registers appear as use operands on return instructions. 125249423Sdim for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end(); 126249423Sdim UsedRegMask != 0 && BI != BE; ++BI) { 127249423Sdim const MachineBasicBlock &MBB = *BI; 128249423Sdim if (MBB.empty() || !MBB.back().isReturn()) 129249423Sdim continue; 130249423Sdim const MachineInstr &Ret = MBB.back(); 131249423Sdim for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) { 132249423Sdim const MachineOperand &MO = Ret.getOperand(I); 133249423Sdim if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg())) 134249423Sdim continue; 135249423Sdim unsigned RegNo = TRI->getEncodingValue(MO.getReg()); 136249423Sdim UsedRegMask &= ~(1 << (31-RegNo)); 137249423Sdim } 138218885Sdim } 139218885Sdim 140218885Sdim // If no registers are used, turn this into a copy. 141218885Sdim if (UsedRegMask == 0) { 142218885Sdim // Remove all VRSAVE code. 143218885Sdim RemoveVRSaveCode(MI); 144218885Sdim return; 145218885Sdim } 146218885Sdim 147218885Sdim unsigned SrcReg = MI->getOperand(1).getReg(); 148218885Sdim unsigned DstReg = MI->getOperand(0).getReg(); 149218885Sdim 150218885Sdim if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 151218885Sdim if (DstReg != SrcReg) 152218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 153218885Sdim .addReg(SrcReg) 154218885Sdim .addImm(UsedRegMask); 155218885Sdim else 156218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 157218885Sdim .addReg(SrcReg, RegState::Kill) 158218885Sdim .addImm(UsedRegMask); 159218885Sdim } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 160218885Sdim if (DstReg != SrcReg) 161218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 162218885Sdim .addReg(SrcReg) 163218885Sdim .addImm(UsedRegMask >> 16); 164218885Sdim else 165218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 166218885Sdim .addReg(SrcReg, RegState::Kill) 167218885Sdim .addImm(UsedRegMask >> 16); 168218885Sdim } else { 169218885Sdim if (DstReg != SrcReg) 170218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 171218885Sdim .addReg(SrcReg) 172218885Sdim .addImm(UsedRegMask >> 16); 173218885Sdim else 174218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 175218885Sdim .addReg(SrcReg, RegState::Kill) 176218885Sdim .addImm(UsedRegMask >> 16); 177218885Sdim 178218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 179218885Sdim .addReg(DstReg, RegState::Kill) 180218885Sdim .addImm(UsedRegMask & 0xFFFF); 181218885Sdim } 182218885Sdim 183218885Sdim // Remove the old UPDATE_VRSAVE instruction. 184218885Sdim MI->eraseFromParent(); 185218885Sdim} 186218885Sdim 187243830Sdimstatic bool spillsCR(const MachineFunction &MF) { 188243830Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 189243830Sdim return FuncInfo->isCRSpilled(); 190243830Sdim} 191243830Sdim 192249423Sdimstatic bool spillsVRSAVE(const MachineFunction &MF) { 193249423Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 194249423Sdim return FuncInfo->isVRSAVESpilled(); 195249423Sdim} 196249423Sdim 197249423Sdimstatic bool hasSpills(const MachineFunction &MF) { 198249423Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 199249423Sdim return FuncInfo->hasSpills(); 200249423Sdim} 201249423Sdim 202249423Sdimstatic bool hasNonRISpills(const MachineFunction &MF) { 203249423Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 204249423Sdim return FuncInfo->hasNonRISpills(); 205249423Sdim} 206249423Sdim 207218885Sdim/// determineFrameLayout - Determine the size of the frame and maximum call 208218885Sdim/// frame size. 209249423Sdimunsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF, 210249423Sdim bool UpdateMF, 211249423Sdim bool UseEstimate) const { 212218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 213218885Sdim 214218885Sdim // Get the number of bytes to allocate from the FrameInfo 215249423Sdim unsigned FrameSize = 216249423Sdim UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize(); 217218885Sdim 218218885Sdim // Get the alignments provided by the target, and the maximum alignment 219218885Sdim // (if any) of the fixed frame objects. 220218885Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 221218885Sdim unsigned TargetAlign = getStackAlignment(); 222218885Sdim unsigned AlignMask = TargetAlign - 1; // 223218885Sdim 224218885Sdim // If we are a leaf function, and use up to 224 bytes of stack space, 225218885Sdim // don't have a frame pointer, calls, or dynamic alloca then we do not need 226243830Sdim // to adjust the stack pointer (we fit in the Red Zone). For 64-bit 227243830Sdim // SVR4, we also require a stack frame if we need to spill the CR, 228243830Sdim // since this spill area is addressed relative to the stack pointer. 229249423Sdim // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate 230249423Sdim // stackless code if all local vars are reg-allocated. 231249423Sdim bool DisableRedZone = MF.getFunction()->getAttributes(). 232249423Sdim hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone); 233218885Sdim if (!DisableRedZone && 234249423Sdim (Subtarget.isPPC64() || // 32-bit SVR4, no stack- 235249423Sdim !Subtarget.isSVR4ABI() || // allocated locals. 236249423Sdim FrameSize == 0) && 237218885Sdim FrameSize <= 224 && // Fits in red zone. 238218885Sdim !MFI->hasVarSizedObjects() && // No dynamic alloca. 239218885Sdim !MFI->adjustsStack() && // No calls. 240243830Sdim !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave. 241243830Sdim Subtarget.isSVR4ABI() 242243830Sdim && spillsCR(MF)) && 243218885Sdim (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 244218885Sdim // No need for frame 245249423Sdim if (UpdateMF) 246249423Sdim MFI->setStackSize(0); 247249423Sdim return 0; 248218885Sdim } 249218885Sdim 250218885Sdim // Get the maximum call frame size of all the calls. 251218885Sdim unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 252218885Sdim 253218885Sdim // Maximum call frame needs to be at least big enough for linkage and 8 args. 254218885Sdim unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 255218885Sdim Subtarget.isDarwinABI()); 256218885Sdim maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 257218885Sdim 258218885Sdim // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 259218885Sdim // that allocations will be aligned. 260218885Sdim if (MFI->hasVarSizedObjects()) 261218885Sdim maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 262218885Sdim 263218885Sdim // Update maximum call frame size. 264249423Sdim if (UpdateMF) 265249423Sdim MFI->setMaxCallFrameSize(maxCallFrameSize); 266218885Sdim 267218885Sdim // Include call frame size in total. 268218885Sdim FrameSize += maxCallFrameSize; 269218885Sdim 270218885Sdim // Make sure the frame is aligned. 271218885Sdim FrameSize = (FrameSize + AlignMask) & ~AlignMask; 272218885Sdim 273218885Sdim // Update frame info. 274249423Sdim if (UpdateMF) 275249423Sdim MFI->setStackSize(FrameSize); 276249423Sdim 277249423Sdim return FrameSize; 278218885Sdim} 279218885Sdim 280218885Sdim// hasFP - Return true if the specified function actually has a dedicated frame 281218885Sdim// pointer register. 282218885Sdimbool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 283218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 284218885Sdim // FIXME: This is pretty much broken by design: hasFP() might be called really 285218885Sdim // early, before the stack layout was calculated and thus hasFP() might return 286218885Sdim // true or false here depending on the time of call. 287218885Sdim return (MFI->getStackSize()) && needsFP(MF); 288218885Sdim} 289218885Sdim 290218885Sdim// needsFP - Return true if the specified function should have a dedicated frame 291218885Sdim// pointer register. This is true if the function has variable sized allocas or 292218885Sdim// if frame pointer elimination is disabled. 293218885Sdimbool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 294218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 295218885Sdim 296218885Sdim // Naked functions have no stack frame pushed, so we don't have a frame 297218885Sdim // pointer. 298249423Sdim if (MF.getFunction()->getAttributes().hasAttribute(AttributeSet::FunctionIndex, 299249423Sdim Attribute::Naked)) 300218885Sdim return false; 301218885Sdim 302234353Sdim return MF.getTarget().Options.DisableFramePointerElim(MF) || 303234353Sdim MFI->hasVarSizedObjects() || 304234353Sdim (MF.getTarget().Options.GuaranteedTailCallOpt && 305234353Sdim MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 306218885Sdim} 307218885Sdim 308249423Sdimvoid PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const { 309249423Sdim bool is31 = needsFP(MF); 310249423Sdim unsigned FPReg = is31 ? PPC::R31 : PPC::R1; 311249423Sdim unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1; 312218885Sdim 313249423Sdim for (MachineFunction::iterator BI = MF.begin(), BE = MF.end(); 314249423Sdim BI != BE; ++BI) 315249423Sdim for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) { 316249423Sdim --MBBI; 317249423Sdim for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) { 318249423Sdim MachineOperand &MO = MBBI->getOperand(I); 319249423Sdim if (!MO.isReg()) 320249423Sdim continue; 321249423Sdim 322249423Sdim switch (MO.getReg()) { 323249423Sdim case PPC::FP: 324249423Sdim MO.setReg(FPReg); 325249423Sdim break; 326249423Sdim case PPC::FP8: 327249423Sdim MO.setReg(FP8Reg); 328249423Sdim break; 329249423Sdim } 330249423Sdim } 331249423Sdim } 332249423Sdim} 333249423Sdim 334218885Sdimvoid PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 335218885Sdim MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 336218885Sdim MachineBasicBlock::iterator MBBI = MBB.begin(); 337218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 338218885Sdim const PPCInstrInfo &TII = 339218885Sdim *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 340218885Sdim 341218885Sdim MachineModuleInfo &MMI = MF.getMMI(); 342218885Sdim DebugLoc dl; 343218885Sdim bool needsFrameMoves = MMI.hasDebugInfo() || 344223017Sdim MF.getFunction()->needsUnwindTableEntry(); 345218885Sdim 346218885Sdim // Prepare for frame info. 347218885Sdim MCSymbol *FrameLabel = 0; 348218885Sdim 349218885Sdim // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 350218885Sdim // process it. 351243830Sdim if (!Subtarget.isSVR4ABI()) 352243830Sdim for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 353243830Sdim if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 354243830Sdim HandleVRSaveUpdate(MBBI, TII); 355243830Sdim break; 356243830Sdim } 357218885Sdim } 358218885Sdim 359218885Sdim // Move MBBI back to the beginning of the function. 360218885Sdim MBBI = MBB.begin(); 361218885Sdim 362218885Sdim // Work out frame sizes. 363249423Sdim unsigned FrameSize = determineFrameLayout(MF); 364218885Sdim int NegFrameSize = -FrameSize; 365218885Sdim 366249423Sdim if (MFI->isFrameAddressTaken()) 367249423Sdim replaceFPWithRealFP(MF); 368249423Sdim 369218885Sdim // Get processor type. 370218885Sdim bool isPPC64 = Subtarget.isPPC64(); 371218885Sdim // Get operating system 372218885Sdim bool isDarwinABI = Subtarget.isDarwinABI(); 373218885Sdim // Check if the link register (LR) must be saved. 374218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 375218885Sdim bool MustSaveLR = FI->mustSaveLR(); 376218885Sdim // Do we have a frame pointer for this function? 377218885Sdim bool HasFP = hasFP(MF); 378218885Sdim 379218885Sdim int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 380218885Sdim 381218885Sdim int FPOffset = 0; 382218885Sdim if (HasFP) { 383218885Sdim if (Subtarget.isSVR4ABI()) { 384218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 385218885Sdim int FPIndex = FI->getFramePointerSaveIndex(); 386218885Sdim assert(FPIndex && "No Frame Pointer Save Slot!"); 387218885Sdim FPOffset = FFI->getObjectOffset(FPIndex); 388218885Sdim } else { 389218885Sdim FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 390218885Sdim } 391218885Sdim } 392218885Sdim 393218885Sdim if (isPPC64) { 394218885Sdim if (MustSaveLR) 395218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 396218885Sdim 397218885Sdim if (HasFP) 398218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 399218885Sdim .addReg(PPC::X31) 400218885Sdim .addImm(FPOffset/4) 401218885Sdim .addReg(PPC::X1); 402218885Sdim 403218885Sdim if (MustSaveLR) 404218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 405218885Sdim .addReg(PPC::X0) 406218885Sdim .addImm(LROffset / 4) 407218885Sdim .addReg(PPC::X1); 408218885Sdim } else { 409218885Sdim if (MustSaveLR) 410218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 411218885Sdim 412218885Sdim if (HasFP) 413239462Sdim // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative 414239462Sdim // offsets of R1 is not allowed. 415218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 416218885Sdim .addReg(PPC::R31) 417218885Sdim .addImm(FPOffset) 418218885Sdim .addReg(PPC::R1); 419218885Sdim 420218885Sdim if (MustSaveLR) 421218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 422218885Sdim .addReg(PPC::R0) 423218885Sdim .addImm(LROffset) 424218885Sdim .addReg(PPC::R1); 425218885Sdim } 426218885Sdim 427218885Sdim // Skip if a leaf routine. 428218885Sdim if (!FrameSize) return; 429218885Sdim 430218885Sdim // Get stack alignments. 431218885Sdim unsigned TargetAlign = getStackAlignment(); 432218885Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 433218885Sdim 434218885Sdim // Adjust stack pointer: r1 += NegFrameSize. 435218885Sdim // If there is a preferred stack alignment, align R1 now 436218885Sdim if (!isPPC64) { 437218885Sdim // PPC32. 438218885Sdim if (ALIGN_STACK && MaxAlign > TargetAlign) { 439218885Sdim assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 440218885Sdim "Invalid alignment!"); 441218885Sdim assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 442218885Sdim 443218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 444218885Sdim .addReg(PPC::R1) 445218885Sdim .addImm(0) 446218885Sdim .addImm(32 - Log2_32(MaxAlign)) 447218885Sdim .addImm(31); 448218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 449218885Sdim .addReg(PPC::R0, RegState::Kill) 450218885Sdim .addImm(NegFrameSize); 451239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 452234353Sdim .addReg(PPC::R1, RegState::Kill) 453239462Sdim .addReg(PPC::R1) 454218885Sdim .addReg(PPC::R0); 455218885Sdim } else if (isInt<16>(NegFrameSize)) { 456218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 457218885Sdim .addReg(PPC::R1) 458218885Sdim .addImm(NegFrameSize) 459218885Sdim .addReg(PPC::R1); 460218885Sdim } else { 461218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 462218885Sdim .addImm(NegFrameSize >> 16); 463218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 464218885Sdim .addReg(PPC::R0, RegState::Kill) 465218885Sdim .addImm(NegFrameSize & 0xFFFF); 466239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 467234353Sdim .addReg(PPC::R1, RegState::Kill) 468239462Sdim .addReg(PPC::R1) 469218885Sdim .addReg(PPC::R0); 470218885Sdim } 471218885Sdim } else { // PPC64. 472218885Sdim if (ALIGN_STACK && MaxAlign > TargetAlign) { 473218885Sdim assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 474218885Sdim "Invalid alignment!"); 475218885Sdim assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 476218885Sdim 477218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 478218885Sdim .addReg(PPC::X1) 479218885Sdim .addImm(0) 480218885Sdim .addImm(64 - Log2_32(MaxAlign)); 481218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 482218885Sdim .addReg(PPC::X0) 483218885Sdim .addImm(NegFrameSize); 484239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 485234353Sdim .addReg(PPC::X1, RegState::Kill) 486239462Sdim .addReg(PPC::X1) 487218885Sdim .addReg(PPC::X0); 488218885Sdim } else if (isInt<16>(NegFrameSize)) { 489218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 490218885Sdim .addReg(PPC::X1) 491218885Sdim .addImm(NegFrameSize / 4) 492218885Sdim .addReg(PPC::X1); 493218885Sdim } else { 494218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 495218885Sdim .addImm(NegFrameSize >> 16); 496218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 497218885Sdim .addReg(PPC::X0, RegState::Kill) 498218885Sdim .addImm(NegFrameSize & 0xFFFF); 499239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 500234353Sdim .addReg(PPC::X1, RegState::Kill) 501239462Sdim .addReg(PPC::X1) 502218885Sdim .addReg(PPC::X0); 503218885Sdim } 504218885Sdim } 505218885Sdim 506218885Sdim std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 507218885Sdim 508218885Sdim // Add the "machine moves" for the instructions we generated above, but in 509218885Sdim // reverse order. 510218885Sdim if (needsFrameMoves) { 511218885Sdim // Mark effective beginning of when frame pointer becomes valid. 512218885Sdim FrameLabel = MMI.getContext().CreateTempSymbol(); 513218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 514218885Sdim 515218885Sdim // Show update of SP. 516218885Sdim if (NegFrameSize) { 517218885Sdim MachineLocation SPDst(MachineLocation::VirtualFP); 518218885Sdim MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 519218885Sdim Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 520218885Sdim } else { 521218885Sdim MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 522218885Sdim Moves.push_back(MachineMove(FrameLabel, SP, SP)); 523218885Sdim } 524218885Sdim 525218885Sdim if (HasFP) { 526218885Sdim MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 527218885Sdim MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 528218885Sdim Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 529218885Sdim } 530218885Sdim 531218885Sdim if (MustSaveLR) { 532218885Sdim MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 533218885Sdim MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 534218885Sdim Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 535218885Sdim } 536218885Sdim } 537218885Sdim 538218885Sdim MCSymbol *ReadyLabel = 0; 539218885Sdim 540218885Sdim // If there is a frame pointer, copy R1 into R31 541218885Sdim if (HasFP) { 542218885Sdim if (!isPPC64) { 543218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 544218885Sdim .addReg(PPC::R1) 545218885Sdim .addReg(PPC::R1); 546218885Sdim } else { 547218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 548218885Sdim .addReg(PPC::X1) 549218885Sdim .addReg(PPC::X1); 550218885Sdim } 551218885Sdim 552218885Sdim if (needsFrameMoves) { 553218885Sdim ReadyLabel = MMI.getContext().CreateTempSymbol(); 554218885Sdim 555218885Sdim // Mark effective beginning of when frame pointer is ready. 556218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 557218885Sdim 558218885Sdim MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 559218885Sdim (isPPC64 ? PPC::X1 : PPC::R1)); 560218885Sdim MachineLocation FPSrc(MachineLocation::VirtualFP); 561218885Sdim Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 562218885Sdim } 563218885Sdim } 564218885Sdim 565218885Sdim if (needsFrameMoves) { 566218885Sdim MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 567218885Sdim 568218885Sdim // Add callee saved registers to move list. 569218885Sdim const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 570218885Sdim for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 571218885Sdim unsigned Reg = CSI[I].getReg(); 572218885Sdim if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 573223017Sdim 574223017Sdim // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 575223017Sdim // subregisters of CR2. We just need to emit a move of CR2. 576239462Sdim if (PPC::CRBITRCRegClass.contains(Reg)) 577223017Sdim continue; 578223017Sdim 579243830Sdim // For SVR4, don't emit a move for the CR spill slot if we haven't 580243830Sdim // spilled CRs. 581243830Sdim if (Subtarget.isSVR4ABI() 582243830Sdim && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 583243830Sdim && !spillsCR(MF)) 584243830Sdim continue; 585243830Sdim 586243830Sdim // For 64-bit SVR4 when we have spilled CRs, the spill location 587243830Sdim // is SP+8, not a frame-relative slot. 588243830Sdim if (Subtarget.isSVR4ABI() 589243830Sdim && Subtarget.isPPC64() 590243830Sdim && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 591243830Sdim MachineLocation CSDst(PPC::X1, 8); 592243830Sdim MachineLocation CSSrc(PPC::CR2); 593243830Sdim Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 594243830Sdim continue; 595243830Sdim } 596243830Sdim 597243830Sdim int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 598218885Sdim MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 599218885Sdim MachineLocation CSSrc(Reg); 600218885Sdim Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 601218885Sdim } 602218885Sdim } 603218885Sdim} 604218885Sdim 605218885Sdimvoid PPCFrameLowering::emitEpilogue(MachineFunction &MF, 606218885Sdim MachineBasicBlock &MBB) const { 607218885Sdim MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 608218885Sdim assert(MBBI != MBB.end() && "Returning block has no terminator"); 609218885Sdim const PPCInstrInfo &TII = 610218885Sdim *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 611218885Sdim 612218885Sdim unsigned RetOpcode = MBBI->getOpcode(); 613218885Sdim DebugLoc dl; 614218885Sdim 615218885Sdim assert((RetOpcode == PPC::BLR || 616218885Sdim RetOpcode == PPC::TCRETURNri || 617218885Sdim RetOpcode == PPC::TCRETURNdi || 618218885Sdim RetOpcode == PPC::TCRETURNai || 619218885Sdim RetOpcode == PPC::TCRETURNri8 || 620218885Sdim RetOpcode == PPC::TCRETURNdi8 || 621218885Sdim RetOpcode == PPC::TCRETURNai8) && 622218885Sdim "Can only insert epilog into returning blocks"); 623218885Sdim 624218885Sdim // Get alignment info so we know how to restore r1 625218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 626218885Sdim unsigned TargetAlign = getStackAlignment(); 627218885Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 628218885Sdim 629218885Sdim // Get the number of bytes allocated from the FrameInfo. 630218885Sdim int FrameSize = MFI->getStackSize(); 631218885Sdim 632218885Sdim // Get processor type. 633218885Sdim bool isPPC64 = Subtarget.isPPC64(); 634218885Sdim // Get operating system 635218885Sdim bool isDarwinABI = Subtarget.isDarwinABI(); 636218885Sdim // Check if the link register (LR) has been saved. 637218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 638218885Sdim bool MustSaveLR = FI->mustSaveLR(); 639218885Sdim // Do we have a frame pointer for this function? 640218885Sdim bool HasFP = hasFP(MF); 641218885Sdim 642218885Sdim int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 643218885Sdim 644218885Sdim int FPOffset = 0; 645218885Sdim if (HasFP) { 646218885Sdim if (Subtarget.isSVR4ABI()) { 647218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 648218885Sdim int FPIndex = FI->getFramePointerSaveIndex(); 649218885Sdim assert(FPIndex && "No Frame Pointer Save Slot!"); 650218885Sdim FPOffset = FFI->getObjectOffset(FPIndex); 651218885Sdim } else { 652218885Sdim FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 653218885Sdim } 654218885Sdim } 655218885Sdim 656218885Sdim bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 657218885Sdim RetOpcode == PPC::TCRETURNdi || 658218885Sdim RetOpcode == PPC::TCRETURNai || 659218885Sdim RetOpcode == PPC::TCRETURNri8 || 660218885Sdim RetOpcode == PPC::TCRETURNdi8 || 661218885Sdim RetOpcode == PPC::TCRETURNai8; 662218885Sdim 663218885Sdim if (UsesTCRet) { 664218885Sdim int MaxTCRetDelta = FI->getTailCallSPDelta(); 665218885Sdim MachineOperand &StackAdjust = MBBI->getOperand(1); 666218885Sdim assert(StackAdjust.isImm() && "Expecting immediate value."); 667218885Sdim // Adjust stack pointer. 668218885Sdim int StackAdj = StackAdjust.getImm(); 669218885Sdim int Delta = StackAdj - MaxTCRetDelta; 670218885Sdim assert((Delta >= 0) && "Delta must be positive"); 671218885Sdim if (MaxTCRetDelta>0) 672218885Sdim FrameSize += (StackAdj +Delta); 673218885Sdim else 674218885Sdim FrameSize += StackAdj; 675218885Sdim } 676218885Sdim 677218885Sdim if (FrameSize) { 678218885Sdim // The loaded (or persistent) stack pointer value is offset by the 'stwu' 679218885Sdim // on entry to the function. Add this offset back now. 680218885Sdim if (!isPPC64) { 681218885Sdim // If this function contained a fastcc call and GuaranteedTailCallOpt is 682218885Sdim // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 683218885Sdim // call which invalidates the stack pointer value in SP(0). So we use the 684218885Sdim // value of R31 in this case. 685218885Sdim if (FI->hasFastCall() && isInt<16>(FrameSize)) { 686218885Sdim assert(hasFP(MF) && "Expecting a valid the frame pointer."); 687218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 688218885Sdim .addReg(PPC::R31).addImm(FrameSize); 689218885Sdim } else if(FI->hasFastCall()) { 690218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 691218885Sdim .addImm(FrameSize >> 16); 692218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 693218885Sdim .addReg(PPC::R0, RegState::Kill) 694218885Sdim .addImm(FrameSize & 0xFFFF); 695218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 696218885Sdim .addReg(PPC::R1) 697218885Sdim .addReg(PPC::R31) 698218885Sdim .addReg(PPC::R0); 699218885Sdim } else if (isInt<16>(FrameSize) && 700218885Sdim (!ALIGN_STACK || TargetAlign >= MaxAlign) && 701218885Sdim !MFI->hasVarSizedObjects()) { 702218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 703218885Sdim .addReg(PPC::R1).addImm(FrameSize); 704218885Sdim } else { 705218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 706218885Sdim .addImm(0).addReg(PPC::R1); 707218885Sdim } 708218885Sdim } else { 709218885Sdim if (FI->hasFastCall() && isInt<16>(FrameSize)) { 710218885Sdim assert(hasFP(MF) && "Expecting a valid the frame pointer."); 711218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 712218885Sdim .addReg(PPC::X31).addImm(FrameSize); 713218885Sdim } else if(FI->hasFastCall()) { 714218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 715218885Sdim .addImm(FrameSize >> 16); 716218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 717218885Sdim .addReg(PPC::X0, RegState::Kill) 718218885Sdim .addImm(FrameSize & 0xFFFF); 719218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 720218885Sdim .addReg(PPC::X1) 721218885Sdim .addReg(PPC::X31) 722218885Sdim .addReg(PPC::X0); 723218885Sdim } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 724218885Sdim !MFI->hasVarSizedObjects()) { 725218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 726218885Sdim .addReg(PPC::X1).addImm(FrameSize); 727218885Sdim } else { 728218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 729218885Sdim .addImm(0).addReg(PPC::X1); 730218885Sdim } 731218885Sdim } 732218885Sdim } 733218885Sdim 734218885Sdim if (isPPC64) { 735218885Sdim if (MustSaveLR) 736218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 737218885Sdim .addImm(LROffset/4).addReg(PPC::X1); 738218885Sdim 739218885Sdim if (HasFP) 740218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 741218885Sdim .addImm(FPOffset/4).addReg(PPC::X1); 742218885Sdim 743218885Sdim if (MustSaveLR) 744218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 745218885Sdim } else { 746218885Sdim if (MustSaveLR) 747218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 748218885Sdim .addImm(LROffset).addReg(PPC::R1); 749218885Sdim 750218885Sdim if (HasFP) 751218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 752218885Sdim .addImm(FPOffset).addReg(PPC::R1); 753218885Sdim 754218885Sdim if (MustSaveLR) 755218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 756218885Sdim } 757218885Sdim 758218885Sdim // Callee pop calling convention. Pop parameter/linkage area. Used for tail 759218885Sdim // call optimization 760234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 761218885Sdim MF.getFunction()->getCallingConv() == CallingConv::Fast) { 762218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 763218885Sdim unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 764218885Sdim unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 765218885Sdim unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 766218885Sdim unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 767218885Sdim unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 768218885Sdim unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 769218885Sdim unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 770218885Sdim unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 771218885Sdim 772218885Sdim if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 773218885Sdim BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 774218885Sdim .addReg(StackReg).addImm(CallerAllocatedAmt); 775218885Sdim } else { 776218885Sdim BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 777218885Sdim .addImm(CallerAllocatedAmt >> 16); 778218885Sdim BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 779218885Sdim .addReg(TmpReg, RegState::Kill) 780218885Sdim .addImm(CallerAllocatedAmt & 0xFFFF); 781218885Sdim BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 782218885Sdim .addReg(StackReg) 783218885Sdim .addReg(FPReg) 784218885Sdim .addReg(TmpReg); 785218885Sdim } 786218885Sdim } else if (RetOpcode == PPC::TCRETURNdi) { 787218885Sdim MBBI = MBB.getLastNonDebugInstr(); 788218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 789218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 790218885Sdim addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 791218885Sdim } else if (RetOpcode == PPC::TCRETURNri) { 792218885Sdim MBBI = MBB.getLastNonDebugInstr(); 793218885Sdim assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 794218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 795218885Sdim } else if (RetOpcode == PPC::TCRETURNai) { 796218885Sdim MBBI = MBB.getLastNonDebugInstr(); 797218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 798218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 799218885Sdim } else if (RetOpcode == PPC::TCRETURNdi8) { 800218885Sdim MBBI = MBB.getLastNonDebugInstr(); 801218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 802218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 803218885Sdim addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 804218885Sdim } else if (RetOpcode == PPC::TCRETURNri8) { 805218885Sdim MBBI = MBB.getLastNonDebugInstr(); 806218885Sdim assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 807218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 808218885Sdim } else if (RetOpcode == PPC::TCRETURNai8) { 809218885Sdim MBBI = MBB.getLastNonDebugInstr(); 810218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 811218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 812218885Sdim } 813218885Sdim} 814218885Sdim 815218885Sdim/// MustSaveLR - Return true if this function requires that we save the LR 816218885Sdim/// register onto the stack in the prolog and restore it in the epilog of the 817218885Sdim/// function. 818218885Sdimstatic bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 819218885Sdim const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 820218885Sdim 821218885Sdim // We need a save/restore of LR if there is any def of LR (which is 822218885Sdim // defined by calls, including the PIC setup sequence), or if there is 823218885Sdim // some use of the LR stack slot (e.g. for builtin_return_address). 824218885Sdim // (LR comes in 32 and 64 bit versions.) 825218885Sdim MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 826218885Sdim return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 827218885Sdim} 828218885Sdim 829218885Sdimvoid 830218885SdimPPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 831249423Sdim RegScavenger *) const { 832218885Sdim const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 833218885Sdim 834218885Sdim // Save and clear the LR state. 835218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 836218885Sdim unsigned LR = RegInfo->getRARegister(); 837218885Sdim FI->setMustSaveLR(MustSaveLR(MF, LR)); 838249423Sdim MachineRegisterInfo &MRI = MF.getRegInfo(); 839249423Sdim MRI.setPhysRegUnused(LR); 840218885Sdim 841218885Sdim // Save R31 if necessary 842218885Sdim int FPSI = FI->getFramePointerSaveIndex(); 843218885Sdim bool isPPC64 = Subtarget.isPPC64(); 844218885Sdim bool isDarwinABI = Subtarget.isDarwinABI(); 845218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 846218885Sdim 847218885Sdim // If the frame pointer save index hasn't been defined yet. 848218885Sdim if (!FPSI && needsFP(MF)) { 849218885Sdim // Find out what the fix offset of the frame pointer save area. 850218885Sdim int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 851218885Sdim // Allocate the frame index for frame pointer save area. 852218885Sdim FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 853218885Sdim // Save the result. 854218885Sdim FI->setFramePointerSaveIndex(FPSI); 855218885Sdim } 856218885Sdim 857218885Sdim // Reserve stack space to move the linkage area to in case of a tail call. 858218885Sdim int TCSPDelta = 0; 859234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 860234353Sdim (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 861218885Sdim MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 862218885Sdim } 863218885Sdim 864249423Sdim // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the 865249423Sdim // function uses CR 2, 3, or 4. 866249423Sdim if (!isPPC64 && !isDarwinABI && 867249423Sdim (MRI.isPhysRegUsed(PPC::CR2) || 868249423Sdim MRI.isPhysRegUsed(PPC::CR3) || 869249423Sdim MRI.isPhysRegUsed(PPC::CR4))) { 870249423Sdim int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true); 871249423Sdim FI->setCRSpillFrameIndex(FrameIdx); 872249423Sdim } 873218885Sdim} 874218885Sdim 875249423Sdimvoid PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF, 876249423Sdim RegScavenger *RS) const { 877218885Sdim // Early exit if not using the SVR4 ABI. 878249423Sdim if (!Subtarget.isSVR4ABI()) { 879249423Sdim addScavengingSpillSlot(MF, RS); 880218885Sdim return; 881249423Sdim } 882218885Sdim 883218885Sdim // Get callee saved register information. 884218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 885218885Sdim const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 886218885Sdim 887218885Sdim // Early exit if no callee saved registers are modified! 888218885Sdim if (CSI.empty() && !needsFP(MF)) { 889249423Sdim addScavengingSpillSlot(MF, RS); 890218885Sdim return; 891218885Sdim } 892218885Sdim 893218885Sdim unsigned MinGPR = PPC::R31; 894218885Sdim unsigned MinG8R = PPC::X31; 895218885Sdim unsigned MinFPR = PPC::F31; 896218885Sdim unsigned MinVR = PPC::V31; 897218885Sdim 898218885Sdim bool HasGPSaveArea = false; 899218885Sdim bool HasG8SaveArea = false; 900218885Sdim bool HasFPSaveArea = false; 901218885Sdim bool HasVRSAVESaveArea = false; 902218885Sdim bool HasVRSaveArea = false; 903218885Sdim 904218885Sdim SmallVector<CalleeSavedInfo, 18> GPRegs; 905218885Sdim SmallVector<CalleeSavedInfo, 18> G8Regs; 906218885Sdim SmallVector<CalleeSavedInfo, 18> FPRegs; 907218885Sdim SmallVector<CalleeSavedInfo, 18> VRegs; 908218885Sdim 909218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 910218885Sdim unsigned Reg = CSI[i].getReg(); 911239462Sdim if (PPC::GPRCRegClass.contains(Reg)) { 912218885Sdim HasGPSaveArea = true; 913218885Sdim 914218885Sdim GPRegs.push_back(CSI[i]); 915218885Sdim 916218885Sdim if (Reg < MinGPR) { 917218885Sdim MinGPR = Reg; 918218885Sdim } 919239462Sdim } else if (PPC::G8RCRegClass.contains(Reg)) { 920218885Sdim HasG8SaveArea = true; 921218885Sdim 922218885Sdim G8Regs.push_back(CSI[i]); 923218885Sdim 924218885Sdim if (Reg < MinG8R) { 925218885Sdim MinG8R = Reg; 926218885Sdim } 927239462Sdim } else if (PPC::F8RCRegClass.contains(Reg)) { 928218885Sdim HasFPSaveArea = true; 929218885Sdim 930218885Sdim FPRegs.push_back(CSI[i]); 931218885Sdim 932218885Sdim if (Reg < MinFPR) { 933218885Sdim MinFPR = Reg; 934218885Sdim } 935239462Sdim } else if (PPC::CRBITRCRegClass.contains(Reg) || 936239462Sdim PPC::CRRCRegClass.contains(Reg)) { 937243830Sdim ; // do nothing, as we already know whether CRs are spilled 938239462Sdim } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 939218885Sdim HasVRSAVESaveArea = true; 940239462Sdim } else if (PPC::VRRCRegClass.contains(Reg)) { 941218885Sdim HasVRSaveArea = true; 942218885Sdim 943218885Sdim VRegs.push_back(CSI[i]); 944218885Sdim 945218885Sdim if (Reg < MinVR) { 946218885Sdim MinVR = Reg; 947218885Sdim } 948218885Sdim } else { 949218885Sdim llvm_unreachable("Unknown RegisterClass!"); 950218885Sdim } 951218885Sdim } 952218885Sdim 953218885Sdim PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 954249423Sdim const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); 955218885Sdim 956218885Sdim int64_t LowerBound = 0; 957218885Sdim 958218885Sdim // Take into account stack space reserved for tail calls. 959218885Sdim int TCSPDelta = 0; 960234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 961234353Sdim (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 962218885Sdim LowerBound = TCSPDelta; 963218885Sdim } 964218885Sdim 965218885Sdim // The Floating-point register save area is right below the back chain word 966218885Sdim // of the previous stack frame. 967218885Sdim if (HasFPSaveArea) { 968218885Sdim for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 969218885Sdim int FI = FPRegs[i].getFrameIdx(); 970218885Sdim 971218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 972218885Sdim } 973218885Sdim 974249423Sdim LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8; 975218885Sdim } 976218885Sdim 977218885Sdim // Check whether the frame pointer register is allocated. If so, make sure it 978218885Sdim // is spilled to the correct offset. 979218885Sdim if (needsFP(MF)) { 980218885Sdim HasGPSaveArea = true; 981218885Sdim 982218885Sdim int FI = PFI->getFramePointerSaveIndex(); 983218885Sdim assert(FI && "No Frame Pointer Save Slot!"); 984218885Sdim 985218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 986218885Sdim } 987218885Sdim 988218885Sdim // General register save area starts right below the Floating-point 989218885Sdim // register save area. 990218885Sdim if (HasGPSaveArea || HasG8SaveArea) { 991218885Sdim // Move general register save area spill slots down, taking into account 992218885Sdim // the size of the Floating-point register save area. 993218885Sdim for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 994218885Sdim int FI = GPRegs[i].getFrameIdx(); 995218885Sdim 996218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 997218885Sdim } 998218885Sdim 999218885Sdim // Move general register save area spill slots down, taking into account 1000218885Sdim // the size of the Floating-point register save area. 1001218885Sdim for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 1002218885Sdim int FI = G8Regs[i].getFrameIdx(); 1003218885Sdim 1004218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1005218885Sdim } 1006218885Sdim 1007218885Sdim unsigned MinReg = 1008249423Sdim std::min<unsigned>(TRI->getEncodingValue(MinGPR), 1009249423Sdim TRI->getEncodingValue(MinG8R)); 1010218885Sdim 1011218885Sdim if (Subtarget.isPPC64()) { 1012218885Sdim LowerBound -= (31 - MinReg + 1) * 8; 1013218885Sdim } else { 1014218885Sdim LowerBound -= (31 - MinReg + 1) * 4; 1015218885Sdim } 1016218885Sdim } 1017218885Sdim 1018243830Sdim // For 32-bit only, the CR save area is below the general register 1019243830Sdim // save area. For 64-bit SVR4, the CR save area is addressed relative 1020243830Sdim // to the stack pointer and hence does not need an adjustment here. 1021243830Sdim // Only CR2 (the first nonvolatile spilled) has an associated frame 1022243830Sdim // index so that we have a single uniform save area. 1023243830Sdim if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 1024218885Sdim // Adjust the frame index of the CR spill slot. 1025218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1026218885Sdim unsigned Reg = CSI[i].getReg(); 1027218885Sdim 1028243830Sdim if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 1029243830Sdim // Leave Darwin logic as-is. 1030243830Sdim || (!Subtarget.isSVR4ABI() && 1031243830Sdim (PPC::CRBITRCRegClass.contains(Reg) || 1032243830Sdim PPC::CRRCRegClass.contains(Reg)))) { 1033218885Sdim int FI = CSI[i].getFrameIdx(); 1034218885Sdim 1035218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1036218885Sdim } 1037218885Sdim } 1038218885Sdim 1039218885Sdim LowerBound -= 4; // The CR save area is always 4 bytes long. 1040218885Sdim } 1041218885Sdim 1042218885Sdim if (HasVRSAVESaveArea) { 1043218885Sdim // FIXME SVR4: Is it actually possible to have multiple elements in CSI 1044218885Sdim // which have the VRSAVE register class? 1045218885Sdim // Adjust the frame index of the VRSAVE spill slot. 1046218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1047218885Sdim unsigned Reg = CSI[i].getReg(); 1048218885Sdim 1049239462Sdim if (PPC::VRSAVERCRegClass.contains(Reg)) { 1050218885Sdim int FI = CSI[i].getFrameIdx(); 1051218885Sdim 1052218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1053218885Sdim } 1054218885Sdim } 1055218885Sdim 1056218885Sdim LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1057218885Sdim } 1058218885Sdim 1059218885Sdim if (HasVRSaveArea) { 1060218885Sdim // Insert alignment padding, we need 16-byte alignment. 1061218885Sdim LowerBound = (LowerBound - 15) & ~(15); 1062218885Sdim 1063218885Sdim for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1064218885Sdim int FI = VRegs[i].getFrameIdx(); 1065218885Sdim 1066218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1067218885Sdim } 1068218885Sdim } 1069249423Sdim 1070249423Sdim addScavengingSpillSlot(MF, RS); 1071218885Sdim} 1072243830Sdim 1073249423Sdimvoid 1074249423SdimPPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF, 1075249423Sdim RegScavenger *RS) const { 1076249423Sdim // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 1077249423Sdim // a large stack, which will require scavenging a register to materialize a 1078249423Sdim // large offset. 1079249423Sdim 1080249423Sdim // We need to have a scavenger spill slot for spills if the frame size is 1081249423Sdim // large. In case there is no free register for large-offset addressing, 1082249423Sdim // this slot is used for the necessary emergency spill. Also, we need the 1083249423Sdim // slot for dynamic stack allocations. 1084249423Sdim 1085249423Sdim // The scavenger might be invoked if the frame offset does not fit into 1086249423Sdim // the 16-bit immediate. We don't know the complete frame size here 1087249423Sdim // because we've not yet computed callee-saved register spills or the 1088249423Sdim // needed alignment padding. 1089249423Sdim unsigned StackSize = determineFrameLayout(MF, false, true); 1090249423Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 1091249423Sdim if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) || 1092249423Sdim hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) { 1093249423Sdim const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 1094249423Sdim const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 1095249423Sdim const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC; 1096249423Sdim RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1097249423Sdim RC->getAlignment(), 1098249423Sdim false)); 1099249423Sdim 1100249423Sdim // These kinds of spills might need two registers. 1101249423Sdim if (spillsCR(MF) || spillsVRSAVE(MF)) 1102249423Sdim RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 1103249423Sdim RC->getAlignment(), 1104249423Sdim false)); 1105249423Sdim 1106249423Sdim } 1107249423Sdim} 1108249423Sdim 1109243830Sdimbool 1110243830SdimPPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1111243830Sdim MachineBasicBlock::iterator MI, 1112243830Sdim const std::vector<CalleeSavedInfo> &CSI, 1113243830Sdim const TargetRegisterInfo *TRI) const { 1114243830Sdim 1115243830Sdim // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1116243830Sdim // Return false otherwise to maintain pre-existing behavior. 1117243830Sdim if (!Subtarget.isSVR4ABI()) 1118243830Sdim return false; 1119243830Sdim 1120243830Sdim MachineFunction *MF = MBB.getParent(); 1121243830Sdim const PPCInstrInfo &TII = 1122243830Sdim *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1123243830Sdim DebugLoc DL; 1124243830Sdim bool CRSpilled = false; 1125243830Sdim 1126243830Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1127243830Sdim unsigned Reg = CSI[i].getReg(); 1128243830Sdim // CR2 through CR4 are the nonvolatile CR fields. 1129243830Sdim bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1130243830Sdim 1131243830Sdim if (CRSpilled && IsCRField) 1132243830Sdim continue; 1133243830Sdim 1134243830Sdim // Add the callee-saved register as live-in; it's killed at the spill. 1135243830Sdim MBB.addLiveIn(Reg); 1136243830Sdim 1137243830Sdim // Insert the spill to the stack frame. 1138243830Sdim if (IsCRField) { 1139243830Sdim CRSpilled = true; 1140243830Sdim // The first time we see a CR field, store the whole CR into the 1141243830Sdim // save slot via GPR12 (available in the prolog for 32- and 64-bit). 1142243830Sdim if (Subtarget.isPPC64()) { 1143243830Sdim // 64-bit: SP+8 1144249423Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR8), PPC::X12)); 1145249423Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW8)) 1146243830Sdim .addReg(PPC::X12, 1147243830Sdim getKillRegState(true)) 1148243830Sdim .addImm(8) 1149243830Sdim .addReg(PPC::X1)); 1150243830Sdim } else { 1151243830Sdim // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1152243830Sdim // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1153243830Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)); 1154243830Sdim MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1155243830Sdim .addReg(PPC::R12, 1156243830Sdim getKillRegState(true)), 1157243830Sdim CSI[i].getFrameIdx())); 1158243830Sdim } 1159243830Sdim 1160243830Sdim // Record that we spill the CR in this function. 1161243830Sdim PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1162243830Sdim FuncInfo->setSpillsCR(); 1163243830Sdim } else { 1164243830Sdim const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1165243830Sdim TII.storeRegToStackSlot(MBB, MI, Reg, true, 1166243830Sdim CSI[i].getFrameIdx(), RC, TRI); 1167243830Sdim } 1168243830Sdim } 1169243830Sdim return true; 1170243830Sdim} 1171243830Sdim 1172243830Sdimstatic void 1173243830SdimrestoreCRs(bool isPPC64, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1174243830Sdim MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1175243830Sdim const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1176243830Sdim 1177243830Sdim MachineFunction *MF = MBB.getParent(); 1178243830Sdim const PPCInstrInfo &TII = 1179243830Sdim *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1180243830Sdim DebugLoc DL; 1181243830Sdim unsigned RestoreOp, MoveReg; 1182243830Sdim 1183243830Sdim if (isPPC64) { 1184243830Sdim // 64-bit: SP+8 1185249423Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ8), PPC::X12) 1186243830Sdim .addImm(8) 1187243830Sdim .addReg(PPC::X1)); 1188243830Sdim RestoreOp = PPC::MTCRF8; 1189243830Sdim MoveReg = PPC::X12; 1190243830Sdim } else { 1191243830Sdim // 32-bit: FP-relative 1192243830Sdim MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1193243830Sdim PPC::R12), 1194243830Sdim CSI[CSIIndex].getFrameIdx())); 1195243830Sdim RestoreOp = PPC::MTCRF; 1196243830Sdim MoveReg = PPC::R12; 1197243830Sdim } 1198243830Sdim 1199243830Sdim if (CR2Spilled) 1200243830Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1201249423Sdim .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled))); 1202243830Sdim 1203243830Sdim if (CR3Spilled) 1204243830Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1205249423Sdim .addReg(MoveReg, getKillRegState(!CR4Spilled))); 1206243830Sdim 1207243830Sdim if (CR4Spilled) 1208243830Sdim MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1209249423Sdim .addReg(MoveReg, getKillRegState(true))); 1210243830Sdim} 1211243830Sdim 1212249423Sdimvoid PPCFrameLowering:: 1213249423SdimeliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, 1214249423Sdim MachineBasicBlock::iterator I) const { 1215249423Sdim const PPCInstrInfo &TII = 1216249423Sdim *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 1217249423Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 1218249423Sdim I->getOpcode() == PPC::ADJCALLSTACKUP) { 1219249423Sdim // Add (actually subtract) back the amount the callee popped on return. 1220249423Sdim if (int CalleeAmt = I->getOperand(1).getImm()) { 1221249423Sdim bool is64Bit = Subtarget.isPPC64(); 1222249423Sdim CalleeAmt *= -1; 1223249423Sdim unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1; 1224249423Sdim unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0; 1225249423Sdim unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI; 1226249423Sdim unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4; 1227249423Sdim unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS; 1228249423Sdim unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI; 1229249423Sdim MachineInstr *MI = I; 1230249423Sdim DebugLoc dl = MI->getDebugLoc(); 1231249423Sdim 1232249423Sdim if (isInt<16>(CalleeAmt)) { 1233249423Sdim BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg) 1234249423Sdim .addReg(StackReg, RegState::Kill) 1235249423Sdim .addImm(CalleeAmt); 1236249423Sdim } else { 1237249423Sdim MachineBasicBlock::iterator MBBI = I; 1238249423Sdim BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 1239249423Sdim .addImm(CalleeAmt >> 16); 1240249423Sdim BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 1241249423Sdim .addReg(TmpReg, RegState::Kill) 1242249423Sdim .addImm(CalleeAmt & 0xFFFF); 1243249423Sdim BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg) 1244249423Sdim .addReg(StackReg, RegState::Kill) 1245249423Sdim .addReg(TmpReg); 1246249423Sdim } 1247249423Sdim } 1248249423Sdim } 1249249423Sdim // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions. 1250249423Sdim MBB.erase(I); 1251249423Sdim} 1252249423Sdim 1253243830Sdimbool 1254243830SdimPPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1255243830Sdim MachineBasicBlock::iterator MI, 1256243830Sdim const std::vector<CalleeSavedInfo> &CSI, 1257243830Sdim const TargetRegisterInfo *TRI) const { 1258243830Sdim 1259243830Sdim // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1260243830Sdim // Return false otherwise to maintain pre-existing behavior. 1261243830Sdim if (!Subtarget.isSVR4ABI()) 1262243830Sdim return false; 1263243830Sdim 1264243830Sdim MachineFunction *MF = MBB.getParent(); 1265243830Sdim const PPCInstrInfo &TII = 1266243830Sdim *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1267243830Sdim bool CR2Spilled = false; 1268243830Sdim bool CR3Spilled = false; 1269243830Sdim bool CR4Spilled = false; 1270243830Sdim unsigned CSIIndex = 0; 1271243830Sdim 1272243830Sdim // Initialize insertion-point logic; we will be restoring in reverse 1273243830Sdim // order of spill. 1274243830Sdim MachineBasicBlock::iterator I = MI, BeforeI = I; 1275243830Sdim bool AtStart = I == MBB.begin(); 1276243830Sdim 1277243830Sdim if (!AtStart) 1278243830Sdim --BeforeI; 1279243830Sdim 1280243830Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1281243830Sdim unsigned Reg = CSI[i].getReg(); 1282243830Sdim 1283243830Sdim if (Reg == PPC::CR2) { 1284243830Sdim CR2Spilled = true; 1285243830Sdim // The spill slot is associated only with CR2, which is the 1286243830Sdim // first nonvolatile spilled. Save it here. 1287243830Sdim CSIIndex = i; 1288243830Sdim continue; 1289243830Sdim } else if (Reg == PPC::CR3) { 1290243830Sdim CR3Spilled = true; 1291243830Sdim continue; 1292243830Sdim } else if (Reg == PPC::CR4) { 1293243830Sdim CR4Spilled = true; 1294243830Sdim continue; 1295243830Sdim } else { 1296243830Sdim // When we first encounter a non-CR register after seeing at 1297243830Sdim // least one CR register, restore all spilled CRs together. 1298243830Sdim if ((CR2Spilled || CR3Spilled || CR4Spilled) 1299243830Sdim && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1300243830Sdim restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled, 1301243830Sdim MBB, I, CSI, CSIIndex); 1302243830Sdim CR2Spilled = CR3Spilled = CR4Spilled = false; 1303243830Sdim } 1304243830Sdim 1305243830Sdim // Default behavior for non-CR saves. 1306243830Sdim const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1307243830Sdim TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1308243830Sdim RC, TRI); 1309243830Sdim assert(I != MBB.begin() && 1310243830Sdim "loadRegFromStackSlot didn't insert any code!"); 1311243830Sdim } 1312243830Sdim 1313243830Sdim // Insert in reverse order. 1314243830Sdim if (AtStart) 1315243830Sdim I = MBB.begin(); 1316243830Sdim else { 1317243830Sdim I = BeforeI; 1318243830Sdim ++I; 1319243830Sdim } 1320243830Sdim } 1321243830Sdim 1322243830Sdim // If we haven't yet spilled the CRs, do so now. 1323243830Sdim if (CR2Spilled || CR3Spilled || CR4Spilled) 1324243830Sdim restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled, 1325243830Sdim MBB, I, CSI, CSIIndex); 1326243830Sdim 1327243830Sdim return true; 1328243830Sdim} 1329243830Sdim 1330