PPCFrameLowering.cpp revision 243830
1//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file contains the PPC implementation of TargetFrameLowering class. 11// 12//===----------------------------------------------------------------------===// 13 14#include "PPCFrameLowering.h" 15#include "PPCInstrInfo.h" 16#include "PPCInstrBuilder.h" 17#include "PPCMachineFunctionInfo.h" 18#include "llvm/Function.h" 19#include "llvm/CodeGen/MachineFrameInfo.h" 20#include "llvm/CodeGen/MachineFunction.h" 21#include "llvm/CodeGen/MachineInstrBuilder.h" 22#include "llvm/CodeGen/MachineModuleInfo.h" 23#include "llvm/CodeGen/MachineRegisterInfo.h" 24#include "llvm/CodeGen/RegisterScavenging.h" 25#include "llvm/Target/TargetOptions.h" 26 27using namespace llvm; 28 29// FIXME This disables some code that aligns the stack to a boundary bigger than 30// the default (16 bytes on Darwin) when there is a stack local of greater 31// alignment. This does not currently work, because the delta between old and 32// new stack pointers is added to offsets that reference incoming parameters 33// after the prolog is generated, and the code that does that doesn't handle a 34// variable delta. You don't want to do that anyway; a better approach is to 35// reserve another register that retains to the incoming stack pointer, and 36// reference parameters relative to that. 37#define ALIGN_STACK 0 38 39 40/// VRRegNo - Map from a numbered VR register to its enum value. 41/// 42static const uint16_t VRRegNo[] = { 43 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 44 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 45 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 46 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 47}; 48 49/// RemoveVRSaveCode - We have found that this function does not need any code 50/// to manipulate the VRSAVE register, even though it uses vector registers. 51/// This can happen when the only registers used are known to be live in or out 52/// of the function. Remove all of the VRSAVE related code from the function. 53/// FIXME: The removal of the code results in a compile failure at -O0 when the 54/// function contains a function call, as the GPR containing original VRSAVE 55/// contents is spilled and reloaded around the call. Without the prolog code, 56/// the spill instruction refers to an undefined register. This code needs 57/// to account for all uses of that GPR. 58static void RemoveVRSaveCode(MachineInstr *MI) { 59 MachineBasicBlock *Entry = MI->getParent(); 60 MachineFunction *MF = Entry->getParent(); 61 62 // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 63 MachineBasicBlock::iterator MBBI = MI; 64 ++MBBI; 65 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 66 MBBI->eraseFromParent(); 67 68 bool RemovedAllMTVRSAVEs = true; 69 // See if we can find and remove the MTVRSAVE instruction from all of the 70 // epilog blocks. 71 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 72 // If last instruction is a return instruction, add an epilogue 73 if (!I->empty() && I->back().isReturn()) { 74 bool FoundIt = false; 75 for (MBBI = I->end(); MBBI != I->begin(); ) { 76 --MBBI; 77 if (MBBI->getOpcode() == PPC::MTVRSAVE) { 78 MBBI->eraseFromParent(); // remove it. 79 FoundIt = true; 80 break; 81 } 82 } 83 RemovedAllMTVRSAVEs &= FoundIt; 84 } 85 } 86 87 // If we found and removed all MTVRSAVE instructions, remove the read of 88 // VRSAVE as well. 89 if (RemovedAllMTVRSAVEs) { 90 MBBI = MI; 91 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 92 --MBBI; 93 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 94 MBBI->eraseFromParent(); 95 } 96 97 // Finally, nuke the UPDATE_VRSAVE. 98 MI->eraseFromParent(); 99} 100 101// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 102// instruction selector. Based on the vector registers that have been used, 103// transform this into the appropriate ORI instruction. 104static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 105 MachineFunction *MF = MI->getParent()->getParent(); 106 DebugLoc dl = MI->getDebugLoc(); 107 108 unsigned UsedRegMask = 0; 109 for (unsigned i = 0; i != 32; ++i) 110 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 111 UsedRegMask |= 1 << (31-i); 112 113 // Live in and live out values already must be in the mask, so don't bother 114 // marking them. 115 for (MachineRegisterInfo::livein_iterator 116 I = MF->getRegInfo().livein_begin(), 117 E = MF->getRegInfo().livein_end(); I != E; ++I) { 118 unsigned RegNo = getPPCRegisterNumbering(I->first); 119 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 120 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 121 } 122 for (MachineRegisterInfo::liveout_iterator 123 I = MF->getRegInfo().liveout_begin(), 124 E = MF->getRegInfo().liveout_end(); I != E; ++I) { 125 unsigned RegNo = getPPCRegisterNumbering(*I); 126 if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 127 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 128 } 129 130 // If no registers are used, turn this into a copy. 131 if (UsedRegMask == 0) { 132 // Remove all VRSAVE code. 133 RemoveVRSaveCode(MI); 134 return; 135 } 136 137 unsigned SrcReg = MI->getOperand(1).getReg(); 138 unsigned DstReg = MI->getOperand(0).getReg(); 139 140 if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 141 if (DstReg != SrcReg) 142 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 143 .addReg(SrcReg) 144 .addImm(UsedRegMask); 145 else 146 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 147 .addReg(SrcReg, RegState::Kill) 148 .addImm(UsedRegMask); 149 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 150 if (DstReg != SrcReg) 151 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 152 .addReg(SrcReg) 153 .addImm(UsedRegMask >> 16); 154 else 155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 156 .addReg(SrcReg, RegState::Kill) 157 .addImm(UsedRegMask >> 16); 158 } else { 159 if (DstReg != SrcReg) 160 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 161 .addReg(SrcReg) 162 .addImm(UsedRegMask >> 16); 163 else 164 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 165 .addReg(SrcReg, RegState::Kill) 166 .addImm(UsedRegMask >> 16); 167 168 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 169 .addReg(DstReg, RegState::Kill) 170 .addImm(UsedRegMask & 0xFFFF); 171 } 172 173 // Remove the old UPDATE_VRSAVE instruction. 174 MI->eraseFromParent(); 175} 176 177static bool spillsCR(const MachineFunction &MF) { 178 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 179 return FuncInfo->isCRSpilled(); 180} 181 182/// determineFrameLayout - Determine the size of the frame and maximum call 183/// frame size. 184void PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const { 185 MachineFrameInfo *MFI = MF.getFrameInfo(); 186 187 // Get the number of bytes to allocate from the FrameInfo 188 unsigned FrameSize = MFI->getStackSize(); 189 190 // Get the alignments provided by the target, and the maximum alignment 191 // (if any) of the fixed frame objects. 192 unsigned MaxAlign = MFI->getMaxAlignment(); 193 unsigned TargetAlign = getStackAlignment(); 194 unsigned AlignMask = TargetAlign - 1; // 195 196 // If we are a leaf function, and use up to 224 bytes of stack space, 197 // don't have a frame pointer, calls, or dynamic alloca then we do not need 198 // to adjust the stack pointer (we fit in the Red Zone). For 64-bit 199 // SVR4, we also require a stack frame if we need to spill the CR, 200 // since this spill area is addressed relative to the stack pointer. 201 bool DisableRedZone = MF.getFunction()->getFnAttributes(). 202 hasAttribute(Attributes::NoRedZone); 203 // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. However, it can 204 // still generate stackless code if all local vars are reg-allocated. 205 // Try: (FrameSize <= 224 206 // || (FrameSize == 0 && Subtarget.isPPC32 && Subtarget.isSVR4ABI())) 207 if (!DisableRedZone && 208 FrameSize <= 224 && // Fits in red zone. 209 !MFI->hasVarSizedObjects() && // No dynamic alloca. 210 !MFI->adjustsStack() && // No calls. 211 !(Subtarget.isPPC64() && // No 64-bit SVR4 CRsave. 212 Subtarget.isSVR4ABI() 213 && spillsCR(MF)) && 214 (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 215 // No need for frame 216 MFI->setStackSize(0); 217 return; 218 } 219 220 // Get the maximum call frame size of all the calls. 221 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 222 223 // Maximum call frame needs to be at least big enough for linkage and 8 args. 224 unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 225 Subtarget.isDarwinABI()); 226 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 227 228 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 229 // that allocations will be aligned. 230 if (MFI->hasVarSizedObjects()) 231 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 232 233 // Update maximum call frame size. 234 MFI->setMaxCallFrameSize(maxCallFrameSize); 235 236 // Include call frame size in total. 237 FrameSize += maxCallFrameSize; 238 239 // Make sure the frame is aligned. 240 FrameSize = (FrameSize + AlignMask) & ~AlignMask; 241 242 // Update frame info. 243 MFI->setStackSize(FrameSize); 244} 245 246// hasFP - Return true if the specified function actually has a dedicated frame 247// pointer register. 248bool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 249 const MachineFrameInfo *MFI = MF.getFrameInfo(); 250 // FIXME: This is pretty much broken by design: hasFP() might be called really 251 // early, before the stack layout was calculated and thus hasFP() might return 252 // true or false here depending on the time of call. 253 return (MFI->getStackSize()) && needsFP(MF); 254} 255 256// needsFP - Return true if the specified function should have a dedicated frame 257// pointer register. This is true if the function has variable sized allocas or 258// if frame pointer elimination is disabled. 259bool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 260 const MachineFrameInfo *MFI = MF.getFrameInfo(); 261 262 // Naked functions have no stack frame pushed, so we don't have a frame 263 // pointer. 264 if (MF.getFunction()->getFnAttributes().hasAttribute(Attributes::Naked)) 265 return false; 266 267 return MF.getTarget().Options.DisableFramePointerElim(MF) || 268 MFI->hasVarSizedObjects() || 269 (MF.getTarget().Options.GuaranteedTailCallOpt && 270 MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 271} 272 273 274void PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 275 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 276 MachineBasicBlock::iterator MBBI = MBB.begin(); 277 MachineFrameInfo *MFI = MF.getFrameInfo(); 278 const PPCInstrInfo &TII = 279 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 280 281 MachineModuleInfo &MMI = MF.getMMI(); 282 DebugLoc dl; 283 bool needsFrameMoves = MMI.hasDebugInfo() || 284 MF.getFunction()->needsUnwindTableEntry(); 285 286 // Prepare for frame info. 287 MCSymbol *FrameLabel = 0; 288 289 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 290 // process it. 291 if (!Subtarget.isSVR4ABI()) 292 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 293 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 294 HandleVRSaveUpdate(MBBI, TII); 295 break; 296 } 297 } 298 299 // Move MBBI back to the beginning of the function. 300 MBBI = MBB.begin(); 301 302 // Work out frame sizes. 303 // FIXME: determineFrameLayout() may change the frame size. This should be 304 // moved upper, to some hook. 305 determineFrameLayout(MF); 306 unsigned FrameSize = MFI->getStackSize(); 307 308 int NegFrameSize = -FrameSize; 309 310 // Get processor type. 311 bool isPPC64 = Subtarget.isPPC64(); 312 // Get operating system 313 bool isDarwinABI = Subtarget.isDarwinABI(); 314 // Check if the link register (LR) must be saved. 315 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 316 bool MustSaveLR = FI->mustSaveLR(); 317 // Do we have a frame pointer for this function? 318 bool HasFP = hasFP(MF); 319 320 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 321 322 int FPOffset = 0; 323 if (HasFP) { 324 if (Subtarget.isSVR4ABI()) { 325 MachineFrameInfo *FFI = MF.getFrameInfo(); 326 int FPIndex = FI->getFramePointerSaveIndex(); 327 assert(FPIndex && "No Frame Pointer Save Slot!"); 328 FPOffset = FFI->getObjectOffset(FPIndex); 329 } else { 330 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 331 } 332 } 333 334 if (isPPC64) { 335 if (MustSaveLR) 336 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 337 338 if (HasFP) 339 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 340 .addReg(PPC::X31) 341 .addImm(FPOffset/4) 342 .addReg(PPC::X1); 343 344 if (MustSaveLR) 345 BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 346 .addReg(PPC::X0) 347 .addImm(LROffset / 4) 348 .addReg(PPC::X1); 349 } else { 350 if (MustSaveLR) 351 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 352 353 if (HasFP) 354 // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative 355 // offsets of R1 is not allowed. 356 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 357 .addReg(PPC::R31) 358 .addImm(FPOffset) 359 .addReg(PPC::R1); 360 361 if (MustSaveLR) 362 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 363 .addReg(PPC::R0) 364 .addImm(LROffset) 365 .addReg(PPC::R1); 366 } 367 368 // Skip if a leaf routine. 369 if (!FrameSize) return; 370 371 // Get stack alignments. 372 unsigned TargetAlign = getStackAlignment(); 373 unsigned MaxAlign = MFI->getMaxAlignment(); 374 375 // Adjust stack pointer: r1 += NegFrameSize. 376 // If there is a preferred stack alignment, align R1 now 377 if (!isPPC64) { 378 // PPC32. 379 if (ALIGN_STACK && MaxAlign > TargetAlign) { 380 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 381 "Invalid alignment!"); 382 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 383 384 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 385 .addReg(PPC::R1) 386 .addImm(0) 387 .addImm(32 - Log2_32(MaxAlign)) 388 .addImm(31); 389 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 390 .addReg(PPC::R0, RegState::Kill) 391 .addImm(NegFrameSize); 392 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 393 .addReg(PPC::R1, RegState::Kill) 394 .addReg(PPC::R1) 395 .addReg(PPC::R0); 396 } else if (isInt<16>(NegFrameSize)) { 397 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 398 .addReg(PPC::R1) 399 .addImm(NegFrameSize) 400 .addReg(PPC::R1); 401 } else { 402 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 403 .addImm(NegFrameSize >> 16); 404 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 405 .addReg(PPC::R0, RegState::Kill) 406 .addImm(NegFrameSize & 0xFFFF); 407 BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 408 .addReg(PPC::R1, RegState::Kill) 409 .addReg(PPC::R1) 410 .addReg(PPC::R0); 411 } 412 } else { // PPC64. 413 if (ALIGN_STACK && MaxAlign > TargetAlign) { 414 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 415 "Invalid alignment!"); 416 assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 417 418 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 419 .addReg(PPC::X1) 420 .addImm(0) 421 .addImm(64 - Log2_32(MaxAlign)); 422 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 423 .addReg(PPC::X0) 424 .addImm(NegFrameSize); 425 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 426 .addReg(PPC::X1, RegState::Kill) 427 .addReg(PPC::X1) 428 .addReg(PPC::X0); 429 } else if (isInt<16>(NegFrameSize)) { 430 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 431 .addReg(PPC::X1) 432 .addImm(NegFrameSize / 4) 433 .addReg(PPC::X1); 434 } else { 435 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 436 .addImm(NegFrameSize >> 16); 437 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 438 .addReg(PPC::X0, RegState::Kill) 439 .addImm(NegFrameSize & 0xFFFF); 440 BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 441 .addReg(PPC::X1, RegState::Kill) 442 .addReg(PPC::X1) 443 .addReg(PPC::X0); 444 } 445 } 446 447 std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 448 449 // Add the "machine moves" for the instructions we generated above, but in 450 // reverse order. 451 if (needsFrameMoves) { 452 // Mark effective beginning of when frame pointer becomes valid. 453 FrameLabel = MMI.getContext().CreateTempSymbol(); 454 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 455 456 // Show update of SP. 457 if (NegFrameSize) { 458 MachineLocation SPDst(MachineLocation::VirtualFP); 459 MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 460 Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 461 } else { 462 MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 463 Moves.push_back(MachineMove(FrameLabel, SP, SP)); 464 } 465 466 if (HasFP) { 467 MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 468 MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 469 Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 470 } 471 472 if (MustSaveLR) { 473 MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 474 MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 475 Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 476 } 477 } 478 479 MCSymbol *ReadyLabel = 0; 480 481 // If there is a frame pointer, copy R1 into R31 482 if (HasFP) { 483 if (!isPPC64) { 484 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 485 .addReg(PPC::R1) 486 .addReg(PPC::R1); 487 } else { 488 BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 489 .addReg(PPC::X1) 490 .addReg(PPC::X1); 491 } 492 493 if (needsFrameMoves) { 494 ReadyLabel = MMI.getContext().CreateTempSymbol(); 495 496 // Mark effective beginning of when frame pointer is ready. 497 BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 498 499 MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 500 (isPPC64 ? PPC::X1 : PPC::R1)); 501 MachineLocation FPSrc(MachineLocation::VirtualFP); 502 Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 503 } 504 } 505 506 if (needsFrameMoves) { 507 MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 508 509 // Add callee saved registers to move list. 510 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 511 for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 512 unsigned Reg = CSI[I].getReg(); 513 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 514 515 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 516 // subregisters of CR2. We just need to emit a move of CR2. 517 if (PPC::CRBITRCRegClass.contains(Reg)) 518 continue; 519 520 // For SVR4, don't emit a move for the CR spill slot if we haven't 521 // spilled CRs. 522 if (Subtarget.isSVR4ABI() 523 && (PPC::CR2 <= Reg && Reg <= PPC::CR4) 524 && !spillsCR(MF)) 525 continue; 526 527 // For 64-bit SVR4 when we have spilled CRs, the spill location 528 // is SP+8, not a frame-relative slot. 529 if (Subtarget.isSVR4ABI() 530 && Subtarget.isPPC64() 531 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 532 MachineLocation CSDst(PPC::X1, 8); 533 MachineLocation CSSrc(PPC::CR2); 534 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 535 continue; 536 } 537 538 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 539 MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 540 MachineLocation CSSrc(Reg); 541 Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 542 } 543 } 544} 545 546void PPCFrameLowering::emitEpilogue(MachineFunction &MF, 547 MachineBasicBlock &MBB) const { 548 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 549 assert(MBBI != MBB.end() && "Returning block has no terminator"); 550 const PPCInstrInfo &TII = 551 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 552 553 unsigned RetOpcode = MBBI->getOpcode(); 554 DebugLoc dl; 555 556 assert((RetOpcode == PPC::BLR || 557 RetOpcode == PPC::TCRETURNri || 558 RetOpcode == PPC::TCRETURNdi || 559 RetOpcode == PPC::TCRETURNai || 560 RetOpcode == PPC::TCRETURNri8 || 561 RetOpcode == PPC::TCRETURNdi8 || 562 RetOpcode == PPC::TCRETURNai8) && 563 "Can only insert epilog into returning blocks"); 564 565 // Get alignment info so we know how to restore r1 566 const MachineFrameInfo *MFI = MF.getFrameInfo(); 567 unsigned TargetAlign = getStackAlignment(); 568 unsigned MaxAlign = MFI->getMaxAlignment(); 569 570 // Get the number of bytes allocated from the FrameInfo. 571 int FrameSize = MFI->getStackSize(); 572 573 // Get processor type. 574 bool isPPC64 = Subtarget.isPPC64(); 575 // Get operating system 576 bool isDarwinABI = Subtarget.isDarwinABI(); 577 // Check if the link register (LR) has been saved. 578 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 579 bool MustSaveLR = FI->mustSaveLR(); 580 // Do we have a frame pointer for this function? 581 bool HasFP = hasFP(MF); 582 583 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 584 585 int FPOffset = 0; 586 if (HasFP) { 587 if (Subtarget.isSVR4ABI()) { 588 MachineFrameInfo *FFI = MF.getFrameInfo(); 589 int FPIndex = FI->getFramePointerSaveIndex(); 590 assert(FPIndex && "No Frame Pointer Save Slot!"); 591 FPOffset = FFI->getObjectOffset(FPIndex); 592 } else { 593 FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 594 } 595 } 596 597 bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 598 RetOpcode == PPC::TCRETURNdi || 599 RetOpcode == PPC::TCRETURNai || 600 RetOpcode == PPC::TCRETURNri8 || 601 RetOpcode == PPC::TCRETURNdi8 || 602 RetOpcode == PPC::TCRETURNai8; 603 604 if (UsesTCRet) { 605 int MaxTCRetDelta = FI->getTailCallSPDelta(); 606 MachineOperand &StackAdjust = MBBI->getOperand(1); 607 assert(StackAdjust.isImm() && "Expecting immediate value."); 608 // Adjust stack pointer. 609 int StackAdj = StackAdjust.getImm(); 610 int Delta = StackAdj - MaxTCRetDelta; 611 assert((Delta >= 0) && "Delta must be positive"); 612 if (MaxTCRetDelta>0) 613 FrameSize += (StackAdj +Delta); 614 else 615 FrameSize += StackAdj; 616 } 617 618 if (FrameSize) { 619 // The loaded (or persistent) stack pointer value is offset by the 'stwu' 620 // on entry to the function. Add this offset back now. 621 if (!isPPC64) { 622 // If this function contained a fastcc call and GuaranteedTailCallOpt is 623 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 624 // call which invalidates the stack pointer value in SP(0). So we use the 625 // value of R31 in this case. 626 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 627 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 628 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 629 .addReg(PPC::R31).addImm(FrameSize); 630 } else if(FI->hasFastCall()) { 631 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 632 .addImm(FrameSize >> 16); 633 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 634 .addReg(PPC::R0, RegState::Kill) 635 .addImm(FrameSize & 0xFFFF); 636 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 637 .addReg(PPC::R1) 638 .addReg(PPC::R31) 639 .addReg(PPC::R0); 640 } else if (isInt<16>(FrameSize) && 641 (!ALIGN_STACK || TargetAlign >= MaxAlign) && 642 !MFI->hasVarSizedObjects()) { 643 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 644 .addReg(PPC::R1).addImm(FrameSize); 645 } else { 646 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 647 .addImm(0).addReg(PPC::R1); 648 } 649 } else { 650 if (FI->hasFastCall() && isInt<16>(FrameSize)) { 651 assert(hasFP(MF) && "Expecting a valid the frame pointer."); 652 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 653 .addReg(PPC::X31).addImm(FrameSize); 654 } else if(FI->hasFastCall()) { 655 BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 656 .addImm(FrameSize >> 16); 657 BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 658 .addReg(PPC::X0, RegState::Kill) 659 .addImm(FrameSize & 0xFFFF); 660 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 661 .addReg(PPC::X1) 662 .addReg(PPC::X31) 663 .addReg(PPC::X0); 664 } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 665 !MFI->hasVarSizedObjects()) { 666 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 667 .addReg(PPC::X1).addImm(FrameSize); 668 } else { 669 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 670 .addImm(0).addReg(PPC::X1); 671 } 672 } 673 } 674 675 if (isPPC64) { 676 if (MustSaveLR) 677 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 678 .addImm(LROffset/4).addReg(PPC::X1); 679 680 if (HasFP) 681 BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 682 .addImm(FPOffset/4).addReg(PPC::X1); 683 684 if (MustSaveLR) 685 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 686 } else { 687 if (MustSaveLR) 688 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 689 .addImm(LROffset).addReg(PPC::R1); 690 691 if (HasFP) 692 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 693 .addImm(FPOffset).addReg(PPC::R1); 694 695 if (MustSaveLR) 696 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 697 } 698 699 // Callee pop calling convention. Pop parameter/linkage area. Used for tail 700 // call optimization 701 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 702 MF.getFunction()->getCallingConv() == CallingConv::Fast) { 703 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 704 unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 705 unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 706 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 707 unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 708 unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 709 unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 710 unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 711 unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 712 713 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 714 BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 715 .addReg(StackReg).addImm(CallerAllocatedAmt); 716 } else { 717 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 718 .addImm(CallerAllocatedAmt >> 16); 719 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 720 .addReg(TmpReg, RegState::Kill) 721 .addImm(CallerAllocatedAmt & 0xFFFF); 722 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 723 .addReg(StackReg) 724 .addReg(FPReg) 725 .addReg(TmpReg); 726 } 727 } else if (RetOpcode == PPC::TCRETURNdi) { 728 MBBI = MBB.getLastNonDebugInstr(); 729 MachineOperand &JumpTarget = MBBI->getOperand(0); 730 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 731 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 732 } else if (RetOpcode == PPC::TCRETURNri) { 733 MBBI = MBB.getLastNonDebugInstr(); 734 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 735 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 736 } else if (RetOpcode == PPC::TCRETURNai) { 737 MBBI = MBB.getLastNonDebugInstr(); 738 MachineOperand &JumpTarget = MBBI->getOperand(0); 739 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 740 } else if (RetOpcode == PPC::TCRETURNdi8) { 741 MBBI = MBB.getLastNonDebugInstr(); 742 MachineOperand &JumpTarget = MBBI->getOperand(0); 743 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 744 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 745 } else if (RetOpcode == PPC::TCRETURNri8) { 746 MBBI = MBB.getLastNonDebugInstr(); 747 assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 748 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 749 } else if (RetOpcode == PPC::TCRETURNai8) { 750 MBBI = MBB.getLastNonDebugInstr(); 751 MachineOperand &JumpTarget = MBBI->getOperand(0); 752 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 753 } 754} 755 756/// MustSaveLR - Return true if this function requires that we save the LR 757/// register onto the stack in the prolog and restore it in the epilog of the 758/// function. 759static bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 760 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 761 762 // We need a save/restore of LR if there is any def of LR (which is 763 // defined by calls, including the PIC setup sequence), or if there is 764 // some use of the LR stack slot (e.g. for builtin_return_address). 765 // (LR comes in 32 and 64 bit versions.) 766 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 767 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 768} 769 770void 771PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 772 RegScavenger *RS) const { 773 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 774 775 // Save and clear the LR state. 776 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 777 unsigned LR = RegInfo->getRARegister(); 778 FI->setMustSaveLR(MustSaveLR(MF, LR)); 779 MF.getRegInfo().setPhysRegUnused(LR); 780 781 // Save R31 if necessary 782 int FPSI = FI->getFramePointerSaveIndex(); 783 bool isPPC64 = Subtarget.isPPC64(); 784 bool isDarwinABI = Subtarget.isDarwinABI(); 785 MachineFrameInfo *MFI = MF.getFrameInfo(); 786 787 // If the frame pointer save index hasn't been defined yet. 788 if (!FPSI && needsFP(MF)) { 789 // Find out what the fix offset of the frame pointer save area. 790 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 791 // Allocate the frame index for frame pointer save area. 792 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 793 // Save the result. 794 FI->setFramePointerSaveIndex(FPSI); 795 } 796 797 // Reserve stack space to move the linkage area to in case of a tail call. 798 int TCSPDelta = 0; 799 if (MF.getTarget().Options.GuaranteedTailCallOpt && 800 (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 801 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 802 } 803 804 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 805 // a large stack, which will require scavenging a register to materialize a 806 // large offset. 807 // FIXME: this doesn't actually check stack size, so is a bit pessimistic 808 // FIXME: doesn't detect whether or not we need to spill vXX, which requires 809 // r0 for now. 810 811 if (RegInfo->requiresRegisterScavenging(MF)) 812 if (needsFP(MF) || spillsCR(MF)) { 813 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 814 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 815 const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 816 RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 817 RC->getAlignment(), 818 false)); 819 } 820} 821 822void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) 823 const { 824 // Early exit if not using the SVR4 ABI. 825 if (!Subtarget.isSVR4ABI()) 826 return; 827 828 // Get callee saved register information. 829 MachineFrameInfo *FFI = MF.getFrameInfo(); 830 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 831 832 // Early exit if no callee saved registers are modified! 833 if (CSI.empty() && !needsFP(MF)) { 834 return; 835 } 836 837 unsigned MinGPR = PPC::R31; 838 unsigned MinG8R = PPC::X31; 839 unsigned MinFPR = PPC::F31; 840 unsigned MinVR = PPC::V31; 841 842 bool HasGPSaveArea = false; 843 bool HasG8SaveArea = false; 844 bool HasFPSaveArea = false; 845 bool HasVRSAVESaveArea = false; 846 bool HasVRSaveArea = false; 847 848 SmallVector<CalleeSavedInfo, 18> GPRegs; 849 SmallVector<CalleeSavedInfo, 18> G8Regs; 850 SmallVector<CalleeSavedInfo, 18> FPRegs; 851 SmallVector<CalleeSavedInfo, 18> VRegs; 852 853 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 854 unsigned Reg = CSI[i].getReg(); 855 if (PPC::GPRCRegClass.contains(Reg)) { 856 HasGPSaveArea = true; 857 858 GPRegs.push_back(CSI[i]); 859 860 if (Reg < MinGPR) { 861 MinGPR = Reg; 862 } 863 } else if (PPC::G8RCRegClass.contains(Reg)) { 864 HasG8SaveArea = true; 865 866 G8Regs.push_back(CSI[i]); 867 868 if (Reg < MinG8R) { 869 MinG8R = Reg; 870 } 871 } else if (PPC::F8RCRegClass.contains(Reg)) { 872 HasFPSaveArea = true; 873 874 FPRegs.push_back(CSI[i]); 875 876 if (Reg < MinFPR) { 877 MinFPR = Reg; 878 } 879 } else if (PPC::CRBITRCRegClass.contains(Reg) || 880 PPC::CRRCRegClass.contains(Reg)) { 881 ; // do nothing, as we already know whether CRs are spilled 882 } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 883 HasVRSAVESaveArea = true; 884 } else if (PPC::VRRCRegClass.contains(Reg)) { 885 HasVRSaveArea = true; 886 887 VRegs.push_back(CSI[i]); 888 889 if (Reg < MinVR) { 890 MinVR = Reg; 891 } 892 } else { 893 llvm_unreachable("Unknown RegisterClass!"); 894 } 895 } 896 897 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 898 899 int64_t LowerBound = 0; 900 901 // Take into account stack space reserved for tail calls. 902 int TCSPDelta = 0; 903 if (MF.getTarget().Options.GuaranteedTailCallOpt && 904 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 905 LowerBound = TCSPDelta; 906 } 907 908 // The Floating-point register save area is right below the back chain word 909 // of the previous stack frame. 910 if (HasFPSaveArea) { 911 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 912 int FI = FPRegs[i].getFrameIdx(); 913 914 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 915 } 916 917 LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8; 918 } 919 920 // Check whether the frame pointer register is allocated. If so, make sure it 921 // is spilled to the correct offset. 922 if (needsFP(MF)) { 923 HasGPSaveArea = true; 924 925 int FI = PFI->getFramePointerSaveIndex(); 926 assert(FI && "No Frame Pointer Save Slot!"); 927 928 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 929 } 930 931 // General register save area starts right below the Floating-point 932 // register save area. 933 if (HasGPSaveArea || HasG8SaveArea) { 934 // Move general register save area spill slots down, taking into account 935 // the size of the Floating-point register save area. 936 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 937 int FI = GPRegs[i].getFrameIdx(); 938 939 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 940 } 941 942 // Move general register save area spill slots down, taking into account 943 // the size of the Floating-point register save area. 944 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 945 int FI = G8Regs[i].getFrameIdx(); 946 947 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 948 } 949 950 unsigned MinReg = 951 std::min<unsigned>(getPPCRegisterNumbering(MinGPR), 952 getPPCRegisterNumbering(MinG8R)); 953 954 if (Subtarget.isPPC64()) { 955 LowerBound -= (31 - MinReg + 1) * 8; 956 } else { 957 LowerBound -= (31 - MinReg + 1) * 4; 958 } 959 } 960 961 // For 32-bit only, the CR save area is below the general register 962 // save area. For 64-bit SVR4, the CR save area is addressed relative 963 // to the stack pointer and hence does not need an adjustment here. 964 // Only CR2 (the first nonvolatile spilled) has an associated frame 965 // index so that we have a single uniform save area. 966 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) { 967 // Adjust the frame index of the CR spill slot. 968 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 969 unsigned Reg = CSI[i].getReg(); 970 971 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2) 972 // Leave Darwin logic as-is. 973 || (!Subtarget.isSVR4ABI() && 974 (PPC::CRBITRCRegClass.contains(Reg) || 975 PPC::CRRCRegClass.contains(Reg)))) { 976 int FI = CSI[i].getFrameIdx(); 977 978 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 979 } 980 } 981 982 LowerBound -= 4; // The CR save area is always 4 bytes long. 983 } 984 985 if (HasVRSAVESaveArea) { 986 // FIXME SVR4: Is it actually possible to have multiple elements in CSI 987 // which have the VRSAVE register class? 988 // Adjust the frame index of the VRSAVE spill slot. 989 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 990 unsigned Reg = CSI[i].getReg(); 991 992 if (PPC::VRSAVERCRegClass.contains(Reg)) { 993 int FI = CSI[i].getFrameIdx(); 994 995 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 996 } 997 } 998 999 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 1000 } 1001 1002 if (HasVRSaveArea) { 1003 // Insert alignment padding, we need 16-byte alignment. 1004 LowerBound = (LowerBound - 15) & ~(15); 1005 1006 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 1007 int FI = VRegs[i].getFrameIdx(); 1008 1009 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 1010 } 1011 } 1012} 1013 1014bool 1015PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB, 1016 MachineBasicBlock::iterator MI, 1017 const std::vector<CalleeSavedInfo> &CSI, 1018 const TargetRegisterInfo *TRI) const { 1019 1020 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1021 // Return false otherwise to maintain pre-existing behavior. 1022 if (!Subtarget.isSVR4ABI()) 1023 return false; 1024 1025 MachineFunction *MF = MBB.getParent(); 1026 const PPCInstrInfo &TII = 1027 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1028 DebugLoc DL; 1029 bool CRSpilled = false; 1030 1031 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1032 unsigned Reg = CSI[i].getReg(); 1033 // CR2 through CR4 are the nonvolatile CR fields. 1034 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4; 1035 1036 if (CRSpilled && IsCRField) 1037 continue; 1038 1039 // Add the callee-saved register as live-in; it's killed at the spill. 1040 MBB.addLiveIn(Reg); 1041 1042 // Insert the spill to the stack frame. 1043 if (IsCRField) { 1044 CRSpilled = true; 1045 // The first time we see a CR field, store the whole CR into the 1046 // save slot via GPR12 (available in the prolog for 32- and 64-bit). 1047 if (Subtarget.isPPC64()) { 1048 // 64-bit: SP+8 1049 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::X12)); 1050 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::STW)) 1051 .addReg(PPC::X12, 1052 getKillRegState(true)) 1053 .addImm(8) 1054 .addReg(PPC::X1)); 1055 } else { 1056 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have 1057 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot. 1058 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)); 1059 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW)) 1060 .addReg(PPC::R12, 1061 getKillRegState(true)), 1062 CSI[i].getFrameIdx())); 1063 } 1064 1065 // Record that we spill the CR in this function. 1066 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>(); 1067 FuncInfo->setSpillsCR(); 1068 } else { 1069 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1070 TII.storeRegToStackSlot(MBB, MI, Reg, true, 1071 CSI[i].getFrameIdx(), RC, TRI); 1072 } 1073 } 1074 return true; 1075} 1076 1077static void 1078restoreCRs(bool isPPC64, bool CR2Spilled, bool CR3Spilled, bool CR4Spilled, 1079 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, 1080 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) { 1081 1082 MachineFunction *MF = MBB.getParent(); 1083 const PPCInstrInfo &TII = 1084 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1085 DebugLoc DL; 1086 unsigned RestoreOp, MoveReg; 1087 1088 if (isPPC64) { 1089 // 64-bit: SP+8 1090 MBB.insert(MI, BuildMI(*MF, DL, TII.get(PPC::LWZ), PPC::X12) 1091 .addImm(8) 1092 .addReg(PPC::X1)); 1093 RestoreOp = PPC::MTCRF8; 1094 MoveReg = PPC::X12; 1095 } else { 1096 // 32-bit: FP-relative 1097 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ), 1098 PPC::R12), 1099 CSI[CSIIndex].getFrameIdx())); 1100 RestoreOp = PPC::MTCRF; 1101 MoveReg = PPC::R12; 1102 } 1103 1104 if (CR2Spilled) 1105 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2) 1106 .addReg(MoveReg)); 1107 1108 if (CR3Spilled) 1109 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3) 1110 .addReg(MoveReg)); 1111 1112 if (CR4Spilled) 1113 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4) 1114 .addReg(MoveReg)); 1115} 1116 1117bool 1118PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB, 1119 MachineBasicBlock::iterator MI, 1120 const std::vector<CalleeSavedInfo> &CSI, 1121 const TargetRegisterInfo *TRI) const { 1122 1123 // Currently, this function only handles SVR4 32- and 64-bit ABIs. 1124 // Return false otherwise to maintain pre-existing behavior. 1125 if (!Subtarget.isSVR4ABI()) 1126 return false; 1127 1128 MachineFunction *MF = MBB.getParent(); 1129 const PPCInstrInfo &TII = 1130 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo()); 1131 bool CR2Spilled = false; 1132 bool CR3Spilled = false; 1133 bool CR4Spilled = false; 1134 unsigned CSIIndex = 0; 1135 1136 // Initialize insertion-point logic; we will be restoring in reverse 1137 // order of spill. 1138 MachineBasicBlock::iterator I = MI, BeforeI = I; 1139 bool AtStart = I == MBB.begin(); 1140 1141 if (!AtStart) 1142 --BeforeI; 1143 1144 for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 1145 unsigned Reg = CSI[i].getReg(); 1146 1147 if (Reg == PPC::CR2) { 1148 CR2Spilled = true; 1149 // The spill slot is associated only with CR2, which is the 1150 // first nonvolatile spilled. Save it here. 1151 CSIIndex = i; 1152 continue; 1153 } else if (Reg == PPC::CR3) { 1154 CR3Spilled = true; 1155 continue; 1156 } else if (Reg == PPC::CR4) { 1157 CR4Spilled = true; 1158 continue; 1159 } else { 1160 // When we first encounter a non-CR register after seeing at 1161 // least one CR register, restore all spilled CRs together. 1162 if ((CR2Spilled || CR3Spilled || CR4Spilled) 1163 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) { 1164 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled, 1165 MBB, I, CSI, CSIIndex); 1166 CR2Spilled = CR3Spilled = CR4Spilled = false; 1167 } 1168 1169 // Default behavior for non-CR saves. 1170 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); 1171 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(), 1172 RC, TRI); 1173 assert(I != MBB.begin() && 1174 "loadRegFromStackSlot didn't insert any code!"); 1175 } 1176 1177 // Insert in reverse order. 1178 if (AtStart) 1179 I = MBB.begin(); 1180 else { 1181 I = BeforeI; 1182 ++I; 1183 } 1184 } 1185 1186 // If we haven't yet spilled the CRs, do so now. 1187 if (CR2Spilled || CR3Spilled || CR4Spilled) 1188 restoreCRs(Subtarget.isPPC64(), CR2Spilled, CR3Spilled, CR4Spilled, 1189 MBB, I, CSI, CSIIndex); 1190 1191 return true; 1192} 1193 1194