PPCFrameLowering.cpp revision 239462
1234353Sdim//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===// 2218885Sdim// 3218885Sdim// The LLVM Compiler Infrastructure 4218885Sdim// 5218885Sdim// This file is distributed under the University of Illinois Open Source 6218885Sdim// License. See LICENSE.TXT for details. 7218885Sdim// 8218885Sdim//===----------------------------------------------------------------------===// 9218885Sdim// 10218885Sdim// This file contains the PPC implementation of TargetFrameLowering class. 11218885Sdim// 12218885Sdim//===----------------------------------------------------------------------===// 13218885Sdim 14218885Sdim#include "PPCFrameLowering.h" 15218885Sdim#include "PPCInstrInfo.h" 16218885Sdim#include "PPCMachineFunctionInfo.h" 17218885Sdim#include "llvm/Function.h" 18218885Sdim#include "llvm/CodeGen/MachineFrameInfo.h" 19218885Sdim#include "llvm/CodeGen/MachineFunction.h" 20218885Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 21218885Sdim#include "llvm/CodeGen/MachineModuleInfo.h" 22218885Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 23218885Sdim#include "llvm/CodeGen/RegisterScavenging.h" 24218885Sdim#include "llvm/Target/TargetOptions.h" 25218885Sdim 26218885Sdimusing namespace llvm; 27218885Sdim 28218885Sdim// FIXME This disables some code that aligns the stack to a boundary bigger than 29218885Sdim// the default (16 bytes on Darwin) when there is a stack local of greater 30218885Sdim// alignment. This does not currently work, because the delta between old and 31218885Sdim// new stack pointers is added to offsets that reference incoming parameters 32218885Sdim// after the prolog is generated, and the code that does that doesn't handle a 33218885Sdim// variable delta. You don't want to do that anyway; a better approach is to 34218885Sdim// reserve another register that retains to the incoming stack pointer, and 35218885Sdim// reference parameters relative to that. 36218885Sdim#define ALIGN_STACK 0 37218885Sdim 38218885Sdim 39218885Sdim/// VRRegNo - Map from a numbered VR register to its enum value. 40218885Sdim/// 41234353Sdimstatic const uint16_t VRRegNo[] = { 42218885Sdim PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 , 43218885Sdim PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15, 44218885Sdim PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23, 45218885Sdim PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31 46218885Sdim}; 47218885Sdim 48218885Sdim/// RemoveVRSaveCode - We have found that this function does not need any code 49218885Sdim/// to manipulate the VRSAVE register, even though it uses vector registers. 50218885Sdim/// This can happen when the only registers used are known to be live in or out 51218885Sdim/// of the function. Remove all of the VRSAVE related code from the function. 52218885Sdimstatic void RemoveVRSaveCode(MachineInstr *MI) { 53218885Sdim MachineBasicBlock *Entry = MI->getParent(); 54218885Sdim MachineFunction *MF = Entry->getParent(); 55218885Sdim 56218885Sdim // We know that the MTVRSAVE instruction immediately follows MI. Remove it. 57218885Sdim MachineBasicBlock::iterator MBBI = MI; 58218885Sdim ++MBBI; 59218885Sdim assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE); 60218885Sdim MBBI->eraseFromParent(); 61218885Sdim 62218885Sdim bool RemovedAllMTVRSAVEs = true; 63218885Sdim // See if we can find and remove the MTVRSAVE instruction from all of the 64218885Sdim // epilog blocks. 65218885Sdim for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) { 66218885Sdim // If last instruction is a return instruction, add an epilogue 67234353Sdim if (!I->empty() && I->back().isReturn()) { 68218885Sdim bool FoundIt = false; 69218885Sdim for (MBBI = I->end(); MBBI != I->begin(); ) { 70218885Sdim --MBBI; 71218885Sdim if (MBBI->getOpcode() == PPC::MTVRSAVE) { 72218885Sdim MBBI->eraseFromParent(); // remove it. 73218885Sdim FoundIt = true; 74218885Sdim break; 75218885Sdim } 76218885Sdim } 77218885Sdim RemovedAllMTVRSAVEs &= FoundIt; 78218885Sdim } 79218885Sdim } 80218885Sdim 81218885Sdim // If we found and removed all MTVRSAVE instructions, remove the read of 82218885Sdim // VRSAVE as well. 83218885Sdim if (RemovedAllMTVRSAVEs) { 84218885Sdim MBBI = MI; 85218885Sdim assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?"); 86218885Sdim --MBBI; 87218885Sdim assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?"); 88218885Sdim MBBI->eraseFromParent(); 89218885Sdim } 90218885Sdim 91218885Sdim // Finally, nuke the UPDATE_VRSAVE. 92218885Sdim MI->eraseFromParent(); 93218885Sdim} 94218885Sdim 95218885Sdim// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the 96218885Sdim// instruction selector. Based on the vector registers that have been used, 97218885Sdim// transform this into the appropriate ORI instruction. 98218885Sdimstatic void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) { 99218885Sdim MachineFunction *MF = MI->getParent()->getParent(); 100218885Sdim DebugLoc dl = MI->getDebugLoc(); 101218885Sdim 102218885Sdim unsigned UsedRegMask = 0; 103218885Sdim for (unsigned i = 0; i != 32; ++i) 104218885Sdim if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i])) 105218885Sdim UsedRegMask |= 1 << (31-i); 106218885Sdim 107218885Sdim // Live in and live out values already must be in the mask, so don't bother 108218885Sdim // marking them. 109218885Sdim for (MachineRegisterInfo::livein_iterator 110218885Sdim I = MF->getRegInfo().livein_begin(), 111218885Sdim E = MF->getRegInfo().livein_end(); I != E; ++I) { 112226633Sdim unsigned RegNo = getPPCRegisterNumbering(I->first); 113218885Sdim if (VRRegNo[RegNo] == I->first) // If this really is a vector reg. 114218885Sdim UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 115218885Sdim } 116218885Sdim for (MachineRegisterInfo::liveout_iterator 117218885Sdim I = MF->getRegInfo().liveout_begin(), 118218885Sdim E = MF->getRegInfo().liveout_end(); I != E; ++I) { 119226633Sdim unsigned RegNo = getPPCRegisterNumbering(*I); 120218885Sdim if (VRRegNo[RegNo] == *I) // If this really is a vector reg. 121218885Sdim UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked. 122218885Sdim } 123218885Sdim 124218885Sdim // If no registers are used, turn this into a copy. 125218885Sdim if (UsedRegMask == 0) { 126218885Sdim // Remove all VRSAVE code. 127218885Sdim RemoveVRSaveCode(MI); 128218885Sdim return; 129218885Sdim } 130218885Sdim 131218885Sdim unsigned SrcReg = MI->getOperand(1).getReg(); 132218885Sdim unsigned DstReg = MI->getOperand(0).getReg(); 133218885Sdim 134218885Sdim if ((UsedRegMask & 0xFFFF) == UsedRegMask) { 135218885Sdim if (DstReg != SrcReg) 136218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 137218885Sdim .addReg(SrcReg) 138218885Sdim .addImm(UsedRegMask); 139218885Sdim else 140218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 141218885Sdim .addReg(SrcReg, RegState::Kill) 142218885Sdim .addImm(UsedRegMask); 143218885Sdim } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) { 144218885Sdim if (DstReg != SrcReg) 145218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 146218885Sdim .addReg(SrcReg) 147218885Sdim .addImm(UsedRegMask >> 16); 148218885Sdim else 149218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 150218885Sdim .addReg(SrcReg, RegState::Kill) 151218885Sdim .addImm(UsedRegMask >> 16); 152218885Sdim } else { 153218885Sdim if (DstReg != SrcReg) 154218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 155218885Sdim .addReg(SrcReg) 156218885Sdim .addImm(UsedRegMask >> 16); 157218885Sdim else 158218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) 159218885Sdim .addReg(SrcReg, RegState::Kill) 160218885Sdim .addImm(UsedRegMask >> 16); 161218885Sdim 162218885Sdim BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) 163218885Sdim .addReg(DstReg, RegState::Kill) 164218885Sdim .addImm(UsedRegMask & 0xFFFF); 165218885Sdim } 166218885Sdim 167218885Sdim // Remove the old UPDATE_VRSAVE instruction. 168218885Sdim MI->eraseFromParent(); 169218885Sdim} 170218885Sdim 171218885Sdim/// determineFrameLayout - Determine the size of the frame and maximum call 172218885Sdim/// frame size. 173218885Sdimvoid PPCFrameLowering::determineFrameLayout(MachineFunction &MF) const { 174218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 175218885Sdim 176218885Sdim // Get the number of bytes to allocate from the FrameInfo 177218885Sdim unsigned FrameSize = MFI->getStackSize(); 178218885Sdim 179218885Sdim // Get the alignments provided by the target, and the maximum alignment 180218885Sdim // (if any) of the fixed frame objects. 181218885Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 182218885Sdim unsigned TargetAlign = getStackAlignment(); 183218885Sdim unsigned AlignMask = TargetAlign - 1; // 184218885Sdim 185218885Sdim // If we are a leaf function, and use up to 224 bytes of stack space, 186218885Sdim // don't have a frame pointer, calls, or dynamic alloca then we do not need 187218885Sdim // to adjust the stack pointer (we fit in the Red Zone). 188218885Sdim bool DisableRedZone = MF.getFunction()->hasFnAttr(Attribute::NoRedZone); 189218885Sdim // FIXME SVR4 The 32-bit SVR4 ABI has no red zone. 190218885Sdim if (!DisableRedZone && 191218885Sdim FrameSize <= 224 && // Fits in red zone. 192218885Sdim !MFI->hasVarSizedObjects() && // No dynamic alloca. 193218885Sdim !MFI->adjustsStack() && // No calls. 194218885Sdim (!ALIGN_STACK || MaxAlign <= TargetAlign)) { // No special alignment. 195218885Sdim // No need for frame 196218885Sdim MFI->setStackSize(0); 197218885Sdim return; 198218885Sdim } 199218885Sdim 200218885Sdim // Get the maximum call frame size of all the calls. 201218885Sdim unsigned maxCallFrameSize = MFI->getMaxCallFrameSize(); 202218885Sdim 203218885Sdim // Maximum call frame needs to be at least big enough for linkage and 8 args. 204218885Sdim unsigned minCallFrameSize = getMinCallFrameSize(Subtarget.isPPC64(), 205218885Sdim Subtarget.isDarwinABI()); 206218885Sdim maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize); 207218885Sdim 208218885Sdim // If we have dynamic alloca then maxCallFrameSize needs to be aligned so 209218885Sdim // that allocations will be aligned. 210218885Sdim if (MFI->hasVarSizedObjects()) 211218885Sdim maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask; 212218885Sdim 213218885Sdim // Update maximum call frame size. 214218885Sdim MFI->setMaxCallFrameSize(maxCallFrameSize); 215218885Sdim 216218885Sdim // Include call frame size in total. 217218885Sdim FrameSize += maxCallFrameSize; 218218885Sdim 219218885Sdim // Make sure the frame is aligned. 220218885Sdim FrameSize = (FrameSize + AlignMask) & ~AlignMask; 221218885Sdim 222218885Sdim // Update frame info. 223218885Sdim MFI->setStackSize(FrameSize); 224218885Sdim} 225218885Sdim 226218885Sdim// hasFP - Return true if the specified function actually has a dedicated frame 227218885Sdim// pointer register. 228218885Sdimbool PPCFrameLowering::hasFP(const MachineFunction &MF) const { 229218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 230218885Sdim // FIXME: This is pretty much broken by design: hasFP() might be called really 231218885Sdim // early, before the stack layout was calculated and thus hasFP() might return 232218885Sdim // true or false here depending on the time of call. 233218885Sdim return (MFI->getStackSize()) && needsFP(MF); 234218885Sdim} 235218885Sdim 236218885Sdim// needsFP - Return true if the specified function should have a dedicated frame 237218885Sdim// pointer register. This is true if the function has variable sized allocas or 238218885Sdim// if frame pointer elimination is disabled. 239218885Sdimbool PPCFrameLowering::needsFP(const MachineFunction &MF) const { 240218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 241218885Sdim 242218885Sdim // Naked functions have no stack frame pushed, so we don't have a frame 243218885Sdim // pointer. 244218885Sdim if (MF.getFunction()->hasFnAttr(Attribute::Naked)) 245218885Sdim return false; 246218885Sdim 247234353Sdim return MF.getTarget().Options.DisableFramePointerElim(MF) || 248234353Sdim MFI->hasVarSizedObjects() || 249234353Sdim (MF.getTarget().Options.GuaranteedTailCallOpt && 250234353Sdim MF.getInfo<PPCFunctionInfo>()->hasFastCall()); 251218885Sdim} 252218885Sdim 253218885Sdim 254218885Sdimvoid PPCFrameLowering::emitPrologue(MachineFunction &MF) const { 255218885Sdim MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB 256218885Sdim MachineBasicBlock::iterator MBBI = MBB.begin(); 257218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 258218885Sdim const PPCInstrInfo &TII = 259218885Sdim *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 260218885Sdim 261218885Sdim MachineModuleInfo &MMI = MF.getMMI(); 262218885Sdim DebugLoc dl; 263218885Sdim bool needsFrameMoves = MMI.hasDebugInfo() || 264223017Sdim MF.getFunction()->needsUnwindTableEntry(); 265218885Sdim 266218885Sdim // Prepare for frame info. 267218885Sdim MCSymbol *FrameLabel = 0; 268218885Sdim 269218885Sdim // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it, 270218885Sdim // process it. 271218885Sdim for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) { 272218885Sdim if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) { 273218885Sdim HandleVRSaveUpdate(MBBI, TII); 274218885Sdim break; 275218885Sdim } 276218885Sdim } 277218885Sdim 278218885Sdim // Move MBBI back to the beginning of the function. 279218885Sdim MBBI = MBB.begin(); 280218885Sdim 281218885Sdim // Work out frame sizes. 282218885Sdim // FIXME: determineFrameLayout() may change the frame size. This should be 283218885Sdim // moved upper, to some hook. 284218885Sdim determineFrameLayout(MF); 285218885Sdim unsigned FrameSize = MFI->getStackSize(); 286218885Sdim 287218885Sdim int NegFrameSize = -FrameSize; 288218885Sdim 289218885Sdim // Get processor type. 290218885Sdim bool isPPC64 = Subtarget.isPPC64(); 291218885Sdim // Get operating system 292218885Sdim bool isDarwinABI = Subtarget.isDarwinABI(); 293218885Sdim // Check if the link register (LR) must be saved. 294218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 295218885Sdim bool MustSaveLR = FI->mustSaveLR(); 296218885Sdim // Do we have a frame pointer for this function? 297218885Sdim bool HasFP = hasFP(MF); 298218885Sdim 299218885Sdim int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 300218885Sdim 301218885Sdim int FPOffset = 0; 302218885Sdim if (HasFP) { 303218885Sdim if (Subtarget.isSVR4ABI()) { 304218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 305218885Sdim int FPIndex = FI->getFramePointerSaveIndex(); 306218885Sdim assert(FPIndex && "No Frame Pointer Save Slot!"); 307218885Sdim FPOffset = FFI->getObjectOffset(FPIndex); 308218885Sdim } else { 309218885Sdim FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 310218885Sdim } 311218885Sdim } 312218885Sdim 313218885Sdim if (isPPC64) { 314218885Sdim if (MustSaveLR) 315218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR8), PPC::X0); 316218885Sdim 317218885Sdim if (HasFP) 318218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 319218885Sdim .addReg(PPC::X31) 320218885Sdim .addImm(FPOffset/4) 321218885Sdim .addReg(PPC::X1); 322218885Sdim 323218885Sdim if (MustSaveLR) 324218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STD)) 325218885Sdim .addReg(PPC::X0) 326218885Sdim .addImm(LROffset / 4) 327218885Sdim .addReg(PPC::X1); 328218885Sdim } else { 329218885Sdim if (MustSaveLR) 330218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MFLR), PPC::R0); 331218885Sdim 332218885Sdim if (HasFP) 333239462Sdim // FIXME: On PPC32 SVR4, FPOffset is negative and access to negative 334239462Sdim // offsets of R1 is not allowed. 335218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 336218885Sdim .addReg(PPC::R31) 337218885Sdim .addImm(FPOffset) 338218885Sdim .addReg(PPC::R1); 339218885Sdim 340218885Sdim if (MustSaveLR) 341218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STW)) 342218885Sdim .addReg(PPC::R0) 343218885Sdim .addImm(LROffset) 344218885Sdim .addReg(PPC::R1); 345218885Sdim } 346218885Sdim 347218885Sdim // Skip if a leaf routine. 348218885Sdim if (!FrameSize) return; 349218885Sdim 350218885Sdim // Get stack alignments. 351218885Sdim unsigned TargetAlign = getStackAlignment(); 352218885Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 353218885Sdim 354218885Sdim // Adjust stack pointer: r1 += NegFrameSize. 355218885Sdim // If there is a preferred stack alignment, align R1 now 356218885Sdim if (!isPPC64) { 357218885Sdim // PPC32. 358218885Sdim if (ALIGN_STACK && MaxAlign > TargetAlign) { 359218885Sdim assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 360218885Sdim "Invalid alignment!"); 361218885Sdim assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 362218885Sdim 363218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), PPC::R0) 364218885Sdim .addReg(PPC::R1) 365218885Sdim .addImm(0) 366218885Sdim .addImm(32 - Log2_32(MaxAlign)) 367218885Sdim .addImm(31); 368218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC) ,PPC::R0) 369218885Sdim .addReg(PPC::R0, RegState::Kill) 370218885Sdim .addImm(NegFrameSize); 371239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 372234353Sdim .addReg(PPC::R1, RegState::Kill) 373239462Sdim .addReg(PPC::R1) 374218885Sdim .addReg(PPC::R0); 375218885Sdim } else if (isInt<16>(NegFrameSize)) { 376218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STWU), PPC::R1) 377218885Sdim .addReg(PPC::R1) 378218885Sdim .addImm(NegFrameSize) 379218885Sdim .addReg(PPC::R1); 380218885Sdim } else { 381218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 382218885Sdim .addImm(NegFrameSize >> 16); 383218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 384218885Sdim .addReg(PPC::R0, RegState::Kill) 385218885Sdim .addImm(NegFrameSize & 0xFFFF); 386239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STWUX), PPC::R1) 387234353Sdim .addReg(PPC::R1, RegState::Kill) 388239462Sdim .addReg(PPC::R1) 389218885Sdim .addReg(PPC::R0); 390218885Sdim } 391218885Sdim } else { // PPC64. 392218885Sdim if (ALIGN_STACK && MaxAlign > TargetAlign) { 393218885Sdim assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) && 394218885Sdim "Invalid alignment!"); 395218885Sdim assert(isInt<16>(NegFrameSize) && "Unhandled stack size and alignment!"); 396218885Sdim 397218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), PPC::X0) 398218885Sdim .addReg(PPC::X1) 399218885Sdim .addImm(0) 400218885Sdim .addImm(64 - Log2_32(MaxAlign)); 401218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBFIC8), PPC::X0) 402218885Sdim .addReg(PPC::X0) 403218885Sdim .addImm(NegFrameSize); 404239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 405234353Sdim .addReg(PPC::X1, RegState::Kill) 406239462Sdim .addReg(PPC::X1) 407218885Sdim .addReg(PPC::X0); 408218885Sdim } else if (isInt<16>(NegFrameSize)) { 409218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STDU), PPC::X1) 410218885Sdim .addReg(PPC::X1) 411218885Sdim .addImm(NegFrameSize / 4) 412218885Sdim .addReg(PPC::X1); 413218885Sdim } else { 414218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 415218885Sdim .addImm(NegFrameSize >> 16); 416218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 417218885Sdim .addReg(PPC::X0, RegState::Kill) 418218885Sdim .addImm(NegFrameSize & 0xFFFF); 419239462Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::STDUX), PPC::X1) 420234353Sdim .addReg(PPC::X1, RegState::Kill) 421239462Sdim .addReg(PPC::X1) 422218885Sdim .addReg(PPC::X0); 423218885Sdim } 424218885Sdim } 425218885Sdim 426218885Sdim std::vector<MachineMove> &Moves = MMI.getFrameMoves(); 427218885Sdim 428218885Sdim // Add the "machine moves" for the instructions we generated above, but in 429218885Sdim // reverse order. 430218885Sdim if (needsFrameMoves) { 431218885Sdim // Mark effective beginning of when frame pointer becomes valid. 432218885Sdim FrameLabel = MMI.getContext().CreateTempSymbol(); 433218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(FrameLabel); 434218885Sdim 435218885Sdim // Show update of SP. 436218885Sdim if (NegFrameSize) { 437218885Sdim MachineLocation SPDst(MachineLocation::VirtualFP); 438218885Sdim MachineLocation SPSrc(MachineLocation::VirtualFP, NegFrameSize); 439218885Sdim Moves.push_back(MachineMove(FrameLabel, SPDst, SPSrc)); 440218885Sdim } else { 441218885Sdim MachineLocation SP(isPPC64 ? PPC::X31 : PPC::R31); 442218885Sdim Moves.push_back(MachineMove(FrameLabel, SP, SP)); 443218885Sdim } 444218885Sdim 445218885Sdim if (HasFP) { 446218885Sdim MachineLocation FPDst(MachineLocation::VirtualFP, FPOffset); 447218885Sdim MachineLocation FPSrc(isPPC64 ? PPC::X31 : PPC::R31); 448218885Sdim Moves.push_back(MachineMove(FrameLabel, FPDst, FPSrc)); 449218885Sdim } 450218885Sdim 451218885Sdim if (MustSaveLR) { 452218885Sdim MachineLocation LRDst(MachineLocation::VirtualFP, LROffset); 453218885Sdim MachineLocation LRSrc(isPPC64 ? PPC::LR8 : PPC::LR); 454218885Sdim Moves.push_back(MachineMove(FrameLabel, LRDst, LRSrc)); 455218885Sdim } 456218885Sdim } 457218885Sdim 458218885Sdim MCSymbol *ReadyLabel = 0; 459218885Sdim 460218885Sdim // If there is a frame pointer, copy R1 into R31 461218885Sdim if (HasFP) { 462218885Sdim if (!isPPC64) { 463218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::OR), PPC::R31) 464218885Sdim .addReg(PPC::R1) 465218885Sdim .addReg(PPC::R1); 466218885Sdim } else { 467218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::OR8), PPC::X31) 468218885Sdim .addReg(PPC::X1) 469218885Sdim .addReg(PPC::X1); 470218885Sdim } 471218885Sdim 472218885Sdim if (needsFrameMoves) { 473218885Sdim ReadyLabel = MMI.getContext().CreateTempSymbol(); 474218885Sdim 475218885Sdim // Mark effective beginning of when frame pointer is ready. 476218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::PROLOG_LABEL)).addSym(ReadyLabel); 477218885Sdim 478218885Sdim MachineLocation FPDst(HasFP ? (isPPC64 ? PPC::X31 : PPC::R31) : 479218885Sdim (isPPC64 ? PPC::X1 : PPC::R1)); 480218885Sdim MachineLocation FPSrc(MachineLocation::VirtualFP); 481218885Sdim Moves.push_back(MachineMove(ReadyLabel, FPDst, FPSrc)); 482218885Sdim } 483218885Sdim } 484218885Sdim 485218885Sdim if (needsFrameMoves) { 486218885Sdim MCSymbol *Label = HasFP ? ReadyLabel : FrameLabel; 487218885Sdim 488218885Sdim // Add callee saved registers to move list. 489218885Sdim const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo(); 490218885Sdim for (unsigned I = 0, E = CSI.size(); I != E; ++I) { 491218885Sdim int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); 492218885Sdim unsigned Reg = CSI[I].getReg(); 493218885Sdim if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue; 494223017Sdim 495223017Sdim // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just 496223017Sdim // subregisters of CR2. We just need to emit a move of CR2. 497239462Sdim if (PPC::CRBITRCRegClass.contains(Reg)) 498223017Sdim continue; 499223017Sdim 500218885Sdim MachineLocation CSDst(MachineLocation::VirtualFP, Offset); 501218885Sdim MachineLocation CSSrc(Reg); 502218885Sdim Moves.push_back(MachineMove(Label, CSDst, CSSrc)); 503218885Sdim } 504218885Sdim } 505218885Sdim} 506218885Sdim 507218885Sdimvoid PPCFrameLowering::emitEpilogue(MachineFunction &MF, 508218885Sdim MachineBasicBlock &MBB) const { 509218885Sdim MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr(); 510218885Sdim assert(MBBI != MBB.end() && "Returning block has no terminator"); 511218885Sdim const PPCInstrInfo &TII = 512218885Sdim *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo()); 513218885Sdim 514218885Sdim unsigned RetOpcode = MBBI->getOpcode(); 515218885Sdim DebugLoc dl; 516218885Sdim 517218885Sdim assert((RetOpcode == PPC::BLR || 518218885Sdim RetOpcode == PPC::TCRETURNri || 519218885Sdim RetOpcode == PPC::TCRETURNdi || 520218885Sdim RetOpcode == PPC::TCRETURNai || 521218885Sdim RetOpcode == PPC::TCRETURNri8 || 522218885Sdim RetOpcode == PPC::TCRETURNdi8 || 523218885Sdim RetOpcode == PPC::TCRETURNai8) && 524218885Sdim "Can only insert epilog into returning blocks"); 525218885Sdim 526218885Sdim // Get alignment info so we know how to restore r1 527218885Sdim const MachineFrameInfo *MFI = MF.getFrameInfo(); 528218885Sdim unsigned TargetAlign = getStackAlignment(); 529218885Sdim unsigned MaxAlign = MFI->getMaxAlignment(); 530218885Sdim 531218885Sdim // Get the number of bytes allocated from the FrameInfo. 532218885Sdim int FrameSize = MFI->getStackSize(); 533218885Sdim 534218885Sdim // Get processor type. 535218885Sdim bool isPPC64 = Subtarget.isPPC64(); 536218885Sdim // Get operating system 537218885Sdim bool isDarwinABI = Subtarget.isDarwinABI(); 538218885Sdim // Check if the link register (LR) has been saved. 539218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 540218885Sdim bool MustSaveLR = FI->mustSaveLR(); 541218885Sdim // Do we have a frame pointer for this function? 542218885Sdim bool HasFP = hasFP(MF); 543218885Sdim 544218885Sdim int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI); 545218885Sdim 546218885Sdim int FPOffset = 0; 547218885Sdim if (HasFP) { 548218885Sdim if (Subtarget.isSVR4ABI()) { 549218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 550218885Sdim int FPIndex = FI->getFramePointerSaveIndex(); 551218885Sdim assert(FPIndex && "No Frame Pointer Save Slot!"); 552218885Sdim FPOffset = FFI->getObjectOffset(FPIndex); 553218885Sdim } else { 554218885Sdim FPOffset = PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI); 555218885Sdim } 556218885Sdim } 557218885Sdim 558218885Sdim bool UsesTCRet = RetOpcode == PPC::TCRETURNri || 559218885Sdim RetOpcode == PPC::TCRETURNdi || 560218885Sdim RetOpcode == PPC::TCRETURNai || 561218885Sdim RetOpcode == PPC::TCRETURNri8 || 562218885Sdim RetOpcode == PPC::TCRETURNdi8 || 563218885Sdim RetOpcode == PPC::TCRETURNai8; 564218885Sdim 565218885Sdim if (UsesTCRet) { 566218885Sdim int MaxTCRetDelta = FI->getTailCallSPDelta(); 567218885Sdim MachineOperand &StackAdjust = MBBI->getOperand(1); 568218885Sdim assert(StackAdjust.isImm() && "Expecting immediate value."); 569218885Sdim // Adjust stack pointer. 570218885Sdim int StackAdj = StackAdjust.getImm(); 571218885Sdim int Delta = StackAdj - MaxTCRetDelta; 572218885Sdim assert((Delta >= 0) && "Delta must be positive"); 573218885Sdim if (MaxTCRetDelta>0) 574218885Sdim FrameSize += (StackAdj +Delta); 575218885Sdim else 576218885Sdim FrameSize += StackAdj; 577218885Sdim } 578218885Sdim 579218885Sdim if (FrameSize) { 580218885Sdim // The loaded (or persistent) stack pointer value is offset by the 'stwu' 581218885Sdim // on entry to the function. Add this offset back now. 582218885Sdim if (!isPPC64) { 583218885Sdim // If this function contained a fastcc call and GuaranteedTailCallOpt is 584218885Sdim // enabled (=> hasFastCall()==true) the fastcc call might contain a tail 585218885Sdim // call which invalidates the stack pointer value in SP(0). So we use the 586218885Sdim // value of R31 in this case. 587218885Sdim if (FI->hasFastCall() && isInt<16>(FrameSize)) { 588218885Sdim assert(hasFP(MF) && "Expecting a valid the frame pointer."); 589218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 590218885Sdim .addReg(PPC::R31).addImm(FrameSize); 591218885Sdim } else if(FI->hasFastCall()) { 592218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS), PPC::R0) 593218885Sdim .addImm(FrameSize >> 16); 594218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI), PPC::R0) 595218885Sdim .addReg(PPC::R0, RegState::Kill) 596218885Sdim .addImm(FrameSize & 0xFFFF); 597218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD4)) 598218885Sdim .addReg(PPC::R1) 599218885Sdim .addReg(PPC::R31) 600218885Sdim .addReg(PPC::R0); 601218885Sdim } else if (isInt<16>(FrameSize) && 602218885Sdim (!ALIGN_STACK || TargetAlign >= MaxAlign) && 603218885Sdim !MFI->hasVarSizedObjects()) { 604218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), PPC::R1) 605218885Sdim .addReg(PPC::R1).addImm(FrameSize); 606218885Sdim } else { 607218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ),PPC::R1) 608218885Sdim .addImm(0).addReg(PPC::R1); 609218885Sdim } 610218885Sdim } else { 611218885Sdim if (FI->hasFastCall() && isInt<16>(FrameSize)) { 612218885Sdim assert(hasFP(MF) && "Expecting a valid the frame pointer."); 613218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 614218885Sdim .addReg(PPC::X31).addImm(FrameSize); 615218885Sdim } else if(FI->hasFastCall()) { 616218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LIS8), PPC::X0) 617218885Sdim .addImm(FrameSize >> 16); 618218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ORI8), PPC::X0) 619218885Sdim .addReg(PPC::X0, RegState::Kill) 620218885Sdim .addImm(FrameSize & 0xFFFF); 621218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADD8)) 622218885Sdim .addReg(PPC::X1) 623218885Sdim .addReg(PPC::X31) 624218885Sdim .addReg(PPC::X0); 625218885Sdim } else if (isInt<16>(FrameSize) && TargetAlign >= MaxAlign && 626218885Sdim !MFI->hasVarSizedObjects()) { 627218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI8), PPC::X1) 628218885Sdim .addReg(PPC::X1).addImm(FrameSize); 629218885Sdim } else { 630218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X1) 631218885Sdim .addImm(0).addReg(PPC::X1); 632218885Sdim } 633218885Sdim } 634218885Sdim } 635218885Sdim 636218885Sdim if (isPPC64) { 637218885Sdim if (MustSaveLR) 638218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X0) 639218885Sdim .addImm(LROffset/4).addReg(PPC::X1); 640218885Sdim 641218885Sdim if (HasFP) 642218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LD), PPC::X31) 643218885Sdim .addImm(FPOffset/4).addReg(PPC::X1); 644218885Sdim 645218885Sdim if (MustSaveLR) 646218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR8)).addReg(PPC::X0); 647218885Sdim } else { 648218885Sdim if (MustSaveLR) 649218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R0) 650218885Sdim .addImm(LROffset).addReg(PPC::R1); 651218885Sdim 652218885Sdim if (HasFP) 653218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ), PPC::R31) 654218885Sdim .addImm(FPOffset).addReg(PPC::R1); 655218885Sdim 656218885Sdim if (MustSaveLR) 657218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::MTLR)).addReg(PPC::R0); 658218885Sdim } 659218885Sdim 660218885Sdim // Callee pop calling convention. Pop parameter/linkage area. Used for tail 661218885Sdim // call optimization 662234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR && 663218885Sdim MF.getFunction()->getCallingConv() == CallingConv::Fast) { 664218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 665218885Sdim unsigned CallerAllocatedAmt = FI->getMinReservedArea(); 666218885Sdim unsigned StackReg = isPPC64 ? PPC::X1 : PPC::R1; 667218885Sdim unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31; 668218885Sdim unsigned TmpReg = isPPC64 ? PPC::X0 : PPC::R0; 669218885Sdim unsigned ADDIInstr = isPPC64 ? PPC::ADDI8 : PPC::ADDI; 670218885Sdim unsigned ADDInstr = isPPC64 ? PPC::ADD8 : PPC::ADD4; 671218885Sdim unsigned LISInstr = isPPC64 ? PPC::LIS8 : PPC::LIS; 672218885Sdim unsigned ORIInstr = isPPC64 ? PPC::ORI8 : PPC::ORI; 673218885Sdim 674218885Sdim if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) { 675218885Sdim BuildMI(MBB, MBBI, dl, TII.get(ADDIInstr), StackReg) 676218885Sdim .addReg(StackReg).addImm(CallerAllocatedAmt); 677218885Sdim } else { 678218885Sdim BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg) 679218885Sdim .addImm(CallerAllocatedAmt >> 16); 680218885Sdim BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg) 681218885Sdim .addReg(TmpReg, RegState::Kill) 682218885Sdim .addImm(CallerAllocatedAmt & 0xFFFF); 683218885Sdim BuildMI(MBB, MBBI, dl, TII.get(ADDInstr)) 684218885Sdim .addReg(StackReg) 685218885Sdim .addReg(FPReg) 686218885Sdim .addReg(TmpReg); 687218885Sdim } 688218885Sdim } else if (RetOpcode == PPC::TCRETURNdi) { 689218885Sdim MBBI = MBB.getLastNonDebugInstr(); 690218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 691218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)). 692218885Sdim addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 693218885Sdim } else if (RetOpcode == PPC::TCRETURNri) { 694218885Sdim MBBI = MBB.getLastNonDebugInstr(); 695218885Sdim assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 696218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR)); 697218885Sdim } else if (RetOpcode == PPC::TCRETURNai) { 698218885Sdim MBBI = MBB.getLastNonDebugInstr(); 699218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 700218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm()); 701218885Sdim } else if (RetOpcode == PPC::TCRETURNdi8) { 702218885Sdim MBBI = MBB.getLastNonDebugInstr(); 703218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 704218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)). 705218885Sdim addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); 706218885Sdim } else if (RetOpcode == PPC::TCRETURNri8) { 707218885Sdim MBBI = MBB.getLastNonDebugInstr(); 708218885Sdim assert(MBBI->getOperand(0).isReg() && "Expecting register operand."); 709218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8)); 710218885Sdim } else if (RetOpcode == PPC::TCRETURNai8) { 711218885Sdim MBBI = MBB.getLastNonDebugInstr(); 712218885Sdim MachineOperand &JumpTarget = MBBI->getOperand(0); 713218885Sdim BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm()); 714218885Sdim } 715218885Sdim} 716218885Sdim 717218885Sdimstatic bool spillsCR(const MachineFunction &MF) { 718218885Sdim const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>(); 719218885Sdim return FuncInfo->isCRSpilled(); 720218885Sdim} 721218885Sdim 722218885Sdim/// MustSaveLR - Return true if this function requires that we save the LR 723218885Sdim/// register onto the stack in the prolog and restore it in the epilog of the 724218885Sdim/// function. 725218885Sdimstatic bool MustSaveLR(const MachineFunction &MF, unsigned LR) { 726218885Sdim const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>(); 727218885Sdim 728218885Sdim // We need a save/restore of LR if there is any def of LR (which is 729218885Sdim // defined by calls, including the PIC setup sequence), or if there is 730218885Sdim // some use of the LR stack slot (e.g. for builtin_return_address). 731218885Sdim // (LR comes in 32 and 64 bit versions.) 732218885Sdim MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR); 733218885Sdim return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired(); 734218885Sdim} 735218885Sdim 736218885Sdimvoid 737218885SdimPPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 738218885Sdim RegScavenger *RS) const { 739218885Sdim const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo(); 740218885Sdim 741218885Sdim // Save and clear the LR state. 742218885Sdim PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>(); 743218885Sdim unsigned LR = RegInfo->getRARegister(); 744218885Sdim FI->setMustSaveLR(MustSaveLR(MF, LR)); 745218885Sdim MF.getRegInfo().setPhysRegUnused(LR); 746218885Sdim 747218885Sdim // Save R31 if necessary 748218885Sdim int FPSI = FI->getFramePointerSaveIndex(); 749218885Sdim bool isPPC64 = Subtarget.isPPC64(); 750218885Sdim bool isDarwinABI = Subtarget.isDarwinABI(); 751218885Sdim MachineFrameInfo *MFI = MF.getFrameInfo(); 752218885Sdim 753218885Sdim // If the frame pointer save index hasn't been defined yet. 754218885Sdim if (!FPSI && needsFP(MF)) { 755218885Sdim // Find out what the fix offset of the frame pointer save area. 756218885Sdim int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI); 757218885Sdim // Allocate the frame index for frame pointer save area. 758218885Sdim FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true); 759218885Sdim // Save the result. 760218885Sdim FI->setFramePointerSaveIndex(FPSI); 761218885Sdim } 762218885Sdim 763218885Sdim // Reserve stack space to move the linkage area to in case of a tail call. 764218885Sdim int TCSPDelta = 0; 765234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 766234353Sdim (TCSPDelta = FI->getTailCallSPDelta()) < 0) { 767218885Sdim MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true); 768218885Sdim } 769218885Sdim 770218885Sdim // Reserve a slot closest to SP or frame pointer if we have a dynalloc or 771218885Sdim // a large stack, which will require scavenging a register to materialize a 772218885Sdim // large offset. 773218885Sdim // FIXME: this doesn't actually check stack size, so is a bit pessimistic 774218885Sdim // FIXME: doesn't detect whether or not we need to spill vXX, which requires 775218885Sdim // r0 for now. 776218885Sdim 777234353Sdim if (RegInfo->requiresRegisterScavenging(MF)) 778218885Sdim if (needsFP(MF) || spillsCR(MF)) { 779218885Sdim const TargetRegisterClass *GPRC = &PPC::GPRCRegClass; 780218885Sdim const TargetRegisterClass *G8RC = &PPC::G8RCRegClass; 781218885Sdim const TargetRegisterClass *RC = isPPC64 ? G8RC : GPRC; 782218885Sdim RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(), 783218885Sdim RC->getAlignment(), 784218885Sdim false)); 785218885Sdim } 786218885Sdim} 787218885Sdim 788218885Sdimvoid PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF) 789218885Sdim const { 790218885Sdim // Early exit if not using the SVR4 ABI. 791218885Sdim if (!Subtarget.isSVR4ABI()) 792218885Sdim return; 793218885Sdim 794218885Sdim // Get callee saved register information. 795218885Sdim MachineFrameInfo *FFI = MF.getFrameInfo(); 796218885Sdim const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo(); 797218885Sdim 798218885Sdim // Early exit if no callee saved registers are modified! 799218885Sdim if (CSI.empty() && !needsFP(MF)) { 800218885Sdim return; 801218885Sdim } 802218885Sdim 803218885Sdim unsigned MinGPR = PPC::R31; 804218885Sdim unsigned MinG8R = PPC::X31; 805218885Sdim unsigned MinFPR = PPC::F31; 806218885Sdim unsigned MinVR = PPC::V31; 807218885Sdim 808218885Sdim bool HasGPSaveArea = false; 809218885Sdim bool HasG8SaveArea = false; 810218885Sdim bool HasFPSaveArea = false; 811218885Sdim bool HasCRSaveArea = false; 812218885Sdim bool HasVRSAVESaveArea = false; 813218885Sdim bool HasVRSaveArea = false; 814218885Sdim 815218885Sdim SmallVector<CalleeSavedInfo, 18> GPRegs; 816218885Sdim SmallVector<CalleeSavedInfo, 18> G8Regs; 817218885Sdim SmallVector<CalleeSavedInfo, 18> FPRegs; 818218885Sdim SmallVector<CalleeSavedInfo, 18> VRegs; 819218885Sdim 820218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 821218885Sdim unsigned Reg = CSI[i].getReg(); 822239462Sdim if (PPC::GPRCRegClass.contains(Reg)) { 823218885Sdim HasGPSaveArea = true; 824218885Sdim 825218885Sdim GPRegs.push_back(CSI[i]); 826218885Sdim 827218885Sdim if (Reg < MinGPR) { 828218885Sdim MinGPR = Reg; 829218885Sdim } 830239462Sdim } else if (PPC::G8RCRegClass.contains(Reg)) { 831218885Sdim HasG8SaveArea = true; 832218885Sdim 833218885Sdim G8Regs.push_back(CSI[i]); 834218885Sdim 835218885Sdim if (Reg < MinG8R) { 836218885Sdim MinG8R = Reg; 837218885Sdim } 838239462Sdim } else if (PPC::F8RCRegClass.contains(Reg)) { 839218885Sdim HasFPSaveArea = true; 840218885Sdim 841218885Sdim FPRegs.push_back(CSI[i]); 842218885Sdim 843218885Sdim if (Reg < MinFPR) { 844218885Sdim MinFPR = Reg; 845218885Sdim } 846218885Sdim// FIXME SVR4: Disable CR save area for now. 847239462Sdim } else if (PPC::CRBITRCRegClass.contains(Reg) || 848239462Sdim PPC::CRRCRegClass.contains(Reg)) { 849218885Sdim// HasCRSaveArea = true; 850239462Sdim } else if (PPC::VRSAVERCRegClass.contains(Reg)) { 851218885Sdim HasVRSAVESaveArea = true; 852239462Sdim } else if (PPC::VRRCRegClass.contains(Reg)) { 853218885Sdim HasVRSaveArea = true; 854218885Sdim 855218885Sdim VRegs.push_back(CSI[i]); 856218885Sdim 857218885Sdim if (Reg < MinVR) { 858218885Sdim MinVR = Reg; 859218885Sdim } 860218885Sdim } else { 861218885Sdim llvm_unreachable("Unknown RegisterClass!"); 862218885Sdim } 863218885Sdim } 864218885Sdim 865218885Sdim PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>(); 866218885Sdim 867218885Sdim int64_t LowerBound = 0; 868218885Sdim 869218885Sdim // Take into account stack space reserved for tail calls. 870218885Sdim int TCSPDelta = 0; 871234353Sdim if (MF.getTarget().Options.GuaranteedTailCallOpt && 872234353Sdim (TCSPDelta = PFI->getTailCallSPDelta()) < 0) { 873218885Sdim LowerBound = TCSPDelta; 874218885Sdim } 875218885Sdim 876218885Sdim // The Floating-point register save area is right below the back chain word 877218885Sdim // of the previous stack frame. 878218885Sdim if (HasFPSaveArea) { 879218885Sdim for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) { 880218885Sdim int FI = FPRegs[i].getFrameIdx(); 881218885Sdim 882218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 883218885Sdim } 884218885Sdim 885226633Sdim LowerBound -= (31 - getPPCRegisterNumbering(MinFPR) + 1) * 8; 886218885Sdim } 887218885Sdim 888218885Sdim // Check whether the frame pointer register is allocated. If so, make sure it 889218885Sdim // is spilled to the correct offset. 890218885Sdim if (needsFP(MF)) { 891218885Sdim HasGPSaveArea = true; 892218885Sdim 893218885Sdim int FI = PFI->getFramePointerSaveIndex(); 894218885Sdim assert(FI && "No Frame Pointer Save Slot!"); 895218885Sdim 896218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 897218885Sdim } 898218885Sdim 899218885Sdim // General register save area starts right below the Floating-point 900218885Sdim // register save area. 901218885Sdim if (HasGPSaveArea || HasG8SaveArea) { 902218885Sdim // Move general register save area spill slots down, taking into account 903218885Sdim // the size of the Floating-point register save area. 904218885Sdim for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) { 905218885Sdim int FI = GPRegs[i].getFrameIdx(); 906218885Sdim 907218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 908218885Sdim } 909218885Sdim 910218885Sdim // Move general register save area spill slots down, taking into account 911218885Sdim // the size of the Floating-point register save area. 912218885Sdim for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) { 913218885Sdim int FI = G8Regs[i].getFrameIdx(); 914218885Sdim 915218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 916218885Sdim } 917218885Sdim 918218885Sdim unsigned MinReg = 919226633Sdim std::min<unsigned>(getPPCRegisterNumbering(MinGPR), 920226633Sdim getPPCRegisterNumbering(MinG8R)); 921218885Sdim 922218885Sdim if (Subtarget.isPPC64()) { 923218885Sdim LowerBound -= (31 - MinReg + 1) * 8; 924218885Sdim } else { 925218885Sdim LowerBound -= (31 - MinReg + 1) * 4; 926218885Sdim } 927218885Sdim } 928218885Sdim 929218885Sdim // The CR save area is below the general register save area. 930218885Sdim if (HasCRSaveArea) { 931218885Sdim // FIXME SVR4: Is it actually possible to have multiple elements in CSI 932218885Sdim // which have the CR/CRBIT register class? 933218885Sdim // Adjust the frame index of the CR spill slot. 934218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 935218885Sdim unsigned Reg = CSI[i].getReg(); 936218885Sdim 937239462Sdim if (PPC::CRBITRCRegClass.contains(Reg) || 938239462Sdim PPC::CRRCRegClass.contains(Reg)) { 939218885Sdim int FI = CSI[i].getFrameIdx(); 940218885Sdim 941218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 942218885Sdim } 943218885Sdim } 944218885Sdim 945218885Sdim LowerBound -= 4; // The CR save area is always 4 bytes long. 946218885Sdim } 947218885Sdim 948218885Sdim if (HasVRSAVESaveArea) { 949218885Sdim // FIXME SVR4: Is it actually possible to have multiple elements in CSI 950218885Sdim // which have the VRSAVE register class? 951218885Sdim // Adjust the frame index of the VRSAVE spill slot. 952218885Sdim for (unsigned i = 0, e = CSI.size(); i != e; ++i) { 953218885Sdim unsigned Reg = CSI[i].getReg(); 954218885Sdim 955239462Sdim if (PPC::VRSAVERCRegClass.contains(Reg)) { 956218885Sdim int FI = CSI[i].getFrameIdx(); 957218885Sdim 958218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 959218885Sdim } 960218885Sdim } 961218885Sdim 962218885Sdim LowerBound -= 4; // The VRSAVE save area is always 4 bytes long. 963218885Sdim } 964218885Sdim 965218885Sdim if (HasVRSaveArea) { 966218885Sdim // Insert alignment padding, we need 16-byte alignment. 967218885Sdim LowerBound = (LowerBound - 15) & ~(15); 968218885Sdim 969218885Sdim for (unsigned i = 0, e = VRegs.size(); i != e; ++i) { 970218885Sdim int FI = VRegs[i].getFrameIdx(); 971218885Sdim 972218885Sdim FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI)); 973218885Sdim } 974218885Sdim } 975218885Sdim} 976