1239310Sdim//===- NVPTXInstrInfo.h - NVPTX Instruction Information----------*- C++ -*-===// 2239310Sdim// 3239310Sdim// The LLVM Compiler Infrastructure 4239310Sdim// 5239310Sdim// This file is distributed under the niversity of Illinois Open Source 6239310Sdim// License. See LICENSE.TXT for details. 7239310Sdim// 8239310Sdim//===----------------------------------------------------------------------===// 9239310Sdim// 10239310Sdim// This file contains the NVPTX implementation of the TargetInstrInfo class. 11239310Sdim// 12239310Sdim//===----------------------------------------------------------------------===// 13239310Sdim 14239310Sdim#ifndef NVPTXINSTRUCTIONINFO_H 15239310Sdim#define NVPTXINSTRUCTIONINFO_H 16239310Sdim 17239310Sdim#include "NVPTX.h" 18239310Sdim#include "NVPTXRegisterInfo.h" 19239310Sdim#include "llvm/Target/TargetInstrInfo.h" 20239310Sdim 21239310Sdim#define GET_INSTRINFO_HEADER 22239310Sdim#include "NVPTXGenInstrInfo.inc" 23239310Sdim 24239310Sdimnamespace llvm { 25239310Sdim 26249423Sdimclass NVPTXInstrInfo : public NVPTXGenInstrInfo { 27239310Sdim NVPTXTargetMachine &TM; 28239310Sdim const NVPTXRegisterInfo RegInfo; 29263508Sdim virtual void anchor(); 30239310Sdimpublic: 31239310Sdim explicit NVPTXInstrInfo(NVPTXTargetMachine &TM); 32239310Sdim 33239310Sdim virtual const NVPTXRegisterInfo &getRegisterInfo() const { return RegInfo; } 34239310Sdim 35239310Sdim /* The following virtual functions are used in register allocation. 36239310Sdim * They are not implemented because the existing interface and the logic 37239310Sdim * at the caller side do not work for the elementized vector load and store. 38239310Sdim * 39239310Sdim * virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, 40239310Sdim * int &FrameIndex) const; 41239310Sdim * virtual unsigned isStoreToStackSlot(const MachineInstr *MI, 42239310Sdim * int &FrameIndex) const; 43239310Sdim * virtual void storeRegToStackSlot(MachineBasicBlock &MBB, 44239310Sdim * MachineBasicBlock::iterator MBBI, 45239310Sdim * unsigned SrcReg, bool isKill, int FrameIndex, 46239310Sdim * const TargetRegisterClass *RC) const; 47239310Sdim * virtual void loadRegFromStackSlot(MachineBasicBlock &MBB, 48239310Sdim * MachineBasicBlock::iterator MBBI, 49239310Sdim * unsigned DestReg, int FrameIndex, 50239310Sdim * const TargetRegisterClass *RC) const; 51239310Sdim */ 52239310Sdim 53249423Sdim virtual void copyPhysReg( 54249423Sdim MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, 55249423Sdim unsigned DestReg, unsigned SrcReg, bool KillSrc) const; 56249423Sdim virtual bool isMoveInstr(const MachineInstr &MI, unsigned &SrcReg, 57239310Sdim unsigned &DestReg) const; 58239310Sdim bool isLoadInstr(const MachineInstr &MI, unsigned &AddrSpace) const; 59239310Sdim bool isStoreInstr(const MachineInstr &MI, unsigned &AddrSpace) const; 60239310Sdim bool isReadSpecialReg(MachineInstr &MI) const; 61239310Sdim 62249423Sdim virtual bool CanTailMerge(const MachineInstr *MI) const; 63239310Sdim // Branch analysis. 64249423Sdim virtual bool AnalyzeBranch( 65249423Sdim MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB, 66249423Sdim SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const; 67239310Sdim virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const; 68249423Sdim virtual unsigned InsertBranch( 69249423Sdim MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, 70249423Sdim const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const; 71239310Sdim unsigned getLdStCodeAddrSpace(const MachineInstr &MI) const { 72249423Sdim return MI.getOperand(2).getImm(); 73239310Sdim } 74239310Sdim 75239310Sdim}; 76239310Sdim 77239310Sdim} // namespace llvm 78239310Sdim 79239310Sdim#endif 80