MipsTargetMachine.h revision 226633 
1//===-- MipsTargetMachine.h - Define TargetMachine for Mips -00--*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the Mips specific subclass of TargetMachine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef MIPSTARGETMACHINE_H
15#define MIPSTARGETMACHINE_H
16
17#include "MipsSubtarget.h"
18#include "MipsInstrInfo.h"
19#include "MipsISelLowering.h"
20#include "MipsFrameLowering.h"
21#include "MipsSelectionDAGInfo.h"
22#include "llvm/Target/TargetMachine.h"
23#include "llvm/Target/TargetData.h"
24#include "llvm/Target/TargetFrameLowering.h"
25#include "MipsJITInfo.h"
26
27namespace llvm {
28  class formatted_raw_ostream;
29
30  class MipsTargetMachine : public LLVMTargetMachine {
31    MipsSubtarget       Subtarget;
32    const TargetData    DataLayout; // Calculates type size & alignment
33    MipsInstrInfo       InstrInfo;
34    MipsFrameLowering   FrameLowering;
35    MipsTargetLowering  TLInfo;
36    MipsSelectionDAGInfo TSInfo;
37    MipsJITInfo JITInfo;
38
39  public:
40    MipsTargetMachine(const Target &T, StringRef TT,
41                      StringRef CPU, StringRef FS,
42                      Reloc::Model RM, CodeModel::Model CM,
43                      bool isLittle);
44
45    virtual const MipsInstrInfo   *getInstrInfo()     const
46    { return &InstrInfo; }
47    virtual const TargetFrameLowering *getFrameLowering()     const
48    { return &FrameLowering; }
49    virtual const MipsSubtarget   *getSubtargetImpl() const
50    { return &Subtarget; }
51    virtual const TargetData      *getTargetData()    const
52    { return &DataLayout;}
53    virtual MipsJITInfo *getJITInfo()
54    { return &JITInfo; }
55
56
57    virtual const MipsRegisterInfo *getRegisterInfo()  const {
58      return &InstrInfo.getRegisterInfo();
59    }
60
61    virtual const MipsTargetLowering *getTargetLowering() const {
62      return &TLInfo;
63    }
64
65    virtual const MipsSelectionDAGInfo* getSelectionDAGInfo() const {
66      return &TSInfo;
67    }
68
69    // Pass Pipeline Configuration
70    virtual bool addInstSelector(PassManagerBase &PM,
71                                 CodeGenOpt::Level OptLevel);
72    virtual bool addPreEmitPass(PassManagerBase &PM,
73                                CodeGenOpt::Level OptLevel);
74    virtual bool addPreRegAlloc(PassManagerBase &PM,
75                                CodeGenOpt::Level OptLevel);
76    virtual bool addPostRegAlloc(PassManagerBase &, CodeGenOpt::Level);
77    virtual bool addCodeEmitter(PassManagerBase &PM,
78				 CodeGenOpt::Level OptLevel,
79				 JITCodeEmitter &JCE);
80
81  };
82
83/// MipsebTargetMachine - Mips32 big endian target machine.
84///
85class MipsebTargetMachine : public MipsTargetMachine {
86public:
87  MipsebTargetMachine(const Target &T, StringRef TT,
88                      StringRef CPU, StringRef FS,
89                      Reloc::Model RM, CodeModel::Model CM);
90};
91
92/// MipselTargetMachine - Mips32 little endian target machine.
93///
94class MipselTargetMachine : public MipsTargetMachine {
95public:
96  MipselTargetMachine(const Target &T, StringRef TT,
97                      StringRef CPU, StringRef FS,
98                      Reloc::Model RM, CodeModel::Model CM);
99};
100
101/// Mips64ebTargetMachine - Mips64 big endian target machine.
102///
103class Mips64ebTargetMachine : public MipsTargetMachine {
104public:
105  Mips64ebTargetMachine(const Target &T, StringRef TT,
106                        StringRef CPU, StringRef FS,
107                        Reloc::Model RM, CodeModel::Model CM);
108};
109
110/// Mips64elTargetMachine - Mips64 little endian target machine.
111///
112class Mips64elTargetMachine : public MipsTargetMachine {
113public:
114  Mips64elTargetMachine(const Target &T, StringRef TT,
115                        StringRef CPU, StringRef FS,
116                        Reloc::Model RM, CodeModel::Model CM);
117};
118} // End llvm namespace
119
120#endif
121