MipsRegisterInfo.td revision 223017
1//===- MipsRegisterInfo.td - Mips Register defs ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10//===----------------------------------------------------------------------===// 11// Declarations that describe the MIPS register file 12//===----------------------------------------------------------------------===// 13 14// We have banks of 32 registers each. 15class MipsReg<string n> : Register<n> { 16 field bits<5> Num; 17 let Namespace = "Mips"; 18} 19 20class MipsRegWithSubRegs<string n, list<Register> subregs> 21 : RegisterWithSubRegs<n, subregs> { 22 field bits<5> Num; 23 let Namespace = "Mips"; 24} 25 26// Mips CPU Registers 27class MipsGPRReg<bits<5> num, string n> : MipsReg<n> { 28 let Num = num; 29} 30 31// Mips 32-bit FPU Registers 32class FPR<bits<5> num, string n> : MipsReg<n> { 33 let Num = num; 34} 35 36// Mips 64-bit (aliased) FPU Registers 37let Namespace = "Mips" in { 38def sub_fpeven : SubRegIndex; 39def sub_fpodd : SubRegIndex; 40} 41class AFPR<bits<5> num, string n, list<Register> subregs> 42 : MipsRegWithSubRegs<n, subregs> { 43 let Num = num; 44 let SubRegIndices = [sub_fpeven, sub_fpodd]; 45} 46 47// Mips Hardware Registers 48class HWR<bits<5> num, string n> : MipsReg<n> { 49 let Num = num; 50} 51 52//===----------------------------------------------------------------------===// 53// Registers 54//===----------------------------------------------------------------------===// 55 56let Namespace = "Mips" in { 57 58 // General Purpose Registers 59 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>; 60 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>; 61 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 62 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 63 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 64 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 65 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 66 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 67 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 68 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 69 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 70 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 71 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 72 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 73 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 74 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 75 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 76 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 77 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 78 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 79 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 80 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 81 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 82 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 83 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 84 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 85 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 86 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 87 def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>; 88 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>; 89 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>; 90 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>; 91 92 /// Mips Single point precision FPU Registers 93 def F0 : FPR< 0, "F0">, DwarfRegNum<[32]>; 94 def F1 : FPR< 1, "F1">, DwarfRegNum<[33]>; 95 def F2 : FPR< 2, "F2">, DwarfRegNum<[34]>; 96 def F3 : FPR< 3, "F3">, DwarfRegNum<[35]>; 97 def F4 : FPR< 4, "F4">, DwarfRegNum<[36]>; 98 def F5 : FPR< 5, "F5">, DwarfRegNum<[37]>; 99 def F6 : FPR< 6, "F6">, DwarfRegNum<[38]>; 100 def F7 : FPR< 7, "F7">, DwarfRegNum<[39]>; 101 def F8 : FPR< 8, "F8">, DwarfRegNum<[40]>; 102 def F9 : FPR< 9, "F9">, DwarfRegNum<[41]>; 103 def F10 : FPR<10, "F10">, DwarfRegNum<[42]>; 104 def F11 : FPR<11, "F11">, DwarfRegNum<[43]>; 105 def F12 : FPR<12, "F12">, DwarfRegNum<[44]>; 106 def F13 : FPR<13, "F13">, DwarfRegNum<[45]>; 107 def F14 : FPR<14, "F14">, DwarfRegNum<[46]>; 108 def F15 : FPR<15, "F15">, DwarfRegNum<[47]>; 109 def F16 : FPR<16, "F16">, DwarfRegNum<[48]>; 110 def F17 : FPR<17, "F17">, DwarfRegNum<[49]>; 111 def F18 : FPR<18, "F18">, DwarfRegNum<[50]>; 112 def F19 : FPR<19, "F19">, DwarfRegNum<[51]>; 113 def F20 : FPR<20, "F20">, DwarfRegNum<[52]>; 114 def F21 : FPR<21, "F21">, DwarfRegNum<[53]>; 115 def F22 : FPR<22, "F22">, DwarfRegNum<[54]>; 116 def F23 : FPR<23, "F23">, DwarfRegNum<[55]>; 117 def F24 : FPR<24, "F24">, DwarfRegNum<[56]>; 118 def F25 : FPR<25, "F25">, DwarfRegNum<[57]>; 119 def F26 : FPR<26, "F26">, DwarfRegNum<[58]>; 120 def F27 : FPR<27, "F27">, DwarfRegNum<[59]>; 121 def F28 : FPR<28, "F28">, DwarfRegNum<[60]>; 122 def F29 : FPR<29, "F29">, DwarfRegNum<[61]>; 123 def F30 : FPR<30, "F30">, DwarfRegNum<[62]>; 124 def F31 : FPR<31, "F31">, DwarfRegNum<[63]>; 125 126 /// Mips Double point precision FPU Registers (aliased 127 /// with the single precision to hold 64 bit values) 128 def D0 : AFPR< 0, "F0", [F0, F1]>; 129 def D1 : AFPR< 2, "F2", [F2, F3]>; 130 def D2 : AFPR< 4, "F4", [F4, F5]>; 131 def D3 : AFPR< 6, "F6", [F6, F7]>; 132 def D4 : AFPR< 8, "F8", [F8, F9]>; 133 def D5 : AFPR<10, "F10", [F10, F11]>; 134 def D6 : AFPR<12, "F12", [F12, F13]>; 135 def D7 : AFPR<14, "F14", [F14, F15]>; 136 def D8 : AFPR<16, "F16", [F16, F17]>; 137 def D9 : AFPR<18, "F18", [F18, F19]>; 138 def D10 : AFPR<20, "F20", [F20, F21]>; 139 def D11 : AFPR<22, "F22", [F22, F23]>; 140 def D12 : AFPR<24, "F24", [F24, F25]>; 141 def D13 : AFPR<26, "F26", [F26, F27]>; 142 def D14 : AFPR<28, "F28", [F28, F29]>; 143 def D15 : AFPR<30, "F30", [F30, F31]>; 144 145 // Hi/Lo registers 146 def HI : Register<"hi">, DwarfRegNum<[64]>; 147 def LO : Register<"lo">, DwarfRegNum<[65]>; 148 149 // Status flags register 150 def FCR31 : Register<"31">; 151 152 // Hardware register $29 153 def HWR29 : Register<"29">; 154} 155 156//===----------------------------------------------------------------------===// 157// Register Classes 158//===----------------------------------------------------------------------===// 159 160def CPURegs : RegisterClass<"Mips", [i32], 32, 161 // Return Values and Arguments 162 [V0, V1, A0, A1, A2, A3, 163 // Not preserved across procedure calls 164 T0, T1, T2, T3, T4, T5, T6, T7, T8, T9, 165 // Callee save 166 S0, S1, S2, S3, S4, S5, S6, S7, 167 // Reserved 168 ZERO, AT, K0, K1, GP, SP, FP, RA]>; 169 170// 64bit fp: 171// * FGR64 - 32 64-bit registers 172// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 173// 174// 32bit fp: 175// * FGR32 - 16 32-bit even registers 176// * FGR32 - 32 32-bit registers (single float only mode) 177def FGR32 : RegisterClass<"Mips", [f32], 32, 178 // Return Values and Arguments 179 [F0, F1, F2, F3, F12, F13, F14, F15, 180 // Not preserved across procedure calls 181 F4, F5, F6, F7, F8, F9, F10, F11, F16, F17, F18, F19, 182 // Callee save 183 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30, 184 // Reserved 185 F31]>; 186 187def AFGR64 : RegisterClass<"Mips", [f64], 64, 188 // Return Values and Arguments 189 [D0, D1, D6, D7, 190 // Not preserved across procedure calls 191 D2, D3, D4, D5, D8, D9, 192 // Callee save 193 D10, D11, D12, D13, D14, 194 // Reserved 195 D15]> { 196 let SubRegClasses = [(FGR32 sub_fpeven, sub_fpodd)]; 197} 198 199// Condition Register for floating point operations 200def CCR : RegisterClass<"Mips", [i32], 32, [FCR31]>; 201 202// Hi/Lo Registers 203def HILO : RegisterClass<"Mips", [i32], 32, [HI, LO]>; 204 205// Hardware registers 206def HWRegs : RegisterClass<"Mips", [i32], 32, [HWR29]>; 207