MipsRegisterInfo.td revision 251662
1234353Sdim//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Declarations that describe the MIPS register file 12193323Sed//===----------------------------------------------------------------------===// 13226633Sdimlet Namespace = "Mips" in { 14226633Sdimdef sub_fpeven : SubRegIndex; 15226633Sdimdef sub_fpodd : SubRegIndex; 16226633Sdimdef sub_32 : SubRegIndex; 17243830Sdimdef sub_lo : SubRegIndex; 18243830Sdimdef sub_hi : SubRegIndex; 19251662Sdimdef sub_dsp16_19 : SubRegIndex; 20251662Sdimdef sub_dsp20 : SubRegIndex; 21251662Sdimdef sub_dsp21 : SubRegIndex; 22251662Sdimdef sub_dsp22 : SubRegIndex; 23251662Sdimdef sub_dsp23 : SubRegIndex; 24226633Sdim} 25193323Sed 26249423Sdimclass Unallocatable { 27249423Sdim bit isAllocatable = 0; 28249423Sdim} 29249423Sdim 30193323Sed// We have banks of 32 registers each. 31249423Sdimclass MipsReg<bits<16> Enc, string n> : Register<n> { 32249423Sdim let HWEncoding = Enc; 33193323Sed let Namespace = "Mips"; 34193323Sed} 35193323Sed 36249423Sdimclass MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 37199511Srdivacky : RegisterWithSubRegs<n, subregs> { 38249423Sdim let HWEncoding = Enc; 39199511Srdivacky let Namespace = "Mips"; 40199511Srdivacky} 41199511Srdivacky 42193323Sed// Mips CPU Registers 43249423Sdimclass MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 44193323Sed 45226633Sdim// Mips 64-bit CPU Registers 46249423Sdimclass Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 47249423Sdim : MipsRegWithSubRegs<Enc, n, subregs> { 48226633Sdim let SubRegIndices = [sub_32]; 49226633Sdim} 50226633Sdim 51193323Sed// Mips 32-bit FPU Registers 52249423Sdimclass FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 53193323Sed 54193323Sed// Mips 64-bit (aliased) FPU Registers 55249423Sdimclass AFPR<bits<16> Enc, string n, list<Register> subregs> 56249423Sdim : MipsRegWithSubRegs<Enc, n, subregs> { 57208599Srdivacky let SubRegIndices = [sub_fpeven, sub_fpodd]; 58234353Sdim let CoveredBySubRegs = 1; 59193323Sed} 60193323Sed 61249423Sdimclass AFPR64<bits<16> Enc, string n, list<Register> subregs> 62249423Sdim : MipsRegWithSubRegs<Enc, n, subregs> { 63226633Sdim let SubRegIndices = [sub_32]; 64226633Sdim} 65226633Sdim 66249423Sdim// Accumulator Registers 67249423Sdimclass ACC<bits<16> Enc, string n, list<Register> subregs> 68249423Sdim : MipsRegWithSubRegs<Enc, n, subregs> { 69249423Sdim let SubRegIndices = [sub_lo, sub_hi]; 70249423Sdim let CoveredBySubRegs = 1; 71223017Sdim} 72223017Sdim 73249423Sdim// Mips Hardware Registers 74249423Sdimclass HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 75249423Sdim 76193323Sed//===----------------------------------------------------------------------===// 77193323Sed// Registers 78193323Sed//===----------------------------------------------------------------------===// 79193323Sed 80193323Sedlet Namespace = "Mips" in { 81193323Sed // General Purpose Registers 82239462Sdim def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 83243830Sdim def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 84193323Sed def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 85193323Sed def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 86223017Sdim def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 87193323Sed def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 88193323Sed def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 89193323Sed def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 90193323Sed def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 91193323Sed def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 92193323Sed def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 93193323Sed def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 94193323Sed def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 95193323Sed def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 96193323Sed def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 97193323Sed def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 98193323Sed def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 99193323Sed def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 100193323Sed def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 101193323Sed def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 102193323Sed def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 103193323Sed def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 104193323Sed def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 105193323Sed def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 106193323Sed def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 107193323Sed def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 108193323Sed def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 109193323Sed def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 110239462Sdim def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 111239462Sdim def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 112239462Sdim def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 113239462Sdim def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 114221345Sdim 115226633Sdim // General Purpose 64-bit Registers 116239462Sdim def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 117243830Sdim def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 118234353Sdim def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 119234353Sdim def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 120234353Sdim def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 121234353Sdim def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 122234353Sdim def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 123234353Sdim def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 124234353Sdim def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 125234353Sdim def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 126234353Sdim def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 127234353Sdim def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 128234353Sdim def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 129234353Sdim def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 130234353Sdim def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 131234353Sdim def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 132234353Sdim def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 133234353Sdim def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 134234353Sdim def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 135234353Sdim def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 136234353Sdim def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 137234353Sdim def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 138234353Sdim def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 139234353Sdim def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 140234353Sdim def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 141234353Sdim def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 142234353Sdim def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 143234353Sdim def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 144239462Sdim def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 145239462Sdim def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 146239462Sdim def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 147239462Sdim def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 148226633Sdim 149193323Sed /// Mips Single point precision FPU Registers 150239462Sdim def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>; 151239462Sdim def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>; 152239462Sdim def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>; 153239462Sdim def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>; 154239462Sdim def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>; 155239462Sdim def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>; 156239462Sdim def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>; 157239462Sdim def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>; 158239462Sdim def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>; 159239462Sdim def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>; 160239462Sdim def F10 : FPR<10, "f10">, DwarfRegNum<[42]>; 161239462Sdim def F11 : FPR<11, "f11">, DwarfRegNum<[43]>; 162239462Sdim def F12 : FPR<12, "f12">, DwarfRegNum<[44]>; 163239462Sdim def F13 : FPR<13, "f13">, DwarfRegNum<[45]>; 164239462Sdim def F14 : FPR<14, "f14">, DwarfRegNum<[46]>; 165239462Sdim def F15 : FPR<15, "f15">, DwarfRegNum<[47]>; 166239462Sdim def F16 : FPR<16, "f16">, DwarfRegNum<[48]>; 167239462Sdim def F17 : FPR<17, "f17">, DwarfRegNum<[49]>; 168239462Sdim def F18 : FPR<18, "f18">, DwarfRegNum<[50]>; 169239462Sdim def F19 : FPR<19, "f19">, DwarfRegNum<[51]>; 170239462Sdim def F20 : FPR<20, "f20">, DwarfRegNum<[52]>; 171239462Sdim def F21 : FPR<21, "f21">, DwarfRegNum<[53]>; 172239462Sdim def F22 : FPR<22, "f22">, DwarfRegNum<[54]>; 173239462Sdim def F23 : FPR<23, "f23">, DwarfRegNum<[55]>; 174239462Sdim def F24 : FPR<24, "f24">, DwarfRegNum<[56]>; 175239462Sdim def F25 : FPR<25, "f25">, DwarfRegNum<[57]>; 176239462Sdim def F26 : FPR<26, "f26">, DwarfRegNum<[58]>; 177239462Sdim def F27 : FPR<27, "f27">, DwarfRegNum<[59]>; 178239462Sdim def F28 : FPR<28, "f28">, DwarfRegNum<[60]>; 179239462Sdim def F29 : FPR<29, "f29">, DwarfRegNum<[61]>; 180239462Sdim def F30 : FPR<30, "f30">, DwarfRegNum<[62]>; 181239462Sdim def F31 : FPR<31, "f31">, DwarfRegNum<[63]>; 182221345Sdim 183193323Sed /// Mips Double point precision FPU Registers (aliased 184193323Sed /// with the single precision to hold 64 bit values) 185239462Sdim def D0 : AFPR< 0, "f0", [F0, F1]>; 186239462Sdim def D1 : AFPR< 2, "f2", [F2, F3]>; 187239462Sdim def D2 : AFPR< 4, "f4", [F4, F5]>; 188239462Sdim def D3 : AFPR< 6, "f6", [F6, F7]>; 189239462Sdim def D4 : AFPR< 8, "f8", [F8, F9]>; 190239462Sdim def D5 : AFPR<10, "f10", [F10, F11]>; 191239462Sdim def D6 : AFPR<12, "f12", [F12, F13]>; 192239462Sdim def D7 : AFPR<14, "f14", [F14, F15]>; 193239462Sdim def D8 : AFPR<16, "f16", [F16, F17]>; 194239462Sdim def D9 : AFPR<18, "f18", [F18, F19]>; 195239462Sdim def D10 : AFPR<20, "f20", [F20, F21]>; 196239462Sdim def D11 : AFPR<22, "f22", [F22, F23]>; 197239462Sdim def D12 : AFPR<24, "f24", [F24, F25]>; 198239462Sdim def D13 : AFPR<26, "f26", [F26, F27]>; 199239462Sdim def D14 : AFPR<28, "f28", [F28, F29]>; 200239462Sdim def D15 : AFPR<30, "f30", [F30, F31]>; 201193323Sed 202226633Sdim /// Mips Double point precision FPU Registers in MFP64 mode. 203239462Sdim def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>; 204239462Sdim def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>; 205239462Sdim def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>; 206239462Sdim def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>; 207239462Sdim def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>; 208239462Sdim def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>; 209239462Sdim def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>; 210239462Sdim def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>; 211239462Sdim def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>; 212239462Sdim def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>; 213239462Sdim def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>; 214239462Sdim def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>; 215239462Sdim def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>; 216239462Sdim def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>; 217239462Sdim def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>; 218239462Sdim def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>; 219239462Sdim def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>; 220239462Sdim def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>; 221239462Sdim def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>; 222239462Sdim def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>; 223239462Sdim def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>; 224239462Sdim def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>; 225239462Sdim def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>; 226239462Sdim def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>; 227239462Sdim def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>; 228239462Sdim def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>; 229239462Sdim def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>; 230239462Sdim def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>; 231239462Sdim def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>; 232239462Sdim def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>; 233239462Sdim def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>; 234239462Sdim def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>; 235226633Sdim 236193323Sed // Hi/Lo registers 237251662Sdim def HI : Register<"ac0">, DwarfRegNum<[64]>; 238251662Sdim def HI1 : Register<"ac1">, DwarfRegNum<[176]>; 239251662Sdim def HI2 : Register<"ac2">, DwarfRegNum<[178]>; 240251662Sdim def HI3 : Register<"ac3">, DwarfRegNum<[180]>; 241251662Sdim def LO : Register<"ac0">, DwarfRegNum<[65]>; 242251662Sdim def LO1 : Register<"ac1">, DwarfRegNum<[177]>; 243251662Sdim def LO2 : Register<"ac2">, DwarfRegNum<[179]>; 244251662Sdim def LO3 : Register<"ac3">, DwarfRegNum<[181]>; 245193323Sed 246226633Sdim let SubRegIndices = [sub_32] in { 247226633Sdim def HI64 : RegisterWithSubRegs<"hi", [HI]>; 248226633Sdim def LO64 : RegisterWithSubRegs<"lo", [LO]>; 249226633Sdim } 250226633Sdim 251193323Sed // Status flags register 252193323Sed def FCR31 : Register<"31">; 253223017Sdim 254239462Sdim // fcc0 register 255249423Sdim def FCC0 : MipsReg<0, "fcc0">; 256239462Sdim 257243830Sdim // PC register 258243830Sdim def PC : Register<"pc">; 259243830Sdim 260223017Sdim // Hardware register $29 261249423Sdim def HWR29 : MipsReg<29, "29">; 262249423Sdim def HWR29_64 : MipsReg<29, "29">; 263243830Sdim 264243830Sdim // Accum registers 265249423Sdim def AC0 : ACC<0, "ac0", [LO, HI]>; 266249423Sdim def AC1 : ACC<1, "ac1", [LO1, HI1]>; 267249423Sdim def AC2 : ACC<2, "ac2", [LO2, HI2]>; 268249423Sdim def AC3 : ACC<3, "ac3", [LO3, HI3]>; 269243830Sdim 270249423Sdim def AC0_64 : ACC<0, "ac0", [LO64, HI64]>; 271249423Sdim 272251662Sdim // DSP-ASE control register fields. 273251662Sdim def DSPPos : Register<"">; 274251662Sdim def DSPSCount : Register<"">; 275251662Sdim def DSPCarry : Register<"">; 276251662Sdim def DSPEFI : Register<"">; 277251662Sdim def DSPOutFlag16_19 : Register<"">; 278251662Sdim def DSPOutFlag20 : Register<"">; 279251662Sdim def DSPOutFlag21 : Register<"">; 280251662Sdim def DSPOutFlag22 : Register<"">; 281251662Sdim def DSPOutFlag23 : Register<"">; 282251662Sdim def DSPCCond : Register<"">; 283251662Sdim 284251662Sdim let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 285251662Sdim sub_dsp23] in 286251662Sdim def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 287251662Sdim DSPOutFlag21, DSPOutFlag22, 288251662Sdim DSPOutFlag23]>; 289193323Sed} 290193323Sed 291193323Sed//===----------------------------------------------------------------------===// 292193323Sed// Register Classes 293193323Sed//===----------------------------------------------------------------------===// 294193323Sed 295243830Sdimclass CPURegsClass<list<ValueType> regTypes> : 296243830Sdim RegisterClass<"Mips", regTypes, 32, (add 297239462Sdim // Reserved 298239462Sdim ZERO, AT, 299193323Sed // Return Values and Arguments 300224145Sdim V0, V1, A0, A1, A2, A3, 301193323Sed // Not preserved across procedure calls 302239462Sdim T0, T1, T2, T3, T4, T5, T6, T7, 303193323Sed // Callee save 304193323Sed S0, S1, S2, S3, S4, S5, S6, S7, 305239462Sdim // Not preserved across procedure calls 306239462Sdim T8, T9, 307193323Sed // Reserved 308239462Sdim K0, K1, GP, SP, FP, RA)>; 309193323Sed 310243830Sdimdef CPURegs : CPURegsClass<[i32]>; 311243830Sdimdef DSPRegs : CPURegsClass<[v4i8, v2i16]>; 312243830Sdim 313226633Sdimdef CPU64Regs : RegisterClass<"Mips", [i64], 64, (add 314239462Sdim// Reserved 315239462Sdim ZERO_64, AT_64, 316226633Sdim // Return Values and Arguments 317226633Sdim V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 318226633Sdim // Not preserved across procedure calls 319239462Sdim T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 320226633Sdim // Callee save 321226633Sdim S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 322239462Sdim // Not preserved across procedure calls 323239462Sdim T8_64, T9_64, 324226633Sdim // Reserved 325239462Sdim K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 326226633Sdim 327239462Sdimdef CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 328239462Sdim // Return Values and Arguments 329239462Sdim V0, V1, A0, A1, A2, A3, 330239462Sdim // Callee save 331239462Sdim S0, S1)>; 332239462Sdim 333249423Sdimdef CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 334239462Sdim 335249423Sdimdef CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 336239462Sdim 337193323Sed// 64bit fp: 338193323Sed// * FGR64 - 32 64-bit registers 339221345Sdim// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 340193323Sed// 341193323Sed// 32bit fp: 342193323Sed// * FGR32 - 16 32-bit even registers 343193323Sed// * FGR32 - 32 32-bit registers (single float only mode) 344224145Sdimdef FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 345193323Sed 346224145Sdimdef AFGR64 : RegisterClass<"Mips", [f64], 64, (add 347193323Sed // Return Values and Arguments 348239462Sdim D0, D1, 349193323Sed // Not preserved across procedure calls 350239462Sdim D2, D3, D4, D5, 351239462Sdim // Return Values and Arguments 352239462Sdim D6, D7, 353239462Sdim // Not preserved across procedure calls 354239462Sdim D8, D9, 355193323Sed // Callee save 356239462Sdim D10, D11, D12, D13, D14, D15)>; 357193323Sed 358239462Sdimdef FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 359226633Sdim 360193323Sed// Condition Register for floating point operations 361249423Sdimdef CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>, Unallocatable; 362193323Sed 363193323Sed// Hi/Lo Registers 364251662Sdimdef LORegs : RegisterClass<"Mips", [i32], 32, (add LO)>; 365251662Sdimdef HIRegs : RegisterClass<"Mips", [i32], 32, (add HI)>; 366251662Sdimdef LORegsDSP : RegisterClass<"Mips", [i32], 32, (add LO, LO1, LO2, LO3)>; 367251662Sdimdef HIRegsDSP : RegisterClass<"Mips", [i32], 32, (add HI, HI1, HI2, HI3)>; 368251662Sdimdef LORegs64 : RegisterClass<"Mips", [i64], 64, (add LO64)>; 369251662Sdimdef HIRegs64 : RegisterClass<"Mips", [i64], 64, (add HI64)>; 370193323Sed 371223017Sdim// Hardware registers 372249423Sdimdef HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; 373249423Sdimdef HWRegs64 : RegisterClass<"Mips", [i64], 64, (add HWR29_64)>, Unallocatable; 374234353Sdim 375243830Sdim// Accumulator Registers 376249423Sdimdef ACRegs : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 377249423Sdim let Size = 64; 378249423Sdim} 379249423Sdim 380249423Sdimdef ACRegs128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 381249423Sdim let Size = 128; 382249423Sdim} 383249423Sdim 384249423Sdimdef ACRegsDSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 385249423Sdim let Size = 64; 386249423Sdim} 387249423Sdim 388251662Sdimdef DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 389251662Sdim 390251662Sdim// Register Operands. 391249423Sdimdef CPURegsAsmOperand : AsmOperandClass { 392249423Sdim let Name = "CPURegsAsm"; 393249423Sdim let ParserMethod = "parseCPURegs"; 394249423Sdim} 395249423Sdim 396249423Sdimdef CPU64RegsAsmOperand : AsmOperandClass { 397249423Sdim let Name = "CPU64RegsAsm"; 398249423Sdim let ParserMethod = "parseCPU64Regs"; 399249423Sdim} 400249423Sdim 401249423Sdimdef CCRAsmOperand : AsmOperandClass { 402249423Sdim let Name = "CCRAsm"; 403249423Sdim let ParserMethod = "parseCCRRegs"; 404249423Sdim} 405249423Sdim 406249423Sdimdef CPURegsOpnd : RegisterOperand<CPURegs, "printCPURegs"> { 407249423Sdim let ParserMatchClass = CPURegsAsmOperand; 408249423Sdim} 409249423Sdim 410249423Sdimdef CPU64RegsOpnd : RegisterOperand<CPU64Regs, "printCPURegs"> { 411249423Sdim let ParserMatchClass = CPU64RegsAsmOperand; 412249423Sdim} 413249423Sdim 414249423Sdimdef CCROpnd : RegisterOperand<CCR, "printCPURegs"> { 415249423Sdim let ParserMatchClass = CCRAsmOperand; 416249423Sdim} 417249423Sdim 418249423Sdimdef HWRegsAsmOperand : AsmOperandClass { 419249423Sdim let Name = "HWRegsAsm"; 420249423Sdim let ParserMethod = "parseHWRegs"; 421249423Sdim} 422249423Sdim 423249423Sdimdef HW64RegsAsmOperand : AsmOperandClass { 424249423Sdim let Name = "HW64RegsAsm"; 425249423Sdim let ParserMethod = "parseHW64Regs"; 426249423Sdim} 427249423Sdim 428249423Sdimdef HWRegsOpnd : RegisterOperand<HWRegs, "printCPURegs"> { 429249423Sdim let ParserMatchClass = HWRegsAsmOperand; 430249423Sdim} 431249423Sdim 432249423Sdimdef HW64RegsOpnd : RegisterOperand<HWRegs64, "printCPURegs"> { 433249423Sdim let ParserMatchClass = HW64RegsAsmOperand; 434249423Sdim} 435