MipsRegisterInfo.td revision 243830
1234353Sdim//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Declarations that describe the MIPS register file 12193323Sed//===----------------------------------------------------------------------===// 13226633Sdimlet Namespace = "Mips" in { 14226633Sdimdef sub_fpeven : SubRegIndex; 15226633Sdimdef sub_fpodd : SubRegIndex; 16226633Sdimdef sub_32 : SubRegIndex; 17243830Sdimdef sub_lo : SubRegIndex; 18243830Sdimdef sub_hi : SubRegIndex; 19226633Sdim} 20193323Sed 21193323Sed// We have banks of 32 registers each. 22193323Sedclass MipsReg<string n> : Register<n> { 23193323Sed field bits<5> Num; 24193323Sed let Namespace = "Mips"; 25193323Sed} 26193323Sed 27221345Sdimclass MipsRegWithSubRegs<string n, list<Register> subregs> 28199511Srdivacky : RegisterWithSubRegs<n, subregs> { 29199511Srdivacky field bits<5> Num; 30199511Srdivacky let Namespace = "Mips"; 31199511Srdivacky} 32199511Srdivacky 33193323Sed// Mips CPU Registers 34193323Sedclass MipsGPRReg<bits<5> num, string n> : MipsReg<n> { 35193323Sed let Num = num; 36193323Sed} 37193323Sed 38226633Sdim// Mips 64-bit CPU Registers 39226633Sdimclass Mips64GPRReg<bits<5> num, string n, list<Register> subregs> 40226633Sdim : MipsRegWithSubRegs<n, subregs> { 41226633Sdim let Num = num; 42226633Sdim let SubRegIndices = [sub_32]; 43226633Sdim} 44226633Sdim 45193323Sed// Mips 32-bit FPU Registers 46193323Sedclass FPR<bits<5> num, string n> : MipsReg<n> { 47193323Sed let Num = num; 48193323Sed} 49193323Sed 50193323Sed// Mips 64-bit (aliased) FPU Registers 51208599Srdivackyclass AFPR<bits<5> num, string n, list<Register> subregs> 52199511Srdivacky : MipsRegWithSubRegs<n, subregs> { 53193323Sed let Num = num; 54208599Srdivacky let SubRegIndices = [sub_fpeven, sub_fpodd]; 55234353Sdim let CoveredBySubRegs = 1; 56193323Sed} 57193323Sed 58226633Sdimclass AFPR64<bits<5> num, string n, list<Register> subregs> 59226633Sdim : MipsRegWithSubRegs<n, subregs> { 60226633Sdim let Num = num; 61226633Sdim let SubRegIndices = [sub_32]; 62226633Sdim} 63226633Sdim 64223017Sdim// Mips Hardware Registers 65223017Sdimclass HWR<bits<5> num, string n> : MipsReg<n> { 66223017Sdim let Num = num; 67223017Sdim} 68223017Sdim 69193323Sed//===----------------------------------------------------------------------===// 70193323Sed// Registers 71193323Sed//===----------------------------------------------------------------------===// 72193323Sed 73193323Sedlet Namespace = "Mips" in { 74193323Sed // General Purpose Registers 75239462Sdim def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 76243830Sdim def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 77193323Sed def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 78193323Sed def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 79223017Sdim def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 80193323Sed def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 81193323Sed def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 82193323Sed def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 83193323Sed def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 84193323Sed def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 85193323Sed def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 86193323Sed def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 87193323Sed def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 88193323Sed def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 89193323Sed def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 90193323Sed def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 91193323Sed def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 92193323Sed def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 93193323Sed def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 94193323Sed def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 95193323Sed def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 96193323Sed def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 97193323Sed def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 98193323Sed def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 99193323Sed def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 100193323Sed def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 101193323Sed def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 102193323Sed def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 103239462Sdim def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 104239462Sdim def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 105239462Sdim def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 106239462Sdim def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 107221345Sdim 108226633Sdim // General Purpose 64-bit Registers 109239462Sdim def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 110243830Sdim def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 111234353Sdim def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 112234353Sdim def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 113234353Sdim def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 114234353Sdim def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 115234353Sdim def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 116234353Sdim def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 117234353Sdim def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 118234353Sdim def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 119234353Sdim def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 120234353Sdim def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 121234353Sdim def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 122234353Sdim def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 123234353Sdim def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 124234353Sdim def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 125234353Sdim def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 126234353Sdim def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 127234353Sdim def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 128234353Sdim def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 129234353Sdim def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 130234353Sdim def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 131234353Sdim def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 132234353Sdim def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 133234353Sdim def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 134234353Sdim def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 135234353Sdim def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 136234353Sdim def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 137239462Sdim def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 138239462Sdim def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 139239462Sdim def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 140239462Sdim def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 141226633Sdim 142193323Sed /// Mips Single point precision FPU Registers 143239462Sdim def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>; 144239462Sdim def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>; 145239462Sdim def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>; 146239462Sdim def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>; 147239462Sdim def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>; 148239462Sdim def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>; 149239462Sdim def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>; 150239462Sdim def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>; 151239462Sdim def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>; 152239462Sdim def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>; 153239462Sdim def F10 : FPR<10, "f10">, DwarfRegNum<[42]>; 154239462Sdim def F11 : FPR<11, "f11">, DwarfRegNum<[43]>; 155239462Sdim def F12 : FPR<12, "f12">, DwarfRegNum<[44]>; 156239462Sdim def F13 : FPR<13, "f13">, DwarfRegNum<[45]>; 157239462Sdim def F14 : FPR<14, "f14">, DwarfRegNum<[46]>; 158239462Sdim def F15 : FPR<15, "f15">, DwarfRegNum<[47]>; 159239462Sdim def F16 : FPR<16, "f16">, DwarfRegNum<[48]>; 160239462Sdim def F17 : FPR<17, "f17">, DwarfRegNum<[49]>; 161239462Sdim def F18 : FPR<18, "f18">, DwarfRegNum<[50]>; 162239462Sdim def F19 : FPR<19, "f19">, DwarfRegNum<[51]>; 163239462Sdim def F20 : FPR<20, "f20">, DwarfRegNum<[52]>; 164239462Sdim def F21 : FPR<21, "f21">, DwarfRegNum<[53]>; 165239462Sdim def F22 : FPR<22, "f22">, DwarfRegNum<[54]>; 166239462Sdim def F23 : FPR<23, "f23">, DwarfRegNum<[55]>; 167239462Sdim def F24 : FPR<24, "f24">, DwarfRegNum<[56]>; 168239462Sdim def F25 : FPR<25, "f25">, DwarfRegNum<[57]>; 169239462Sdim def F26 : FPR<26, "f26">, DwarfRegNum<[58]>; 170239462Sdim def F27 : FPR<27, "f27">, DwarfRegNum<[59]>; 171239462Sdim def F28 : FPR<28, "f28">, DwarfRegNum<[60]>; 172239462Sdim def F29 : FPR<29, "f29">, DwarfRegNum<[61]>; 173239462Sdim def F30 : FPR<30, "f30">, DwarfRegNum<[62]>; 174239462Sdim def F31 : FPR<31, "f31">, DwarfRegNum<[63]>; 175221345Sdim 176193323Sed /// Mips Double point precision FPU Registers (aliased 177193323Sed /// with the single precision to hold 64 bit values) 178239462Sdim def D0 : AFPR< 0, "f0", [F0, F1]>; 179239462Sdim def D1 : AFPR< 2, "f2", [F2, F3]>; 180239462Sdim def D2 : AFPR< 4, "f4", [F4, F5]>; 181239462Sdim def D3 : AFPR< 6, "f6", [F6, F7]>; 182239462Sdim def D4 : AFPR< 8, "f8", [F8, F9]>; 183239462Sdim def D5 : AFPR<10, "f10", [F10, F11]>; 184239462Sdim def D6 : AFPR<12, "f12", [F12, F13]>; 185239462Sdim def D7 : AFPR<14, "f14", [F14, F15]>; 186239462Sdim def D8 : AFPR<16, "f16", [F16, F17]>; 187239462Sdim def D9 : AFPR<18, "f18", [F18, F19]>; 188239462Sdim def D10 : AFPR<20, "f20", [F20, F21]>; 189239462Sdim def D11 : AFPR<22, "f22", [F22, F23]>; 190239462Sdim def D12 : AFPR<24, "f24", [F24, F25]>; 191239462Sdim def D13 : AFPR<26, "f26", [F26, F27]>; 192239462Sdim def D14 : AFPR<28, "f28", [F28, F29]>; 193239462Sdim def D15 : AFPR<30, "f30", [F30, F31]>; 194193323Sed 195226633Sdim /// Mips Double point precision FPU Registers in MFP64 mode. 196239462Sdim def D0_64 : AFPR64<0, "f0", [F0]>, DwarfRegNum<[32]>; 197239462Sdim def D1_64 : AFPR64<1, "f1", [F1]>, DwarfRegNum<[33]>; 198239462Sdim def D2_64 : AFPR64<2, "f2", [F2]>, DwarfRegNum<[34]>; 199239462Sdim def D3_64 : AFPR64<3, "f3", [F3]>, DwarfRegNum<[35]>; 200239462Sdim def D4_64 : AFPR64<4, "f4", [F4]>, DwarfRegNum<[36]>; 201239462Sdim def D5_64 : AFPR64<5, "f5", [F5]>, DwarfRegNum<[37]>; 202239462Sdim def D6_64 : AFPR64<6, "f6", [F6]>, DwarfRegNum<[38]>; 203239462Sdim def D7_64 : AFPR64<7, "f7", [F7]>, DwarfRegNum<[39]>; 204239462Sdim def D8_64 : AFPR64<8, "f8", [F8]>, DwarfRegNum<[40]>; 205239462Sdim def D9_64 : AFPR64<9, "f9", [F9]>, DwarfRegNum<[41]>; 206239462Sdim def D10_64 : AFPR64<10, "f10", [F10]>, DwarfRegNum<[42]>; 207239462Sdim def D11_64 : AFPR64<11, "f11", [F11]>, DwarfRegNum<[43]>; 208239462Sdim def D12_64 : AFPR64<12, "f12", [F12]>, DwarfRegNum<[44]>; 209239462Sdim def D13_64 : AFPR64<13, "f13", [F13]>, DwarfRegNum<[45]>; 210239462Sdim def D14_64 : AFPR64<14, "f14", [F14]>, DwarfRegNum<[46]>; 211239462Sdim def D15_64 : AFPR64<15, "f15", [F15]>, DwarfRegNum<[47]>; 212239462Sdim def D16_64 : AFPR64<16, "f16", [F16]>, DwarfRegNum<[48]>; 213239462Sdim def D17_64 : AFPR64<17, "f17", [F17]>, DwarfRegNum<[49]>; 214239462Sdim def D18_64 : AFPR64<18, "f18", [F18]>, DwarfRegNum<[50]>; 215239462Sdim def D19_64 : AFPR64<19, "f19", [F19]>, DwarfRegNum<[51]>; 216239462Sdim def D20_64 : AFPR64<20, "f20", [F20]>, DwarfRegNum<[52]>; 217239462Sdim def D21_64 : AFPR64<21, "f21", [F21]>, DwarfRegNum<[53]>; 218239462Sdim def D22_64 : AFPR64<22, "f22", [F22]>, DwarfRegNum<[54]>; 219239462Sdim def D23_64 : AFPR64<23, "f23", [F23]>, DwarfRegNum<[55]>; 220239462Sdim def D24_64 : AFPR64<24, "f24", [F24]>, DwarfRegNum<[56]>; 221239462Sdim def D25_64 : AFPR64<25, "f25", [F25]>, DwarfRegNum<[57]>; 222239462Sdim def D26_64 : AFPR64<26, "f26", [F26]>, DwarfRegNum<[58]>; 223239462Sdim def D27_64 : AFPR64<27, "f27", [F27]>, DwarfRegNum<[59]>; 224239462Sdim def D28_64 : AFPR64<28, "f28", [F28]>, DwarfRegNum<[60]>; 225239462Sdim def D29_64 : AFPR64<29, "f29", [F29]>, DwarfRegNum<[61]>; 226239462Sdim def D30_64 : AFPR64<30, "f30", [F30]>, DwarfRegNum<[62]>; 227239462Sdim def D31_64 : AFPR64<31, "f31", [F31]>, DwarfRegNum<[63]>; 228226633Sdim 229193323Sed // Hi/Lo registers 230193323Sed def HI : Register<"hi">, DwarfRegNum<[64]>; 231193323Sed def LO : Register<"lo">, DwarfRegNum<[65]>; 232193323Sed 233226633Sdim let SubRegIndices = [sub_32] in { 234226633Sdim def HI64 : RegisterWithSubRegs<"hi", [HI]>; 235226633Sdim def LO64 : RegisterWithSubRegs<"lo", [LO]>; 236226633Sdim } 237226633Sdim 238193323Sed // Status flags register 239193323Sed def FCR31 : Register<"31">; 240223017Sdim 241239462Sdim // fcc0 register 242239462Sdim def FCC0 : Register<"fcc0">; 243239462Sdim 244243830Sdim // PC register 245243830Sdim def PC : Register<"pc">; 246243830Sdim 247223017Sdim // Hardware register $29 248223017Sdim def HWR29 : Register<"29">; 249234353Sdim def HWR29_64 : Register<"29">; 250243830Sdim 251243830Sdim // Accum registers 252243830Sdim let SubRegIndices = [sub_lo, sub_hi] in 253243830Sdim def AC0 : RegisterWithSubRegs<"ac0", [LO, HI]>; 254243830Sdim def AC1 : Register<"ac1">; 255243830Sdim def AC2 : Register<"ac2">; 256243830Sdim def AC3 : Register<"ac3">; 257243830Sdim 258243830Sdim def DSPCtrl : Register<"dspctrl">; 259193323Sed} 260193323Sed 261193323Sed//===----------------------------------------------------------------------===// 262193323Sed// Register Classes 263193323Sed//===----------------------------------------------------------------------===// 264193323Sed 265243830Sdimclass CPURegsClass<list<ValueType> regTypes> : 266243830Sdim RegisterClass<"Mips", regTypes, 32, (add 267239462Sdim // Reserved 268239462Sdim ZERO, AT, 269193323Sed // Return Values and Arguments 270224145Sdim V0, V1, A0, A1, A2, A3, 271193323Sed // Not preserved across procedure calls 272239462Sdim T0, T1, T2, T3, T4, T5, T6, T7, 273193323Sed // Callee save 274193323Sed S0, S1, S2, S3, S4, S5, S6, S7, 275239462Sdim // Not preserved across procedure calls 276239462Sdim T8, T9, 277193323Sed // Reserved 278239462Sdim K0, K1, GP, SP, FP, RA)>; 279193323Sed 280243830Sdimdef CPURegs : CPURegsClass<[i32]>; 281243830Sdimdef DSPRegs : CPURegsClass<[v4i8, v2i16]>; 282243830Sdim 283226633Sdimdef CPU64Regs : RegisterClass<"Mips", [i64], 64, (add 284239462Sdim// Reserved 285239462Sdim ZERO_64, AT_64, 286226633Sdim // Return Values and Arguments 287226633Sdim V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 288226633Sdim // Not preserved across procedure calls 289239462Sdim T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 290226633Sdim // Callee save 291226633Sdim S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 292239462Sdim // Not preserved across procedure calls 293239462Sdim T8_64, T9_64, 294226633Sdim // Reserved 295239462Sdim K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 296226633Sdim 297239462Sdimdef CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 298239462Sdim // Return Values and Arguments 299239462Sdim V0, V1, A0, A1, A2, A3, 300239462Sdim // Callee save 301239462Sdim S0, S1)>; 302239462Sdim 303239462Sdimdef CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>; 304239462Sdim 305243830Sdimdef CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>; 306239462Sdim 307193323Sed// 64bit fp: 308193323Sed// * FGR64 - 32 64-bit registers 309221345Sdim// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 310193323Sed// 311193323Sed// 32bit fp: 312193323Sed// * FGR32 - 16 32-bit even registers 313193323Sed// * FGR32 - 32 32-bit registers (single float only mode) 314224145Sdimdef FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 315193323Sed 316224145Sdimdef AFGR64 : RegisterClass<"Mips", [f64], 64, (add 317193323Sed // Return Values and Arguments 318239462Sdim D0, D1, 319193323Sed // Not preserved across procedure calls 320239462Sdim D2, D3, D4, D5, 321239462Sdim // Return Values and Arguments 322239462Sdim D6, D7, 323239462Sdim // Not preserved across procedure calls 324239462Sdim D8, D9, 325193323Sed // Callee save 326239462Sdim D10, D11, D12, D13, D14, D15)>; 327193323Sed 328239462Sdimdef FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 329226633Sdim 330193323Sed// Condition Register for floating point operations 331239462Sdimdef CCR : RegisterClass<"Mips", [i32], 32, (add FCR31,FCC0)>; 332193323Sed 333193323Sed// Hi/Lo Registers 334224145Sdimdef HILO : RegisterClass<"Mips", [i32], 32, (add HI, LO)>; 335239462Sdimdef HILO64 : RegisterClass<"Mips", [i64], 64, (add HI64, LO64)>; 336193323Sed 337223017Sdim// Hardware registers 338224145Sdimdef HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>; 339234353Sdimdef HWRegs64 : RegisterClass<"Mips", [i64], 32, (add HWR29_64)>; 340234353Sdim 341243830Sdim// Accumulator Registers 342243830Sdimdef ACRegs : RegisterClass<"Mips", [i64], 64, (sequence "AC%u", 0, 3)>; 343