1234353Sdim//===-- MipsRegisterInfo.td - Mips Register defs -----------*- tablegen -*-===// 2193323Sed// 3193323Sed// The LLVM Compiler Infrastructure 4193323Sed// 5193323Sed// This file is distributed under the University of Illinois Open Source 6193323Sed// License. See LICENSE.TXT for details. 7193323Sed// 8193323Sed//===----------------------------------------------------------------------===// 9193323Sed 10193323Sed//===----------------------------------------------------------------------===// 11193323Sed// Declarations that describe the MIPS register file 12193323Sed//===----------------------------------------------------------------------===// 13226633Sdimlet Namespace = "Mips" in { 14263508Sdimdef sub_32 : SubRegIndex<32>; 15263508Sdimdef sub_64 : SubRegIndex<64>; 16263508Sdimdef sub_lo : SubRegIndex<32>; 17263508Sdimdef sub_hi : SubRegIndex<32, 32>; 18263508Sdimdef sub_dsp16_19 : SubRegIndex<4, 16>; 19263508Sdimdef sub_dsp20 : SubRegIndex<1, 20>; 20263508Sdimdef sub_dsp21 : SubRegIndex<1, 21>; 21263508Sdimdef sub_dsp22 : SubRegIndex<1, 22>; 22263508Sdimdef sub_dsp23 : SubRegIndex<1, 23>; 23226633Sdim} 24193323Sed 25249423Sdimclass Unallocatable { 26249423Sdim bit isAllocatable = 0; 27249423Sdim} 28249423Sdim 29193323Sed// We have banks of 32 registers each. 30249423Sdimclass MipsReg<bits<16> Enc, string n> : Register<n> { 31249423Sdim let HWEncoding = Enc; 32193323Sed let Namespace = "Mips"; 33193323Sed} 34193323Sed 35249423Sdimclass MipsRegWithSubRegs<bits<16> Enc, string n, list<Register> subregs> 36199511Srdivacky : RegisterWithSubRegs<n, subregs> { 37249423Sdim let HWEncoding = Enc; 38199511Srdivacky let Namespace = "Mips"; 39199511Srdivacky} 40199511Srdivacky 41193323Sed// Mips CPU Registers 42249423Sdimclass MipsGPRReg<bits<16> Enc, string n> : MipsReg<Enc, n>; 43193323Sed 44226633Sdim// Mips 64-bit CPU Registers 45249423Sdimclass Mips64GPRReg<bits<16> Enc, string n, list<Register> subregs> 46249423Sdim : MipsRegWithSubRegs<Enc, n, subregs> { 47226633Sdim let SubRegIndices = [sub_32]; 48226633Sdim} 49226633Sdim 50193323Sed// Mips 32-bit FPU Registers 51249423Sdimclass FPR<bits<16> Enc, string n> : MipsReg<Enc, n>; 52193323Sed 53193323Sed// Mips 64-bit (aliased) FPU Registers 54249423Sdimclass AFPR<bits<16> Enc, string n, list<Register> subregs> 55249423Sdim : MipsRegWithSubRegs<Enc, n, subregs> { 56263508Sdim let SubRegIndices = [sub_lo, sub_hi]; 57234353Sdim let CoveredBySubRegs = 1; 58193323Sed} 59193323Sed 60249423Sdimclass AFPR64<bits<16> Enc, string n, list<Register> subregs> 61249423Sdim : MipsRegWithSubRegs<Enc, n, subregs> { 62263508Sdim let SubRegIndices = [sub_lo, sub_hi]; 63263508Sdim let CoveredBySubRegs = 1; 64226633Sdim} 65226633Sdim 66263508Sdim// Mips 128-bit (aliased) MSA Registers 67263508Sdimclass AFPR128<bits<16> Enc, string n, list<Register> subregs> 68263508Sdim : MipsRegWithSubRegs<Enc, n, subregs> { 69263508Sdim let SubRegIndices = [sub_64]; 70263508Sdim} 71263508Sdim 72249423Sdim// Accumulator Registers 73263508Sdimclass ACCReg<bits<16> Enc, string n, list<Register> subregs> 74249423Sdim : MipsRegWithSubRegs<Enc, n, subregs> { 75249423Sdim let SubRegIndices = [sub_lo, sub_hi]; 76249423Sdim let CoveredBySubRegs = 1; 77223017Sdim} 78223017Sdim 79249423Sdim// Mips Hardware Registers 80249423Sdimclass HWR<bits<16> Enc, string n> : MipsReg<Enc, n>; 81249423Sdim 82193323Sed//===----------------------------------------------------------------------===// 83193323Sed// Registers 84193323Sed//===----------------------------------------------------------------------===// 85193323Sed 86193323Sedlet Namespace = "Mips" in { 87193323Sed // General Purpose Registers 88239462Sdim def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>; 89243830Sdim def AT : MipsGPRReg< 1, "1">, DwarfRegNum<[1]>; 90193323Sed def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>; 91193323Sed def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>; 92223017Sdim def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[4]>; 93193323Sed def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>; 94193323Sed def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>; 95193323Sed def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>; 96193323Sed def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>; 97193323Sed def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>; 98193323Sed def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>; 99193323Sed def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>; 100193323Sed def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>; 101193323Sed def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>; 102193323Sed def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>; 103193323Sed def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>; 104193323Sed def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>; 105193323Sed def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>; 106193323Sed def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>; 107193323Sed def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>; 108193323Sed def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>; 109193323Sed def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>; 110193323Sed def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>; 111193323Sed def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>; 112193323Sed def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>; 113193323Sed def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>; 114193323Sed def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>; 115193323Sed def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>; 116239462Sdim def GP : MipsGPRReg< 28, "gp">, DwarfRegNum<[28]>; 117239462Sdim def SP : MipsGPRReg< 29, "sp">, DwarfRegNum<[29]>; 118239462Sdim def FP : MipsGPRReg< 30, "fp">, DwarfRegNum<[30]>; 119239462Sdim def RA : MipsGPRReg< 31, "ra">, DwarfRegNum<[31]>; 120221345Sdim 121226633Sdim // General Purpose 64-bit Registers 122239462Sdim def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>; 123243830Sdim def AT_64 : Mips64GPRReg< 1, "1", [AT]>, DwarfRegNum<[1]>; 124234353Sdim def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>; 125234353Sdim def V1_64 : Mips64GPRReg< 3, "3", [V1]>, DwarfRegNum<[3]>; 126234353Sdim def A0_64 : Mips64GPRReg< 4, "4", [A0]>, DwarfRegNum<[4]>; 127234353Sdim def A1_64 : Mips64GPRReg< 5, "5", [A1]>, DwarfRegNum<[5]>; 128234353Sdim def A2_64 : Mips64GPRReg< 6, "6", [A2]>, DwarfRegNum<[6]>; 129234353Sdim def A3_64 : Mips64GPRReg< 7, "7", [A3]>, DwarfRegNum<[7]>; 130234353Sdim def T0_64 : Mips64GPRReg< 8, "8", [T0]>, DwarfRegNum<[8]>; 131234353Sdim def T1_64 : Mips64GPRReg< 9, "9", [T1]>, DwarfRegNum<[9]>; 132234353Sdim def T2_64 : Mips64GPRReg< 10, "10", [T2]>, DwarfRegNum<[10]>; 133234353Sdim def T3_64 : Mips64GPRReg< 11, "11", [T3]>, DwarfRegNum<[11]>; 134234353Sdim def T4_64 : Mips64GPRReg< 12, "12", [T4]>, DwarfRegNum<[12]>; 135234353Sdim def T5_64 : Mips64GPRReg< 13, "13", [T5]>, DwarfRegNum<[13]>; 136234353Sdim def T6_64 : Mips64GPRReg< 14, "14", [T6]>, DwarfRegNum<[14]>; 137234353Sdim def T7_64 : Mips64GPRReg< 15, "15", [T7]>, DwarfRegNum<[15]>; 138234353Sdim def S0_64 : Mips64GPRReg< 16, "16", [S0]>, DwarfRegNum<[16]>; 139234353Sdim def S1_64 : Mips64GPRReg< 17, "17", [S1]>, DwarfRegNum<[17]>; 140234353Sdim def S2_64 : Mips64GPRReg< 18, "18", [S2]>, DwarfRegNum<[18]>; 141234353Sdim def S3_64 : Mips64GPRReg< 19, "19", [S3]>, DwarfRegNum<[19]>; 142234353Sdim def S4_64 : Mips64GPRReg< 20, "20", [S4]>, DwarfRegNum<[20]>; 143234353Sdim def S5_64 : Mips64GPRReg< 21, "21", [S5]>, DwarfRegNum<[21]>; 144234353Sdim def S6_64 : Mips64GPRReg< 22, "22", [S6]>, DwarfRegNum<[22]>; 145234353Sdim def S7_64 : Mips64GPRReg< 23, "23", [S7]>, DwarfRegNum<[23]>; 146234353Sdim def T8_64 : Mips64GPRReg< 24, "24", [T8]>, DwarfRegNum<[24]>; 147234353Sdim def T9_64 : Mips64GPRReg< 25, "25", [T9]>, DwarfRegNum<[25]>; 148234353Sdim def K0_64 : Mips64GPRReg< 26, "26", [K0]>, DwarfRegNum<[26]>; 149234353Sdim def K1_64 : Mips64GPRReg< 27, "27", [K1]>, DwarfRegNum<[27]>; 150239462Sdim def GP_64 : Mips64GPRReg< 28, "gp", [GP]>, DwarfRegNum<[28]>; 151239462Sdim def SP_64 : Mips64GPRReg< 29, "sp", [SP]>, DwarfRegNum<[29]>; 152239462Sdim def FP_64 : Mips64GPRReg< 30, "fp", [FP]>, DwarfRegNum<[30]>; 153239462Sdim def RA_64 : Mips64GPRReg< 31, "ra", [RA]>, DwarfRegNum<[31]>; 154226633Sdim 155193323Sed /// Mips Single point precision FPU Registers 156263508Sdim foreach I = 0-31 in 157263508Sdim def F#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 158221345Sdim 159263508Sdim // Higher half of 64-bit FP registers. 160263508Sdim foreach I = 0-31 in 161263508Sdim def F_HI#I : FPR<I, "f"#I>, DwarfRegNum<[!add(I, 32)]>; 162263508Sdim 163193323Sed /// Mips Double point precision FPU Registers (aliased 164193323Sed /// with the single precision to hold 64 bit values) 165263508Sdim foreach I = 0-15 in 166263508Sdim def D#I : AFPR<!shl(I, 1), "f"#!shl(I, 1), 167263508Sdim [!cast<FPR>("F"#!shl(I, 1)), 168263508Sdim !cast<FPR>("F"#!add(!shl(I, 1), 1))]>; 169193323Sed 170226633Sdim /// Mips Double point precision FPU Registers in MFP64 mode. 171263508Sdim foreach I = 0-31 in 172263508Sdim def D#I#_64 : AFPR64<I, "f"#I, [!cast<FPR>("F"#I), !cast<FPR>("F_HI"#I)]>, 173263508Sdim DwarfRegNum<[!add(I, 32)]>; 174226633Sdim 175263508Sdim /// Mips MSA registers 176263508Sdim /// MSA and FPU cannot both be present unless the FPU has 64-bit registers 177263508Sdim foreach I = 0-31 in 178263508Sdim def W#I : AFPR128<I, "w"#I, [!cast<AFPR64>("D"#I#"_64")]>, 179263508Sdim DwarfRegNum<[!add(I, 32)]>; 180263508Sdim 181193323Sed // Hi/Lo registers 182263508Sdim def HI0 : MipsReg<0, "ac0">, DwarfRegNum<[64]>; 183263508Sdim def HI1 : MipsReg<1, "ac1">, DwarfRegNum<[176]>; 184263508Sdim def HI2 : MipsReg<2, "ac2">, DwarfRegNum<[178]>; 185263508Sdim def HI3 : MipsReg<3, "ac3">, DwarfRegNum<[180]>; 186263508Sdim def LO0 : MipsReg<0, "ac0">, DwarfRegNum<[65]>; 187263508Sdim def LO1 : MipsReg<1, "ac1">, DwarfRegNum<[177]>; 188263508Sdim def LO2 : MipsReg<2, "ac2">, DwarfRegNum<[179]>; 189263508Sdim def LO3 : MipsReg<3, "ac3">, DwarfRegNum<[181]>; 190193323Sed 191226633Sdim let SubRegIndices = [sub_32] in { 192263508Sdim def HI0_64 : RegisterWithSubRegs<"hi", [HI0]>; 193263508Sdim def LO0_64 : RegisterWithSubRegs<"lo", [LO0]>; 194226633Sdim } 195226633Sdim 196263508Sdim // FP control registers. 197263508Sdim foreach I = 0-31 in 198263508Sdim def FCR#I : MipsReg<#I, ""#I>; 199223017Sdim 200263508Sdim // FP condition code registers. 201263508Sdim foreach I = 0-7 in 202263508Sdim def FCC#I : MipsReg<#I, "fcc"#I>; 203239462Sdim 204263508Sdim // COP2 registers. 205263508Sdim foreach I = 0-31 in 206263508Sdim def COP2#I : MipsReg<#I, ""#I>; 207263508Sdim 208243830Sdim // PC register 209243830Sdim def PC : Register<"pc">; 210243830Sdim 211223017Sdim // Hardware register $29 212249423Sdim def HWR29 : MipsReg<29, "29">; 213243830Sdim 214243830Sdim // Accum registers 215263508Sdim foreach I = 0-3 in 216263508Sdim def AC#I : ACCReg<#I, "ac"#I, 217263508Sdim [!cast<Register>("LO"#I), !cast<Register>("HI"#I)]>; 218243830Sdim 219263508Sdim def AC0_64 : ACCReg<0, "ac0", [LO0_64, HI0_64]>; 220249423Sdim 221251662Sdim // DSP-ASE control register fields. 222251662Sdim def DSPPos : Register<"">; 223251662Sdim def DSPSCount : Register<"">; 224251662Sdim def DSPCarry : Register<"">; 225251662Sdim def DSPEFI : Register<"">; 226251662Sdim def DSPOutFlag16_19 : Register<"">; 227251662Sdim def DSPOutFlag20 : Register<"">; 228251662Sdim def DSPOutFlag21 : Register<"">; 229251662Sdim def DSPOutFlag22 : Register<"">; 230251662Sdim def DSPOutFlag23 : Register<"">; 231251662Sdim def DSPCCond : Register<"">; 232251662Sdim 233251662Sdim let SubRegIndices = [sub_dsp16_19, sub_dsp20, sub_dsp21, sub_dsp22, 234251662Sdim sub_dsp23] in 235251662Sdim def DSPOutFlag : RegisterWithSubRegs<"", [DSPOutFlag16_19, DSPOutFlag20, 236251662Sdim DSPOutFlag21, DSPOutFlag22, 237251662Sdim DSPOutFlag23]>; 238263508Sdim 239263508Sdim // MSA-ASE control registers. 240263508Sdim def MSAIR : MipsReg<0, "0">; 241263508Sdim def MSACSR : MipsReg<1, "1">; 242263508Sdim def MSAAccess : MipsReg<2, "2">; 243263508Sdim def MSASave : MipsReg<3, "3">; 244263508Sdim def MSAModify : MipsReg<4, "4">; 245263508Sdim def MSARequest : MipsReg<5, "5">; 246263508Sdim def MSAMap : MipsReg<6, "6">; 247263508Sdim def MSAUnmap : MipsReg<7, "7">; 248193323Sed} 249193323Sed 250193323Sed//===----------------------------------------------------------------------===// 251193323Sed// Register Classes 252193323Sed//===----------------------------------------------------------------------===// 253193323Sed 254263508Sdimclass GPR32Class<list<ValueType> regTypes> : 255243830Sdim RegisterClass<"Mips", regTypes, 32, (add 256239462Sdim // Reserved 257239462Sdim ZERO, AT, 258193323Sed // Return Values and Arguments 259224145Sdim V0, V1, A0, A1, A2, A3, 260193323Sed // Not preserved across procedure calls 261239462Sdim T0, T1, T2, T3, T4, T5, T6, T7, 262193323Sed // Callee save 263193323Sed S0, S1, S2, S3, S4, S5, S6, S7, 264239462Sdim // Not preserved across procedure calls 265239462Sdim T8, T9, 266193323Sed // Reserved 267239462Sdim K0, K1, GP, SP, FP, RA)>; 268193323Sed 269263508Sdimdef GPR32 : GPR32Class<[i32]>; 270263508Sdimdef DSPR : GPR32Class<[v4i8, v2i16]>; 271243830Sdim 272263508Sdimdef GPR64 : RegisterClass<"Mips", [i64], 64, (add 273239462Sdim// Reserved 274239462Sdim ZERO_64, AT_64, 275226633Sdim // Return Values and Arguments 276226633Sdim V0_64, V1_64, A0_64, A1_64, A2_64, A3_64, 277226633Sdim // Not preserved across procedure calls 278239462Sdim T0_64, T1_64, T2_64, T3_64, T4_64, T5_64, T6_64, T7_64, 279226633Sdim // Callee save 280226633Sdim S0_64, S1_64, S2_64, S3_64, S4_64, S5_64, S6_64, S7_64, 281239462Sdim // Not preserved across procedure calls 282239462Sdim T8_64, T9_64, 283226633Sdim // Reserved 284239462Sdim K0_64, K1_64, GP_64, SP_64, FP_64, RA_64)>; 285226633Sdim 286239462Sdimdef CPU16Regs : RegisterClass<"Mips", [i32], 32, (add 287239462Sdim // Return Values and Arguments 288239462Sdim V0, V1, A0, A1, A2, A3, 289239462Sdim // Callee save 290239462Sdim S0, S1)>; 291239462Sdim 292263508Sdimdef CPU16RegsPlusSP : RegisterClass<"Mips", [i32], 32, (add 293263508Sdim // Return Values and Arguments 294263508Sdim V0, V1, A0, A1, A2, A3, 295263508Sdim // Callee save 296263508Sdim S0, S1, 297263508Sdim SP)>; 298263508Sdim 299249423Sdimdef CPURAReg : RegisterClass<"Mips", [i32], 32, (add RA)>, Unallocatable; 300239462Sdim 301249423Sdimdef CPUSPReg : RegisterClass<"Mips", [i32], 32, (add SP)>, Unallocatable; 302239462Sdim 303193323Sed// 64bit fp: 304193323Sed// * FGR64 - 32 64-bit registers 305221345Sdim// * AFGR64 - 16 32-bit even registers (32-bit FP Mode) 306193323Sed// 307193323Sed// 32bit fp: 308193323Sed// * FGR32 - 16 32-bit even registers 309193323Sed// * FGR32 - 32 32-bit registers (single float only mode) 310224145Sdimdef FGR32 : RegisterClass<"Mips", [f32], 32, (sequence "F%u", 0, 31)>; 311193323Sed 312263508Sdimdef FGRH32 : RegisterClass<"Mips", [f32], 32, (sequence "F_HI%u", 0, 31)>, 313263508Sdim Unallocatable; 314263508Sdim 315224145Sdimdef AFGR64 : RegisterClass<"Mips", [f64], 64, (add 316193323Sed // Return Values and Arguments 317239462Sdim D0, D1, 318193323Sed // Not preserved across procedure calls 319239462Sdim D2, D3, D4, D5, 320239462Sdim // Return Values and Arguments 321239462Sdim D6, D7, 322239462Sdim // Not preserved across procedure calls 323239462Sdim D8, D9, 324193323Sed // Callee save 325239462Sdim D10, D11, D12, D13, D14, D15)>; 326193323Sed 327239462Sdimdef FGR64 : RegisterClass<"Mips", [f64], 64, (sequence "D%u_64", 0, 31)>; 328226633Sdim 329263508Sdim// FP control registers. 330263508Sdimdef CCR : RegisterClass<"Mips", [i32], 32, (sequence "FCR%u", 0, 31)>, 331263508Sdim Unallocatable; 332193323Sed 333263508Sdim// FP condition code registers. 334263508Sdimdef FCC : RegisterClass<"Mips", [i32], 32, (sequence "FCC%u", 0, 7)>, 335263508Sdim Unallocatable; 336263508Sdim 337263508Sdimdef MSA128B: RegisterClass<"Mips", [v16i8], 128, 338263508Sdim (sequence "W%u", 0, 31)>; 339263508Sdimdef MSA128H: RegisterClass<"Mips", [v8i16, v8f16], 128, 340263508Sdim (sequence "W%u", 0, 31)>; 341263508Sdimdef MSA128W: RegisterClass<"Mips", [v4i32, v4f32], 128, 342263508Sdim (sequence "W%u", 0, 31)>; 343263508Sdimdef MSA128D: RegisterClass<"Mips", [v2i64, v2f64], 128, 344263508Sdim (sequence "W%u", 0, 31)>; 345263508Sdim 346263508Sdimdef MSACtrl: RegisterClass<"Mips", [i32], 32, (add 347263508Sdim MSAIR, MSACSR, MSAAccess, MSASave, MSAModify, MSARequest, MSAMap, MSAUnmap)>; 348263508Sdim 349193323Sed// Hi/Lo Registers 350263508Sdimdef LO32 : RegisterClass<"Mips", [i32], 32, (add LO0)>; 351263508Sdimdef HI32 : RegisterClass<"Mips", [i32], 32, (add HI0)>; 352263508Sdimdef LO32DSP : RegisterClass<"Mips", [i32], 32, (sequence "LO%u", 0, 3)>; 353263508Sdimdef HI32DSP : RegisterClass<"Mips", [i32], 32, (sequence "HI%u", 0, 3)>; 354263508Sdimdef LO64 : RegisterClass<"Mips", [i64], 64, (add LO0_64)>; 355263508Sdimdef HI64 : RegisterClass<"Mips", [i64], 64, (add HI0_64)>; 356193323Sed 357223017Sdim// Hardware registers 358249423Sdimdef HWRegs : RegisterClass<"Mips", [i32], 32, (add HWR29)>, Unallocatable; 359234353Sdim 360243830Sdim// Accumulator Registers 361263508Sdimdef ACC64 : RegisterClass<"Mips", [untyped], 64, (add AC0)> { 362249423Sdim let Size = 64; 363249423Sdim} 364249423Sdim 365263508Sdimdef ACC128 : RegisterClass<"Mips", [untyped], 128, (add AC0_64)> { 366249423Sdim let Size = 128; 367249423Sdim} 368249423Sdim 369263508Sdimdef ACC64DSP : RegisterClass<"Mips", [untyped], 64, (sequence "AC%u", 0, 3)> { 370249423Sdim let Size = 64; 371249423Sdim} 372249423Sdim 373251662Sdimdef DSPCC : RegisterClass<"Mips", [v4i8, v2i16], 32, (add DSPCCond)>; 374251662Sdim 375263508Sdim// Coprocessor 2 registers. 376263508Sdimdef COP2 : RegisterClass<"Mips", [i32], 32, (sequence "COP2%u", 0, 31)>, 377263508Sdim Unallocatable; 378263508Sdim 379251662Sdim// Register Operands. 380263508Sdim 381263508Sdimclass MipsAsmRegOperand : AsmOperandClass { 382263508Sdim let RenderMethod = "addRegAsmOperands"; 383249423Sdim} 384263508Sdimdef GPR32AsmOperand : MipsAsmRegOperand { 385263508Sdim let Name = "GPR32Asm"; 386263508Sdim let ParserMethod = "parseGPR32"; 387263508Sdim} 388249423Sdim 389263508Sdimdef GPR64AsmOperand : MipsAsmRegOperand { 390263508Sdim let Name = "GPR64Asm"; 391263508Sdim let ParserMethod = "parseGPR64"; 392249423Sdim} 393249423Sdim 394263508Sdimdef ACC64DSPAsmOperand : MipsAsmRegOperand { 395263508Sdim let Name = "ACC64DSPAsm"; 396263508Sdim let ParserMethod = "parseACC64DSP"; 397263508Sdim} 398263508Sdim 399263508Sdimdef LO32DSPAsmOperand : MipsAsmRegOperand { 400263508Sdim let Name = "LO32DSPAsm"; 401263508Sdim let ParserMethod = "parseLO32DSP"; 402263508Sdim} 403263508Sdim 404263508Sdimdef HI32DSPAsmOperand : MipsAsmRegOperand { 405263508Sdim let Name = "HI32DSPAsm"; 406263508Sdim let ParserMethod = "parseHI32DSP"; 407263508Sdim} 408263508Sdim 409263508Sdimdef CCRAsmOperand : MipsAsmRegOperand { 410249423Sdim let Name = "CCRAsm"; 411249423Sdim let ParserMethod = "parseCCRRegs"; 412249423Sdim} 413249423Sdim 414263508Sdimdef AFGR64AsmOperand : MipsAsmRegOperand { 415263508Sdim let Name = "AFGR64Asm"; 416263508Sdim let ParserMethod = "parseAFGR64Regs"; 417249423Sdim} 418249423Sdim 419263508Sdimdef FGR64AsmOperand : MipsAsmRegOperand { 420263508Sdim let Name = "FGR64Asm"; 421263508Sdim let ParserMethod = "parseFGR64Regs"; 422249423Sdim} 423249423Sdim 424263508Sdimdef FGR32AsmOperand : MipsAsmRegOperand { 425263508Sdim let Name = "FGR32Asm"; 426263508Sdim let ParserMethod = "parseFGR32Regs"; 427263508Sdim} 428263508Sdim 429263508Sdimdef FGRH32AsmOperand : MipsAsmRegOperand { 430263508Sdim let Name = "FGRH32Asm"; 431263508Sdim let ParserMethod = "parseFGRH32Regs"; 432263508Sdim} 433263508Sdim 434263508Sdimdef FCCRegsAsmOperand : MipsAsmRegOperand { 435263508Sdim let Name = "FCCRegsAsm"; 436263508Sdim let ParserMethod = "parseFCCRegs"; 437263508Sdim} 438263508Sdim 439263508Sdimdef MSA128BAsmOperand : MipsAsmRegOperand { 440263508Sdim let Name = "MSA128BAsm"; 441263508Sdim let ParserMethod = "parseMSA128BRegs"; 442263508Sdim} 443263508Sdim 444263508Sdimdef MSA128HAsmOperand : MipsAsmRegOperand { 445263508Sdim let Name = "MSA128HAsm"; 446263508Sdim let ParserMethod = "parseMSA128HRegs"; 447263508Sdim} 448263508Sdim 449263508Sdimdef MSA128WAsmOperand : MipsAsmRegOperand { 450263508Sdim let Name = "MSA128WAsm"; 451263508Sdim let ParserMethod = "parseMSA128WRegs"; 452263508Sdim} 453263508Sdim 454263508Sdimdef MSA128DAsmOperand : MipsAsmRegOperand { 455263508Sdim let Name = "MSA128DAsm"; 456263508Sdim let ParserMethod = "parseMSA128DRegs"; 457263508Sdim} 458263508Sdim 459263508Sdimdef MSA128CRAsmOperand : MipsAsmRegOperand { 460263508Sdim let Name = "MSA128CRAsm"; 461263508Sdim let ParserMethod = "parseMSA128CtrlRegs"; 462263508Sdim} 463263508Sdim 464263508Sdimdef GPR32Opnd : RegisterOperand<GPR32> { 465263508Sdim let ParserMatchClass = GPR32AsmOperand; 466263508Sdim} 467263508Sdim 468263508Sdimdef GPR64Opnd : RegisterOperand<GPR64> { 469263508Sdim let ParserMatchClass = GPR64AsmOperand; 470263508Sdim} 471263508Sdim 472263508Sdimdef DSPROpnd : RegisterOperand<DSPR> { 473263508Sdim let ParserMatchClass = GPR32AsmOperand; 474263508Sdim} 475263508Sdim 476263508Sdimdef CCROpnd : RegisterOperand<CCR> { 477249423Sdim let ParserMatchClass = CCRAsmOperand; 478249423Sdim} 479249423Sdim 480263508Sdimdef HWRegsAsmOperand : MipsAsmRegOperand { 481249423Sdim let Name = "HWRegsAsm"; 482249423Sdim let ParserMethod = "parseHWRegs"; 483249423Sdim} 484249423Sdim 485263508Sdimdef COP2AsmOperand : MipsAsmRegOperand { 486263508Sdim let Name = "COP2Asm"; 487263508Sdim let ParserMethod = "parseCOP2"; 488249423Sdim} 489249423Sdim 490263508Sdimdef HWRegsOpnd : RegisterOperand<HWRegs> { 491249423Sdim let ParserMatchClass = HWRegsAsmOperand; 492249423Sdim} 493249423Sdim 494263508Sdimdef AFGR64Opnd : RegisterOperand<AFGR64> { 495263508Sdim let ParserMatchClass = AFGR64AsmOperand; 496249423Sdim} 497263508Sdim 498263508Sdimdef FGR64Opnd : RegisterOperand<FGR64> { 499263508Sdim let ParserMatchClass = FGR64AsmOperand; 500263508Sdim} 501263508Sdim 502263508Sdimdef FGR32Opnd : RegisterOperand<FGR32> { 503263508Sdim let ParserMatchClass = FGR32AsmOperand; 504263508Sdim} 505263508Sdim 506263508Sdimdef FGRH32Opnd : RegisterOperand<FGRH32> { 507263508Sdim let ParserMatchClass = FGRH32AsmOperand; 508263508Sdim} 509263508Sdim 510263508Sdimdef FCCRegsOpnd : RegisterOperand<FCC> { 511263508Sdim let ParserMatchClass = FCCRegsAsmOperand; 512263508Sdim} 513263508Sdim 514263508Sdimdef LO32DSPOpnd : RegisterOperand<LO32DSP> { 515263508Sdim let ParserMatchClass = LO32DSPAsmOperand; 516263508Sdim} 517263508Sdim 518263508Sdimdef HI32DSPOpnd : RegisterOperand<HI32DSP> { 519263508Sdim let ParserMatchClass = HI32DSPAsmOperand; 520263508Sdim} 521263508Sdim 522263508Sdimdef ACC64DSPOpnd : RegisterOperand<ACC64DSP> { 523263508Sdim let ParserMatchClass = ACC64DSPAsmOperand; 524263508Sdim} 525263508Sdim 526263508Sdimdef COP2Opnd : RegisterOperand<COP2> { 527263508Sdim let ParserMatchClass = COP2AsmOperand; 528263508Sdim} 529263508Sdim 530263508Sdimdef MSA128BOpnd : RegisterOperand<MSA128B> { 531263508Sdim let ParserMatchClass = MSA128BAsmOperand; 532263508Sdim} 533263508Sdim 534263508Sdimdef MSA128HOpnd : RegisterOperand<MSA128H> { 535263508Sdim let ParserMatchClass = MSA128HAsmOperand; 536263508Sdim} 537263508Sdim 538263508Sdimdef MSA128WOpnd : RegisterOperand<MSA128W> { 539263508Sdim let ParserMatchClass = MSA128WAsmOperand; 540263508Sdim} 541263508Sdim 542263508Sdimdef MSA128DOpnd : RegisterOperand<MSA128D> { 543263508Sdim let ParserMatchClass = MSA128DAsmOperand; 544263508Sdim} 545263508Sdim 546263508Sdimdef MSA128CROpnd : RegisterOperand<MSACtrl> { 547263508Sdim let ParserMatchClass = MSA128CRAsmOperand; 548263508Sdim} 549263508Sdim 550