1226584Sdim//===- Mips64InstrInfo.td - Mips64 Instruction Information -*- tablegen -*-===// 2226584Sdim// 3226584Sdim// The LLVM Compiler Infrastructure 4226584Sdim// 5226584Sdim// This file is distributed under the University of Illinois Open Source 6226584Sdim// License. See LICENSE.TXT for details. 7226584Sdim// 8226584Sdim//===----------------------------------------------------------------------===// 9226584Sdim// 10226584Sdim// This file describes Mips64 instructions. 11226584Sdim// 12226584Sdim//===----------------------------------------------------------------------===// 13226584Sdim 14226584Sdim//===----------------------------------------------------------------------===// 15226584Sdim// Mips Operand, Complex Patterns and Transformations Definitions. 16226584Sdim//===----------------------------------------------------------------------===// 17226584Sdim 18226584Sdim// Unsigned Operand 19226584Sdimdef uimm16_64 : Operand<i64> { 20226584Sdim let PrintMethod = "printUnsignedImm"; 21226584Sdim} 22226584Sdim 23226584Sdim// Transformation Function - get Imm - 32. 24226584Sdimdef Subtract32 : SDNodeXForm<imm, [{ 25234353Sdim return getImm(N, (unsigned)N->getZExtValue() - 32); 26226584Sdim}]>; 27226584Sdim 28234353Sdim// shamt must fit in 6 bits. 29234353Sdimdef immZExt6 : ImmLeaf<i32, [{return Imm == (Imm & 0x3f);}]>; 30226584Sdim 31226584Sdim//===----------------------------------------------------------------------===// 32226584Sdim// Instructions specific format 33226584Sdim//===----------------------------------------------------------------------===// 34263508Sdimlet usesCustomInserter = 1 in { 35263508Sdim def ATOMIC_LOAD_ADD_I64 : Atomic2Ops<atomic_load_add_64, GPR64>; 36263508Sdim def ATOMIC_LOAD_SUB_I64 : Atomic2Ops<atomic_load_sub_64, GPR64>; 37263508Sdim def ATOMIC_LOAD_AND_I64 : Atomic2Ops<atomic_load_and_64, GPR64>; 38263508Sdim def ATOMIC_LOAD_OR_I64 : Atomic2Ops<atomic_load_or_64, GPR64>; 39263508Sdim def ATOMIC_LOAD_XOR_I64 : Atomic2Ops<atomic_load_xor_64, GPR64>; 40263508Sdim def ATOMIC_LOAD_NAND_I64 : Atomic2Ops<atomic_load_nand_64, GPR64>; 41263508Sdim def ATOMIC_SWAP_I64 : Atomic2Ops<atomic_swap_64, GPR64>; 42263508Sdim def ATOMIC_CMP_SWAP_I64 : AtomicCmpSwap<atomic_cmp_swap_64, GPR64>; 43226584Sdim} 44226584Sdim 45251662Sdim/// Pseudo instructions for loading and storing accumulator registers. 46263508Sdimlet isPseudo = 1, isCodeGenOnly = 1 in { 47263508Sdim def LOAD_ACC128 : Load<"", ACC128>; 48263508Sdim def STORE_ACC128 : Store<"", ACC128>; 49249423Sdim} 50249423Sdim 51226584Sdim//===----------------------------------------------------------------------===// 52226584Sdim// Instruction definition 53226584Sdim//===----------------------------------------------------------------------===// 54234982Sdimlet DecoderNamespace = "Mips64" in { 55226584Sdim/// Arithmetic Instructions (ALU Immediate) 56263508Sdimdef DADDi : ArithLogicI<"daddi", simm16_64, GPR64Opnd>, ADDI_FM<0x18>; 57263508Sdimdef DADDiu : ArithLogicI<"daddiu", simm16_64, GPR64Opnd, IIArith, 58263508Sdim immSExt16, add>, 59249423Sdim ADDI_FM<0x19>, IsAsCheapAsAMove; 60263508Sdim 61263508Sdimlet isCodeGenOnly = 1 in { 62263508Sdimdef SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 63249423Sdim SLTI_FM<0xa>; 64263508Sdimdef SLTiu64 : SetCC_I<"sltiu", setult, simm16_64, immSExt16, GPR64Opnd>, 65249423Sdim SLTI_FM<0xb>; 66263508Sdimdef ANDi64 : ArithLogicI<"andi", uimm16_64, GPR64Opnd, IILogic, immZExt16, 67263508Sdim and>, 68263508Sdim ADDI_FM<0xc>; 69263508Sdimdef ORi64 : ArithLogicI<"ori", uimm16_64, GPR64Opnd, IILogic, immZExt16, 70263508Sdim or>, 71249423Sdim ADDI_FM<0xd>; 72263508Sdimdef XORi64 : ArithLogicI<"xori", uimm16_64, GPR64Opnd, IILogic, immZExt16, 73263508Sdim xor>, 74249423Sdim ADDI_FM<0xe>; 75263508Sdimdef LUi64 : LoadUpper<"lui", GPR64Opnd, uimm16_64>, LUI_FM; 76263508Sdim} 77226584Sdim 78226584Sdim/// Arithmetic Instructions (3-Operand, R-Type) 79263508Sdimdef DADD : ArithLogicR<"dadd", GPR64Opnd>, ADD_FM<0, 0x2c>; 80263508Sdimdef DADDu : ArithLogicR<"daddu", GPR64Opnd, 1, IIArith, add>, 81249423Sdim ADD_FM<0, 0x2d>; 82263508Sdimdef DSUBu : ArithLogicR<"dsubu", GPR64Opnd, 0, IIArith, sub>, 83249423Sdim ADD_FM<0, 0x2f>; 84226584Sdim 85263508Sdimlet isCodeGenOnly = 1 in { 86263508Sdimdef SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>; 87263508Sdimdef SLTu64 : SetCC_R<"sltu", setult, GPR64Opnd>, ADD_FM<0, 0x2b>; 88263508Sdimdef AND64 : ArithLogicR<"and", GPR64Opnd, 1, IIArith, and>, ADD_FM<0, 0x24>; 89263508Sdimdef OR64 : ArithLogicR<"or", GPR64Opnd, 1, IIArith, or>, ADD_FM<0, 0x25>; 90263508Sdimdef XOR64 : ArithLogicR<"xor", GPR64Opnd, 1, IIArith, xor>, ADD_FM<0, 0x26>; 91263508Sdimdef NOR64 : LogicNOR<"nor", GPR64Opnd>, ADD_FM<0, 0x27>; 92263508Sdim} 93263508Sdim 94226584Sdim/// Shift Instructions 95263508Sdimdef DSLL : shift_rotate_imm<"dsll", uimm6, GPR64Opnd, shl, immZExt6>, 96249423Sdim SRA_FM<0x38, 0>; 97263508Sdimdef DSRL : shift_rotate_imm<"dsrl", uimm6, GPR64Opnd, srl, immZExt6>, 98249423Sdim SRA_FM<0x3a, 0>; 99263508Sdimdef DSRA : shift_rotate_imm<"dsra", uimm6, GPR64Opnd, sra, immZExt6>, 100249423Sdim SRA_FM<0x3b, 0>; 101263508Sdimdef DSLLV : shift_rotate_reg<"dsllv", GPR64Opnd, shl>, SRLV_FM<0x14, 0>; 102263508Sdimdef DSRLV : shift_rotate_reg<"dsrlv", GPR64Opnd, srl>, SRLV_FM<0x16, 0>; 103263508Sdimdef DSRAV : shift_rotate_reg<"dsrav", GPR64Opnd, sra>, SRLV_FM<0x17, 0>; 104263508Sdimdef DSLL32 : shift_rotate_imm<"dsll32", uimm5, GPR64Opnd>, SRA_FM<0x3c, 0>; 105263508Sdimdef DSRL32 : shift_rotate_imm<"dsrl32", uimm5, GPR64Opnd>, SRA_FM<0x3e, 0>; 106263508Sdimdef DSRA32 : shift_rotate_imm<"dsra32", uimm5, GPR64Opnd>, SRA_FM<0x3f, 0>; 107263508Sdim 108226584Sdim// Rotate Instructions 109263508Sdimlet Predicates = [HasMips64r2, HasStdEnc] in { 110263508Sdim def DROTR : shift_rotate_imm<"drotr", uimm6, GPR64Opnd, rotr, immZExt6>, 111249423Sdim SRA_FM<0x3a, 1>; 112263508Sdim def DROTRV : shift_rotate_reg<"drotrv", GPR64Opnd, rotr>, 113249423Sdim SRLV_FM<0x16, 1>; 114263508Sdim def DROTR32 : shift_rotate_imm<"drotr32", uimm5, GPR64Opnd>, SRA_FM<0x3e, 1>; 115226584Sdim} 116226584Sdim 117226584Sdim/// Load and Store Instructions 118234353Sdim/// aligned 119263508Sdimlet isCodeGenOnly = 1 in { 120263508Sdimdef LB64 : Load<"lb", GPR64Opnd, sextloadi8, IILoad>, LW_FM<0x20>; 121263508Sdimdef LBu64 : Load<"lbu", GPR64Opnd, zextloadi8, IILoad>, LW_FM<0x24>; 122263508Sdimdef LH64 : Load<"lh", GPR64Opnd, sextloadi16, IILoad>, LW_FM<0x21>; 123263508Sdimdef LHu64 : Load<"lhu", GPR64Opnd, zextloadi16, IILoad>, LW_FM<0x25>; 124263508Sdimdef LW64 : Load<"lw", GPR64Opnd, sextloadi32, IILoad>, LW_FM<0x23>; 125263508Sdimdef SB64 : Store<"sb", GPR64Opnd, truncstorei8, IIStore>, LW_FM<0x28>; 126263508Sdimdef SH64 : Store<"sh", GPR64Opnd, truncstorei16, IIStore>, LW_FM<0x29>; 127263508Sdimdef SW64 : Store<"sw", GPR64Opnd, truncstorei32, IIStore>, LW_FM<0x2b>; 128263508Sdim} 129226584Sdim 130263508Sdimdef LWu : Load<"lwu", GPR64Opnd, zextloadi32, IILoad>, LW_FM<0x27>; 131263508Sdimdef LD : Load<"ld", GPR64Opnd, load, IILoad>, LW_FM<0x37>; 132263508Sdimdef SD : Store<"sd", GPR64Opnd, store, IIStore>, LW_FM<0x3f>; 133263508Sdim 134239462Sdim/// load/store left/right 135263508Sdimlet isCodeGenOnly = 1 in { 136263508Sdimdef LWL64 : LoadLeftRight<"lwl", MipsLWL, GPR64Opnd, IILoad>, LW_FM<0x22>; 137263508Sdimdef LWR64 : LoadLeftRight<"lwr", MipsLWR, GPR64Opnd, IILoad>, LW_FM<0x26>; 138263508Sdimdef SWL64 : StoreLeftRight<"swl", MipsSWL, GPR64Opnd, IIStore>, LW_FM<0x2a>; 139263508Sdimdef SWR64 : StoreLeftRight<"swr", MipsSWR, GPR64Opnd, IIStore>, LW_FM<0x2e>; 140263508Sdim} 141239462Sdim 142263508Sdimdef LDL : LoadLeftRight<"ldl", MipsLDL, GPR64Opnd, IILoad>, LW_FM<0x1a>; 143263508Sdimdef LDR : LoadLeftRight<"ldr", MipsLDR, GPR64Opnd, IILoad>, LW_FM<0x1b>; 144263508Sdimdef SDL : StoreLeftRight<"sdl", MipsSDL, GPR64Opnd, IIStore>, LW_FM<0x2c>; 145263508Sdimdef SDR : StoreLeftRight<"sdr", MipsSDR, GPR64Opnd, IIStore>, LW_FM<0x2d>; 146249423Sdim 147234353Sdim/// Load-linked, Store-conditional 148263508Sdimdef LLD : LLBase<"lld", GPR64Opnd>, LW_FM<0x34>; 149263508Sdimdef SCD : SCBase<"scd", GPR64Opnd>, LW_FM<0x3c>; 150249423Sdim 151226584Sdim/// Jump and Branch Instructions 152263508Sdimlet isCodeGenOnly = 1 in { 153263508Sdimdef JR64 : IndirectBranch<"jr", GPR64Opnd>, MTLO_FM<8>; 154263508Sdimdef BEQ64 : CBranch<"beq", brtarget, seteq, GPR64Opnd>, BEQ_FM<4>; 155263508Sdimdef BNE64 : CBranch<"bne", brtarget, setne, GPR64Opnd>, BEQ_FM<5>; 156263508Sdimdef BGEZ64 : CBranchZero<"bgez", brtarget, setge, GPR64Opnd>, BGEZ_FM<1, 1>; 157263508Sdimdef BGTZ64 : CBranchZero<"bgtz", brtarget, setgt, GPR64Opnd>, BGEZ_FM<7, 0>; 158263508Sdimdef BLEZ64 : CBranchZero<"blez", brtarget, setle, GPR64Opnd>, BGEZ_FM<6, 0>; 159263508Sdimdef BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; 160263508Sdimdef JALR64 : JumpLinkReg<"jalr", GPR64Opnd>, JALR_FM; 161263508Sdimdef JALR64Pseudo : JumpLinkRegPseudo<GPR64Opnd, JALR, RA, GPR32Opnd>; 162263508Sdimdef TAILCALL64_R : JumpFR<"tcallr", GPR64Opnd, MipsTailCall>, 163263508Sdim MTLO_FM<8>, IsTailCall; 164234982Sdim} 165234353Sdim 166226584Sdim/// Multiply and Divide Instructions. 167263508Sdimdef DMULT : Mult<"dmult", IIImult, GPR64Opnd, [HI0_64, LO0_64]>, 168249423Sdim MULT_FM<0, 0x1c>; 169263508Sdimdef DMULTu : Mult<"dmultu", IIImult, GPR64Opnd, [HI0_64, LO0_64]>, 170249423Sdim MULT_FM<0, 0x1d>; 171263508Sdimdef PseudoDMULT : MultDivPseudo<DMULT, ACC128, GPR64Opnd, MipsMult, 172263508Sdim IIImult>; 173263508Sdimdef PseudoDMULTu : MultDivPseudo<DMULTu, ACC128, GPR64Opnd, MipsMultu, 174263508Sdim IIImult>; 175263508Sdimdef DSDIV : Div<"ddiv", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1e>; 176263508Sdimdef DUDIV : Div<"ddivu", IIIdiv, GPR64Opnd, [HI0_64, LO0_64]>, MULT_FM<0, 0x1f>; 177263508Sdimdef PseudoDSDIV : MultDivPseudo<DSDIV, ACC128, GPR64Opnd, MipsDivRem, 178263508Sdim IIIdiv, 0, 1, 1>; 179263508Sdimdef PseudoDUDIV : MultDivPseudo<DUDIV, ACC128, GPR64Opnd, MipsDivRemU, 180263508Sdim IIIdiv, 0, 1, 1>; 181226584Sdim 182263508Sdimlet isCodeGenOnly = 1 in { 183263508Sdimdef MTHI64 : MoveToLOHI<"mthi", GPR64Opnd, [HI0_64]>, MTLO_FM<0x11>; 184263508Sdimdef MTLO64 : MoveToLOHI<"mtlo", GPR64Opnd, [LO0_64]>, MTLO_FM<0x13>; 185263508Sdimdef MFHI64 : MoveFromLOHI<"mfhi", GPR64Opnd, AC0_64>, MFLO_FM<0x10>; 186263508Sdimdef MFLO64 : MoveFromLOHI<"mflo", GPR64Opnd, AC0_64>, MFLO_FM<0x12>; 187263508Sdimdef PseudoMFHI64 : PseudoMFLOHI<GPR64, ACC128, MipsMFHI>; 188263508Sdimdef PseudoMFLO64 : PseudoMFLOHI<GPR64, ACC128, MipsMFLO>; 189263508Sdimdef PseudoMTLOHI64 : PseudoMTLOHI<ACC128, GPR64>; 190226584Sdim 191234353Sdim/// Sign Ext In Register Instructions. 192263508Sdimdef SEB64 : SignExtInReg<"seb", i8, GPR64Opnd>, SEB_FM<0x10, 0x20>; 193263508Sdimdef SEH64 : SignExtInReg<"seh", i16, GPR64Opnd>, SEB_FM<0x18, 0x20>; 194263508Sdim} 195226584Sdim 196226584Sdim/// Count Leading 197263508Sdimdef DCLZ : CountLeading0<"dclz", GPR64Opnd>, CLO_FM<0x24>; 198263508Sdimdef DCLO : CountLeading1<"dclo", GPR64Opnd>, CLO_FM<0x25>; 199226584Sdim 200234353Sdim/// Double Word Swap Bytes/HalfWords 201263508Sdimdef DSBH : SubwordSwap<"dsbh", GPR64Opnd>, SEB_FM<2, 0x24>; 202263508Sdimdef DSHD : SubwordSwap<"dshd", GPR64Opnd>, SEB_FM<5, 0x24>; 203234353Sdim 204263508Sdimdef LEA_ADDiu64 : EffectiveAddress<"daddiu", GPR64Opnd>, LW_FM<0x19>; 205249423Sdim 206263508Sdimlet isCodeGenOnly = 1 in 207263508Sdimdef RDHWR64 : ReadHardware<GPR64Opnd, HWRegsOpnd>, RDHWR_FM; 208234353Sdim 209263508Sdimdef DEXT : ExtBase<"dext", GPR64Opnd, uimm6, MipsExt>, EXT_FM<3>; 210263508Sdimdef DEXTU : ExtBase<"dextu", GPR64Opnd, uimm6>, EXT_FM<2>; 211263508Sdimdef DEXTM : ExtBase<"dextm", GPR64Opnd, uimm5>, EXT_FM<1>; 212234353Sdim 213263508Sdimdef DINS : InsBase<"dins", GPR64Opnd, uimm6, MipsIns>, EXT_FM<7>; 214263508Sdimdef DINSU : InsBase<"dinsu", GPR64Opnd, uimm6>, EXT_FM<6>; 215263508Sdimdef DINSM : InsBase<"dinsm", GPR64Opnd, uimm5>, EXT_FM<5>; 216263508Sdim 217239462Sdimlet isCodeGenOnly = 1, rs = 0, shamt = 0 in { 218263508Sdim def DSLL64_32 : FR<0x00, 0x3c, (outs GPR64:$rd), (ins GPR32:$rt), 219263508Sdim "dsll\t$rd, $rt, 32", [], IIArith>; 220263508Sdim def SLL64_32 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR32:$rt), 221263508Sdim "sll\t$rd, $rt, 0", [], IIArith>; 222263508Sdim def SLL64_64 : FR<0x0, 0x00, (outs GPR64:$rd), (ins GPR64:$rt), 223263508Sdim "sll\t$rd, $rt, 0", [], IIArith>; 224234982Sdim} 225239462Sdim} 226226584Sdim//===----------------------------------------------------------------------===// 227226584Sdim// Arbitrary patterns that map to one or more instructions 228226584Sdim//===----------------------------------------------------------------------===// 229226584Sdim 230234353Sdim// extended loads 231263508Sdimlet Predicates = [HasStdEnc] in { 232239462Sdim def : MipsPat<(i64 (extloadi1 addr:$src)), (LB64 addr:$src)>; 233239462Sdim def : MipsPat<(i64 (extloadi8 addr:$src)), (LB64 addr:$src)>; 234243830Sdim def : MipsPat<(i64 (extloadi16 addr:$src)), (LH64 addr:$src)>; 235243830Sdim def : MipsPat<(i64 (extloadi32 addr:$src)), (LW64 addr:$src)>; 236234353Sdim} 237226584Sdim 238226584Sdim// hi/lo relocs 239239462Sdimdef : MipsPat<(MipsHi tglobaladdr:$in), (LUi64 tglobaladdr:$in)>; 240239462Sdimdef : MipsPat<(MipsHi tblockaddress:$in), (LUi64 tblockaddress:$in)>; 241239462Sdimdef : MipsPat<(MipsHi tjumptable:$in), (LUi64 tjumptable:$in)>; 242239462Sdimdef : MipsPat<(MipsHi tconstpool:$in), (LUi64 tconstpool:$in)>; 243239462Sdimdef : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi64 tglobaltlsaddr:$in)>; 244244628Sdimdef : MipsPat<(MipsHi texternalsym:$in), (LUi64 texternalsym:$in)>; 245226584Sdim 246239462Sdimdef : MipsPat<(MipsLo tglobaladdr:$in), (DADDiu ZERO_64, tglobaladdr:$in)>; 247239462Sdimdef : MipsPat<(MipsLo tblockaddress:$in), (DADDiu ZERO_64, tblockaddress:$in)>; 248239462Sdimdef : MipsPat<(MipsLo tjumptable:$in), (DADDiu ZERO_64, tjumptable:$in)>; 249239462Sdimdef : MipsPat<(MipsLo tconstpool:$in), (DADDiu ZERO_64, tconstpool:$in)>; 250239462Sdimdef : MipsPat<(MipsLo tglobaltlsaddr:$in), 251239462Sdim (DADDiu ZERO_64, tglobaltlsaddr:$in)>; 252244628Sdimdef : MipsPat<(MipsLo texternalsym:$in), (DADDiu ZERO_64, texternalsym:$in)>; 253234353Sdim 254263508Sdimdef : MipsPat<(add GPR64:$hi, (MipsLo tglobaladdr:$lo)), 255263508Sdim (DADDiu GPR64:$hi, tglobaladdr:$lo)>; 256263508Sdimdef : MipsPat<(add GPR64:$hi, (MipsLo tblockaddress:$lo)), 257263508Sdim (DADDiu GPR64:$hi, tblockaddress:$lo)>; 258263508Sdimdef : MipsPat<(add GPR64:$hi, (MipsLo tjumptable:$lo)), 259263508Sdim (DADDiu GPR64:$hi, tjumptable:$lo)>; 260263508Sdimdef : MipsPat<(add GPR64:$hi, (MipsLo tconstpool:$lo)), 261263508Sdim (DADDiu GPR64:$hi, tconstpool:$lo)>; 262263508Sdimdef : MipsPat<(add GPR64:$hi, (MipsLo tglobaltlsaddr:$lo)), 263263508Sdim (DADDiu GPR64:$hi, tglobaltlsaddr:$lo)>; 264234353Sdim 265263508Sdimdef : WrapperPat<tglobaladdr, DADDiu, GPR64>; 266263508Sdimdef : WrapperPat<tconstpool, DADDiu, GPR64>; 267263508Sdimdef : WrapperPat<texternalsym, DADDiu, GPR64>; 268263508Sdimdef : WrapperPat<tblockaddress, DADDiu, GPR64>; 269263508Sdimdef : WrapperPat<tjumptable, DADDiu, GPR64>; 270263508Sdimdef : WrapperPat<tglobaltlsaddr, DADDiu, GPR64>; 271234353Sdim 272263508Sdimdefm : BrcondPats<GPR64, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64, 273226584Sdim ZERO_64>; 274226584Sdim 275263508Sdimdef : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst), 276263508Sdim (BLEZ64 i64:$lhs, bb:$dst)>; 277263508Sdimdef : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst), 278263508Sdim (BGEZ64 i64:$lhs, bb:$dst)>; 279263508Sdim 280226584Sdim// setcc patterns 281263508Sdimdefm : SeteqPats<GPR64, SLTiu64, XOR64, SLTu64, ZERO_64>; 282263508Sdimdefm : SetlePats<GPR64, SLT64, SLTu64>; 283263508Sdimdefm : SetgtPats<GPR64, SLT64, SLTu64>; 284263508Sdimdefm : SetgePats<GPR64, SLT64, SLTu64>; 285263508Sdimdefm : SetgeImmPats<GPR64, SLTi64, SLTiu64>; 286234353Sdim 287234353Sdim// truncate 288263508Sdimdef : MipsPat<(i32 (trunc GPR64:$src)), 289263508Sdim (SLL (EXTRACT_SUBREG GPR64:$src, sub_32), 0)>, 290263508Sdim Requires<[HasStdEnc]>; 291234353Sdim 292234353Sdim// 32-to-64-bit extension 293263508Sdimdef : MipsPat<(i64 (anyext GPR32:$src)), (SLL64_32 GPR32:$src)>; 294263508Sdimdef : MipsPat<(i64 (zext GPR32:$src)), (DSRL (DSLL64_32 GPR32:$src), 32)>; 295263508Sdimdef : MipsPat<(i64 (sext GPR32:$src)), (SLL64_32 GPR32:$src)>; 296234353Sdim 297234353Sdim// Sign extend in register 298263508Sdimdef : MipsPat<(i64 (sext_inreg GPR64:$src, i32)), 299263508Sdim (SLL64_64 GPR64:$src)>; 300234353Sdim 301239462Sdim// bswap MipsPattern 302263508Sdimdef : MipsPat<(bswap GPR64:$rt), (DSHD (DSBH GPR64:$rt))>; 303243830Sdim 304243830Sdim//===----------------------------------------------------------------------===// 305243830Sdim// Instruction aliases 306243830Sdim//===----------------------------------------------------------------------===// 307249423Sdimdef : InstAlias<"move $dst, $src", 308263508Sdim (DADDu GPR64Opnd:$dst, GPR64Opnd:$src, ZERO_64), 1>, 309249423Sdim Requires<[HasMips64]>; 310249423Sdimdef : InstAlias<"daddu $rs, $rt, $imm", 311263508Sdim (DADDiu GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 312263508Sdim 0>; 313249423Sdimdef : InstAlias<"dadd $rs, $rt, $imm", 314263508Sdim (DADDi GPR64Opnd:$rs, GPR64Opnd:$rt, simm16_64:$imm), 315263508Sdim 0>; 316263508Sdim 317249423Sdim/// Move between CPU and coprocessor registers 318263508Sdimlet DecoderNamespace = "Mips64", Predicates = [HasMips64] in { 319263508Sdimdef DMFC0 : MFC3OP<"dmfc0", GPR64Opnd>, MFC3OP_FM<0x10, 1>; 320263508Sdimdef DMTC0 : MFC3OP<"dmtc0", GPR64Opnd>, MFC3OP_FM<0x10, 5>; 321263508Sdimdef DMFC2 : MFC3OP<"dmfc2", GPR64Opnd>, MFC3OP_FM<0x12, 1>; 322263508Sdimdef DMTC2 : MFC3OP<"dmtc2", GPR64Opnd>, MFC3OP_FM<0x12, 5>; 323243830Sdim} 324249423Sdim 325243830Sdim// Two operand (implicit 0 selector) versions: 326263508Sdimdef : InstAlias<"dmfc0 $rt, $rd", (DMFC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 327263508Sdimdef : InstAlias<"dmtc0 $rt, $rd", (DMTC0 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 328263508Sdimdef : InstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 329263508Sdimdef : InstAlias<"dmtc2 $rt, $rd", (DMTC2 GPR64Opnd:$rt, GPR64Opnd:$rd, 0), 0>; 330243830Sdim 331