HexagonInstrInfo.cpp revision 249423 
1254721Semaste//===-- HexagonInstrInfo.cpp - Hexagon Instruction Information ------------===//
2254721Semaste//
3254721Semaste//                     The LLVM Compiler Infrastructure
4254721Semaste//
5254721Semaste// This file is distributed under the University of Illinois Open Source
6254721Semaste// License. See LICENSE.TXT for details.
7254721Semaste//
8254721Semaste//===----------------------------------------------------------------------===//
9254721Semaste//
10254721Semaste// This file contains the Hexagon implementation of the TargetInstrInfo class.
11254721Semaste//
12254721Semaste//===----------------------------------------------------------------------===//
13254721Semaste
14254721Semaste#include "HexagonInstrInfo.h"
15254721Semaste#include "Hexagon.h"
16254721Semaste#include "HexagonRegisterInfo.h"
17254721Semaste#include "HexagonSubtarget.h"
18254721Semaste#include "llvm/ADT/STLExtras.h"
19#include "llvm/ADT/SmallVector.h"
20#include "llvm/CodeGen/DFAPacketizer.h"
21#include "llvm/CodeGen/MachineFrameInfo.h"
22#include "llvm/CodeGen/MachineInstrBuilder.h"
23#include "llvm/CodeGen/MachineMemOperand.h"
24#include "llvm/CodeGen/MachineRegisterInfo.h"
25#include "llvm/CodeGen/PseudoSourceValue.h"
26#include "llvm/Support/MathExtras.h"
27#define GET_INSTRINFO_CTOR
28#define GET_INSTRMAP_INFO
29#include "HexagonGenInstrInfo.inc"
30#include "HexagonGenDFAPacketizer.inc"
31
32using namespace llvm;
33
34///
35/// Constants for Hexagon instructions.
36///
37const int Hexagon_MEMW_OFFSET_MAX = 4095;
38const int Hexagon_MEMW_OFFSET_MIN = -4096;
39const int Hexagon_MEMD_OFFSET_MAX = 8191;
40const int Hexagon_MEMD_OFFSET_MIN = -8192;
41const int Hexagon_MEMH_OFFSET_MAX = 2047;
42const int Hexagon_MEMH_OFFSET_MIN = -2048;
43const int Hexagon_MEMB_OFFSET_MAX = 1023;
44const int Hexagon_MEMB_OFFSET_MIN = -1024;
45const int Hexagon_ADDI_OFFSET_MAX = 32767;
46const int Hexagon_ADDI_OFFSET_MIN = -32768;
47const int Hexagon_MEMD_AUTOINC_MAX = 56;
48const int Hexagon_MEMD_AUTOINC_MIN = -64;
49const int Hexagon_MEMW_AUTOINC_MAX = 28;
50const int Hexagon_MEMW_AUTOINC_MIN = -32;
51const int Hexagon_MEMH_AUTOINC_MAX = 14;
52const int Hexagon_MEMH_AUTOINC_MIN = -16;
53const int Hexagon_MEMB_AUTOINC_MAX = 7;
54const int Hexagon_MEMB_AUTOINC_MIN = -8;
55
56
57HexagonInstrInfo::HexagonInstrInfo(HexagonSubtarget &ST)
58  : HexagonGenInstrInfo(Hexagon::ADJCALLSTACKDOWN, Hexagon::ADJCALLSTACKUP),
59    RI(ST, *this), Subtarget(ST) {
60}
61
62
63/// isLoadFromStackSlot - If the specified machine instruction is a direct
64/// load from a stack slot, return the virtual or physical register number of
65/// the destination along with the FrameIndex of the loaded stack slot.  If
66/// not, return 0.  This predicate must return 0 if the instruction has
67/// any side effects other than loading from the stack slot.
68unsigned HexagonInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
69                                             int &FrameIndex) const {
70
71
72  switch (MI->getOpcode()) {
73  default: break;
74  case Hexagon::LDriw:
75  case Hexagon::LDrid:
76  case Hexagon::LDrih:
77  case Hexagon::LDrib:
78  case Hexagon::LDriub:
79    if (MI->getOperand(2).isFI() &&
80        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
81      FrameIndex = MI->getOperand(2).getIndex();
82      return MI->getOperand(0).getReg();
83    }
84    break;
85  }
86  return 0;
87}
88
89
90/// isStoreToStackSlot - If the specified machine instruction is a direct
91/// store to a stack slot, return the virtual or physical register number of
92/// the source reg along with the FrameIndex of the loaded stack slot.  If
93/// not, return 0.  This predicate must return 0 if the instruction has
94/// any side effects other than storing to the stack slot.
95unsigned HexagonInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96                                            int &FrameIndex) const {
97  switch (MI->getOpcode()) {
98  default: break;
99  case Hexagon::STriw:
100  case Hexagon::STrid:
101  case Hexagon::STrih:
102  case Hexagon::STrib:
103    if (MI->getOperand(2).isFI() &&
104        MI->getOperand(1).isImm() && (MI->getOperand(1).getImm() == 0)) {
105      FrameIndex = MI->getOperand(0).getIndex();
106      return MI->getOperand(2).getReg();
107    }
108    break;
109  }
110  return 0;
111}
112
113
114unsigned
115HexagonInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
116                             MachineBasicBlock *FBB,
117                             const SmallVectorImpl<MachineOperand> &Cond,
118                             DebugLoc DL) const{
119
120    int BOpc   = Hexagon::JMP;
121    int BccOpc = Hexagon::JMP_c;
122
123    assert(TBB && "InsertBranch must not be told to insert a fallthrough");
124
125    int regPos = 0;
126    // Check if ReverseBranchCondition has asked to reverse this branch
127    // If we want to reverse the branch an odd number of times, we want
128    // JMP_cNot.
129    if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
130      BccOpc = Hexagon::JMP_cNot;
131      regPos = 1;
132    }
133
134    if (FBB == 0) {
135      if (Cond.empty()) {
136        // Due to a bug in TailMerging/CFG Optimization, we need to add a
137        // special case handling of a predicated jump followed by an
138        // unconditional jump. If not, Tail Merging and CFG Optimization go
139        // into an infinite loop.
140        MachineBasicBlock *NewTBB, *NewFBB;
141        SmallVector<MachineOperand, 4> Cond;
142        MachineInstr *Term = MBB.getFirstTerminator();
143        if (isPredicated(Term) && !AnalyzeBranch(MBB, NewTBB, NewFBB, Cond,
144                                                 false)) {
145          MachineBasicBlock *NextBB =
146            llvm::next(MachineFunction::iterator(&MBB));
147          if (NewTBB == NextBB) {
148            ReverseBranchCondition(Cond);
149            RemoveBranch(MBB);
150            return InsertBranch(MBB, TBB, 0, Cond, DL);
151          }
152        }
153        BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
154      } else {
155        BuildMI(&MBB, DL,
156                get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
157      }
158      return 1;
159    }
160
161    BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[regPos].getReg()).addMBB(TBB);
162    BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
163
164    return 2;
165}
166
167
168bool HexagonInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
169                                     MachineBasicBlock *&TBB,
170                                 MachineBasicBlock *&FBB,
171                                 SmallVectorImpl<MachineOperand> &Cond,
172                                 bool AllowModify) const {
173  TBB = NULL;
174  FBB = NULL;
175
176  // If the block has no terminators, it just falls into the block after it.
177  MachineBasicBlock::iterator I = MBB.end();
178  if (I == MBB.begin())
179    return false;
180
181  // A basic block may looks like this:
182  //
183  //  [   insn
184  //     EH_LABEL
185  //      insn
186  //      insn
187  //      insn
188  //     EH_LABEL
189  //      insn     ]
190  //
191  // It has two succs but does not have a terminator
192  // Don't know how to handle it.
193  do {
194    --I;
195    if (I->isEHLabel())
196      return true;
197  } while (I != MBB.begin());
198
199  I = MBB.end();
200  --I;
201
202  while (I->isDebugValue()) {
203    if (I == MBB.begin())
204      return false;
205    --I;
206  }
207  if (!isUnpredicatedTerminator(I))
208    return false;
209
210  // Get the last instruction in the block.
211  MachineInstr *LastInst = I;
212
213  // If there is only one terminator instruction, process it.
214  if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
215    if (LastInst->getOpcode() == Hexagon::JMP) {
216      TBB = LastInst->getOperand(0).getMBB();
217      return false;
218    }
219    if (LastInst->getOpcode() == Hexagon::JMP_c) {
220      // Block ends with fall-through true condbranch.
221      TBB = LastInst->getOperand(1).getMBB();
222      Cond.push_back(LastInst->getOperand(0));
223      return false;
224    }
225    if (LastInst->getOpcode() == Hexagon::JMP_cNot) {
226      // Block ends with fall-through false condbranch.
227      TBB = LastInst->getOperand(1).getMBB();
228      Cond.push_back(MachineOperand::CreateImm(0));
229      Cond.push_back(LastInst->getOperand(0));
230      return false;
231    }
232    // Otherwise, don't know what this is.
233    return true;
234  }
235
236  // Get the instruction before it if it's a terminator.
237  MachineInstr *SecondLastInst = I;
238
239  // If there are three terminators, we don't know what sort of block this is.
240  if (SecondLastInst && I != MBB.begin() &&
241      isUnpredicatedTerminator(--I))
242    return true;
243
244  // If the block ends with Hexagon::BRCOND and Hexagon:JMP, handle it.
245  if (((SecondLastInst->getOpcode() == Hexagon::BRCOND) ||
246      (SecondLastInst->getOpcode() == Hexagon::JMP_c)) &&
247      LastInst->getOpcode() == Hexagon::JMP) {
248    TBB =  SecondLastInst->getOperand(1).getMBB();
249    Cond.push_back(SecondLastInst->getOperand(0));
250    FBB = LastInst->getOperand(0).getMBB();
251    return false;
252  }
253
254  // If the block ends with Hexagon::JMP_cNot and Hexagon:JMP, handle it.
255  if ((SecondLastInst->getOpcode() == Hexagon::JMP_cNot) &&
256      LastInst->getOpcode() == Hexagon::JMP) {
257    TBB =  SecondLastInst->getOperand(1).getMBB();
258    Cond.push_back(MachineOperand::CreateImm(0));
259    Cond.push_back(SecondLastInst->getOperand(0));
260    FBB = LastInst->getOperand(0).getMBB();
261    return false;
262  }
263
264  // If the block ends with two Hexagon:JMPs, handle it.  The second one is not
265  // executed, so remove it.
266  if (SecondLastInst->getOpcode() == Hexagon::JMP &&
267      LastInst->getOpcode() == Hexagon::JMP) {
268    TBB = SecondLastInst->getOperand(0).getMBB();
269    I = LastInst;
270    if (AllowModify)
271      I->eraseFromParent();
272    return false;
273  }
274
275  // Otherwise, can't handle this.
276  return true;
277}
278
279
280unsigned HexagonInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
281  int BOpc   = Hexagon::JMP;
282  int BccOpc = Hexagon::JMP_c;
283  int BccOpcNot = Hexagon::JMP_cNot;
284
285  MachineBasicBlock::iterator I = MBB.end();
286  if (I == MBB.begin()) return 0;
287  --I;
288  if (I->getOpcode() != BOpc && I->getOpcode() != BccOpc &&
289      I->getOpcode() != BccOpcNot)
290    return 0;
291
292  // Remove the branch.
293  I->eraseFromParent();
294
295  I = MBB.end();
296
297  if (I == MBB.begin()) return 1;
298  --I;
299  if (I->getOpcode() != BccOpc && I->getOpcode() != BccOpcNot)
300    return 1;
301
302  // Remove the branch.
303  I->eraseFromParent();
304  return 2;
305}
306
307
308/// \brief For a comparison instruction, return the source registers in
309/// \p SrcReg and \p SrcReg2 if having two register operands, and the value it
310/// compares against in CmpValue. Return true if the comparison instruction
311/// can be analyzed.
312bool HexagonInstrInfo::analyzeCompare(const MachineInstr *MI,
313                                      unsigned &SrcReg, unsigned &SrcReg2,
314                                      int &Mask, int &Value) const {
315  unsigned Opc = MI->getOpcode();
316
317  // Set mask and the first source register.
318  switch (Opc) {
319    case Hexagon::CMPEHexagon4rr:
320    case Hexagon::CMPEQri:
321    case Hexagon::CMPEQrr:
322    case Hexagon::CMPGT64rr:
323    case Hexagon::CMPGTU64rr:
324    case Hexagon::CMPGTUri:
325    case Hexagon::CMPGTUrr:
326    case Hexagon::CMPGTri:
327    case Hexagon::CMPGTrr:
328    case Hexagon::CMPLTUrr:
329    case Hexagon::CMPLTrr:
330      SrcReg = MI->getOperand(1).getReg();
331      Mask = ~0;
332      break;
333    case Hexagon::CMPbEQri_V4:
334    case Hexagon::CMPbEQrr_sbsb_V4:
335    case Hexagon::CMPbEQrr_ubub_V4:
336    case Hexagon::CMPbGTUri_V4:
337    case Hexagon::CMPbGTUrr_V4:
338    case Hexagon::CMPbGTrr_V4:
339      SrcReg = MI->getOperand(1).getReg();
340      Mask = 0xFF;
341      break;
342    case Hexagon::CMPhEQri_V4:
343    case Hexagon::CMPhEQrr_shl_V4:
344    case Hexagon::CMPhEQrr_xor_V4:
345    case Hexagon::CMPhGTUri_V4:
346    case Hexagon::CMPhGTUrr_V4:
347    case Hexagon::CMPhGTrr_shl_V4:
348      SrcReg = MI->getOperand(1).getReg();
349      Mask = 0xFFFF;
350      break;
351  }
352
353  // Set the value/second source register.
354  switch (Opc) {
355    case Hexagon::CMPEHexagon4rr:
356    case Hexagon::CMPEQrr:
357    case Hexagon::CMPGT64rr:
358    case Hexagon::CMPGTU64rr:
359    case Hexagon::CMPGTUrr:
360    case Hexagon::CMPGTrr:
361    case Hexagon::CMPbEQrr_sbsb_V4:
362    case Hexagon::CMPbEQrr_ubub_V4:
363    case Hexagon::CMPbGTUrr_V4:
364    case Hexagon::CMPbGTrr_V4:
365    case Hexagon::CMPhEQrr_shl_V4:
366    case Hexagon::CMPhEQrr_xor_V4:
367    case Hexagon::CMPhGTUrr_V4:
368    case Hexagon::CMPhGTrr_shl_V4:
369    case Hexagon::CMPLTUrr:
370    case Hexagon::CMPLTrr:
371      SrcReg2 = MI->getOperand(2).getReg();
372      return true;
373
374    case Hexagon::CMPEQri:
375    case Hexagon::CMPGTUri:
376    case Hexagon::CMPGTri:
377    case Hexagon::CMPbEQri_V4:
378    case Hexagon::CMPbGTUri_V4:
379    case Hexagon::CMPhEQri_V4:
380    case Hexagon::CMPhGTUri_V4:
381      SrcReg2 = 0;
382      Value = MI->getOperand(2).getImm();
383      return true;
384  }
385
386  return false;
387}
388
389
390void HexagonInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
391                                 MachineBasicBlock::iterator I, DebugLoc DL,
392                                 unsigned DestReg, unsigned SrcReg,
393                                 bool KillSrc) const {
394  if (Hexagon::IntRegsRegClass.contains(SrcReg, DestReg)) {
395    BuildMI(MBB, I, DL, get(Hexagon::TFR), DestReg).addReg(SrcReg);
396    return;
397  }
398  if (Hexagon::DoubleRegsRegClass.contains(SrcReg, DestReg)) {
399    BuildMI(MBB, I, DL, get(Hexagon::TFR64), DestReg).addReg(SrcReg);
400    return;
401  }
402  if (Hexagon::PredRegsRegClass.contains(SrcReg, DestReg)) {
403    // Map Pd = Ps to Pd = or(Ps, Ps).
404    BuildMI(MBB, I, DL, get(Hexagon::OR_pp),
405            DestReg).addReg(SrcReg).addReg(SrcReg);
406    return;
407  }
408  if (Hexagon::DoubleRegsRegClass.contains(DestReg) &&
409      Hexagon::IntRegsRegClass.contains(SrcReg)) {
410    // We can have an overlap between single and double reg: r1:0 = r0.
411    if(SrcReg == RI.getSubReg(DestReg, Hexagon::subreg_loreg)) {
412        // r1:0 = r0
413        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
414                Hexagon::subreg_hireg))).addImm(0);
415    } else {
416        // r1:0 = r1 or no overlap.
417        BuildMI(MBB, I, DL, get(Hexagon::TFR), (RI.getSubReg(DestReg,
418                Hexagon::subreg_loreg))).addReg(SrcReg);
419        BuildMI(MBB, I, DL, get(Hexagon::TFRI), (RI.getSubReg(DestReg,
420                Hexagon::subreg_hireg))).addImm(0);
421    }
422    return;
423  }
424  if (Hexagon::CRRegsRegClass.contains(DestReg) &&
425      Hexagon::IntRegsRegClass.contains(SrcReg)) {
426    BuildMI(MBB, I, DL, get(Hexagon::TFCR), DestReg).addReg(SrcReg);
427    return;
428  }
429  if (Hexagon::PredRegsRegClass.contains(SrcReg) &&
430      Hexagon::IntRegsRegClass.contains(DestReg)) {
431    BuildMI(MBB, I, DL, get(Hexagon::TFR_RsPd), DestReg).
432      addReg(SrcReg, getKillRegState(KillSrc));
433    return;
434  }
435  if (Hexagon::IntRegsRegClass.contains(SrcReg) &&
436      Hexagon::PredRegsRegClass.contains(DestReg)) {
437    BuildMI(MBB, I, DL, get(Hexagon::TFR_PdRs), DestReg).
438      addReg(SrcReg, getKillRegState(KillSrc));
439    return;
440  }
441
442  llvm_unreachable("Unimplemented");
443}
444
445
446void HexagonInstrInfo::
447storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
448                    unsigned SrcReg, bool isKill, int FI,
449                    const TargetRegisterClass *RC,
450                    const TargetRegisterInfo *TRI) const {
451
452  DebugLoc DL = MBB.findDebugLoc(I);
453  MachineFunction &MF = *MBB.getParent();
454  MachineFrameInfo &MFI = *MF.getFrameInfo();
455  unsigned Align = MFI.getObjectAlignment(FI);
456
457  MachineMemOperand *MMO =
458      MF.getMachineMemOperand(
459                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
460                      MachineMemOperand::MOStore,
461                      MFI.getObjectSize(FI),
462                      Align);
463
464  if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) {
465    BuildMI(MBB, I, DL, get(Hexagon::STriw))
466          .addFrameIndex(FI).addImm(0)
467          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
468  } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) {
469    BuildMI(MBB, I, DL, get(Hexagon::STrid))
470          .addFrameIndex(FI).addImm(0)
471          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
472  } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) {
473    BuildMI(MBB, I, DL, get(Hexagon::STriw_pred))
474          .addFrameIndex(FI).addImm(0)
475          .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
476  } else {
477    llvm_unreachable("Unimplemented");
478  }
479}
480
481
482void HexagonInstrInfo::storeRegToAddr(
483                                 MachineFunction &MF, unsigned SrcReg,
484                                 bool isKill,
485                                 SmallVectorImpl<MachineOperand> &Addr,
486                                 const TargetRegisterClass *RC,
487                                 SmallVectorImpl<MachineInstr*> &NewMIs) const
488{
489  llvm_unreachable("Unimplemented");
490}
491
492
493void HexagonInstrInfo::
494loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
495                     unsigned DestReg, int FI,
496                     const TargetRegisterClass *RC,
497                     const TargetRegisterInfo *TRI) const {
498  DebugLoc DL = MBB.findDebugLoc(I);
499  MachineFunction &MF = *MBB.getParent();
500  MachineFrameInfo &MFI = *MF.getFrameInfo();
501  unsigned Align = MFI.getObjectAlignment(FI);
502
503  MachineMemOperand *MMO =
504      MF.getMachineMemOperand(
505                      MachinePointerInfo(PseudoSourceValue::getFixedStack(FI)),
506                      MachineMemOperand::MOLoad,
507                      MFI.getObjectSize(FI),
508                      Align);
509  if (RC == &Hexagon::IntRegsRegClass) {
510    BuildMI(MBB, I, DL, get(Hexagon::LDriw), DestReg)
511          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
512  } else if (RC == &Hexagon::DoubleRegsRegClass) {
513    BuildMI(MBB, I, DL, get(Hexagon::LDrid), DestReg)
514          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
515  } else if (RC == &Hexagon::PredRegsRegClass) {
516    BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
517          .addFrameIndex(FI).addImm(0).addMemOperand(MMO);
518  } else {
519    llvm_unreachable("Can't store this register to stack slot");
520  }
521}
522
523
524void HexagonInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
525                                        SmallVectorImpl<MachineOperand> &Addr,
526                                        const TargetRegisterClass *RC,
527                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
528  llvm_unreachable("Unimplemented");
529}
530
531
532MachineInstr *HexagonInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
533                                                    MachineInstr* MI,
534                                          const SmallVectorImpl<unsigned> &Ops,
535                                                    int FI) const {
536  // Hexagon_TODO: Implement.
537  return(0);
538}
539
540MachineInstr*
541HexagonInstrInfo::emitFrameIndexDebugValue(MachineFunction &MF,
542                                           int FrameIx, uint64_t Offset,
543                                           const MDNode *MDPtr,
544                                           DebugLoc DL) const {
545  MachineInstrBuilder MIB = BuildMI(MF, DL, get(Hexagon::DBG_VALUE))
546    .addImm(0).addImm(Offset).addMetadata(MDPtr);
547  return &*MIB;
548}
549
550unsigned HexagonInstrInfo::createVR(MachineFunction* MF, MVT VT) const {
551
552  MachineRegisterInfo &RegInfo = MF->getRegInfo();
553  const TargetRegisterClass *TRC;
554  if (VT == MVT::i1) {
555    TRC = &Hexagon::PredRegsRegClass;
556  } else if (VT == MVT::i32 || VT == MVT::f32) {
557    TRC = &Hexagon::IntRegsRegClass;
558  } else if (VT == MVT::i64 || VT == MVT::f64) {
559    TRC = &Hexagon::DoubleRegsRegClass;
560  } else {
561    llvm_unreachable("Cannot handle this register class");
562  }
563
564  unsigned NewReg = RegInfo.createVirtualRegister(TRC);
565  return NewReg;
566}
567
568bool HexagonInstrInfo::isExtendable(const MachineInstr *MI) const {
569  // Constant extenders are allowed only for V4 and above.
570  if (!Subtarget.hasV4TOps())
571    return false;
572
573  const MCInstrDesc &MID = MI->getDesc();
574  const uint64_t F = MID.TSFlags;
575  if ((F >> HexagonII::ExtendablePos) & HexagonII::ExtendableMask)
576    return true;
577
578  // TODO: This is largely obsolete now. Will need to be removed
579  // in consecutive patches.
580  switch(MI->getOpcode()) {
581    // TFR_FI Remains a special case.
582    case Hexagon::TFR_FI:
583      return true;
584    default:
585      return false;
586  }
587  return  false;
588}
589
590// This returns true in two cases:
591// - The OP code itself indicates that this is an extended instruction.
592// - One of MOs has been marked with HMOTF_ConstExtended flag.
593bool HexagonInstrInfo::isExtended(const MachineInstr *MI) const {
594  // First check if this is permanently extended op code.
595  const uint64_t F = MI->getDesc().TSFlags;
596  if ((F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask)
597    return true;
598  // Use MO operand flags to determine if one of MI's operands
599  // has HMOTF_ConstExtended flag set.
600  for (MachineInstr::const_mop_iterator I = MI->operands_begin(),
601       E = MI->operands_end(); I != E; ++I) {
602    if (I->getTargetFlags() && HexagonII::HMOTF_ConstExtended)
603      return true;
604  }
605  return  false;
606}
607
608bool HexagonInstrInfo::isNewValueJump(const MachineInstr *MI) const {
609  switch (MI->getOpcode()) {
610    default: return false;
611    // JMP_EQri
612    case Hexagon::JMP_EQriPt_nv_V4:
613    case Hexagon::JMP_EQriPnt_nv_V4:
614    case Hexagon::JMP_EQriNotPt_nv_V4:
615    case Hexagon::JMP_EQriNotPnt_nv_V4:
616    case Hexagon::JMP_EQriPt_ie_nv_V4:
617    case Hexagon::JMP_EQriPnt_ie_nv_V4:
618    case Hexagon::JMP_EQriNotPt_ie_nv_V4:
619    case Hexagon::JMP_EQriNotPnt_ie_nv_V4:
620
621    // JMP_EQri - with -1
622    case Hexagon::JMP_EQriPtneg_nv_V4:
623    case Hexagon::JMP_EQriPntneg_nv_V4:
624    case Hexagon::JMP_EQriNotPtneg_nv_V4:
625    case Hexagon::JMP_EQriNotPntneg_nv_V4:
626    case Hexagon::JMP_EQriPtneg_ie_nv_V4:
627    case Hexagon::JMP_EQriPntneg_ie_nv_V4:
628    case Hexagon::JMP_EQriNotPtneg_ie_nv_V4:
629    case Hexagon::JMP_EQriNotPntneg_ie_nv_V4:
630
631    // JMP_EQrr
632    case Hexagon::JMP_EQrrPt_nv_V4:
633    case Hexagon::JMP_EQrrPnt_nv_V4:
634    case Hexagon::JMP_EQrrNotPt_nv_V4:
635    case Hexagon::JMP_EQrrNotPnt_nv_V4:
636    case Hexagon::JMP_EQrrPt_ie_nv_V4:
637    case Hexagon::JMP_EQrrPnt_ie_nv_V4:
638    case Hexagon::JMP_EQrrNotPt_ie_nv_V4:
639    case Hexagon::JMP_EQrrNotPnt_ie_nv_V4:
640
641    // JMP_GTri
642    case Hexagon::JMP_GTriPt_nv_V4:
643    case Hexagon::JMP_GTriPnt_nv_V4:
644    case Hexagon::JMP_GTriNotPt_nv_V4:
645    case Hexagon::JMP_GTriNotPnt_nv_V4:
646    case Hexagon::JMP_GTriPt_ie_nv_V4:
647    case Hexagon::JMP_GTriPnt_ie_nv_V4:
648    case Hexagon::JMP_GTriNotPt_ie_nv_V4:
649    case Hexagon::JMP_GTriNotPnt_ie_nv_V4:
650
651    // JMP_GTri - with -1
652    case Hexagon::JMP_GTriPtneg_nv_V4:
653    case Hexagon::JMP_GTriPntneg_nv_V4:
654    case Hexagon::JMP_GTriNotPtneg_nv_V4:
655    case Hexagon::JMP_GTriNotPntneg_nv_V4:
656    case Hexagon::JMP_GTriPtneg_ie_nv_V4:
657    case Hexagon::JMP_GTriPntneg_ie_nv_V4:
658    case Hexagon::JMP_GTriNotPtneg_ie_nv_V4:
659    case Hexagon::JMP_GTriNotPntneg_ie_nv_V4:
660
661    // JMP_GTrr
662    case Hexagon::JMP_GTrrPt_nv_V4:
663    case Hexagon::JMP_GTrrPnt_nv_V4:
664    case Hexagon::JMP_GTrrNotPt_nv_V4:
665    case Hexagon::JMP_GTrrNotPnt_nv_V4:
666    case Hexagon::JMP_GTrrPt_ie_nv_V4:
667    case Hexagon::JMP_GTrrPnt_ie_nv_V4:
668    case Hexagon::JMP_GTrrNotPt_ie_nv_V4:
669    case Hexagon::JMP_GTrrNotPnt_ie_nv_V4:
670
671    // JMP_GTrrdn
672    case Hexagon::JMP_GTrrdnPt_nv_V4:
673    case Hexagon::JMP_GTrrdnPnt_nv_V4:
674    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
675    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
676    case Hexagon::JMP_GTrrdnPt_ie_nv_V4:
677    case Hexagon::JMP_GTrrdnPnt_ie_nv_V4:
678    case Hexagon::JMP_GTrrdnNotPt_ie_nv_V4:
679    case Hexagon::JMP_GTrrdnNotPnt_ie_nv_V4:
680
681    // JMP_GTUri
682    case Hexagon::JMP_GTUriPt_nv_V4:
683    case Hexagon::JMP_GTUriPnt_nv_V4:
684    case Hexagon::JMP_GTUriNotPt_nv_V4:
685    case Hexagon::JMP_GTUriNotPnt_nv_V4:
686    case Hexagon::JMP_GTUriPt_ie_nv_V4:
687    case Hexagon::JMP_GTUriPnt_ie_nv_V4:
688    case Hexagon::JMP_GTUriNotPt_ie_nv_V4:
689    case Hexagon::JMP_GTUriNotPnt_ie_nv_V4:
690
691    // JMP_GTUrr
692    case Hexagon::JMP_GTUrrPt_nv_V4:
693    case Hexagon::JMP_GTUrrPnt_nv_V4:
694    case Hexagon::JMP_GTUrrNotPt_nv_V4:
695    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
696    case Hexagon::JMP_GTUrrPt_ie_nv_V4:
697    case Hexagon::JMP_GTUrrPnt_ie_nv_V4:
698    case Hexagon::JMP_GTUrrNotPt_ie_nv_V4:
699    case Hexagon::JMP_GTUrrNotPnt_ie_nv_V4:
700
701    // JMP_GTUrrdn
702    case Hexagon::JMP_GTUrrdnPt_nv_V4:
703    case Hexagon::JMP_GTUrrdnPnt_nv_V4:
704    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
705    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
706    case Hexagon::JMP_GTUrrdnPt_ie_nv_V4:
707    case Hexagon::JMP_GTUrrdnPnt_ie_nv_V4:
708    case Hexagon::JMP_GTUrrdnNotPt_ie_nv_V4:
709    case Hexagon::JMP_GTUrrdnNotPnt_ie_nv_V4:
710      return true;
711  }
712}
713
714bool HexagonInstrInfo::isNewValueStore(const MachineInstr *MI) const {
715  switch (MI->getOpcode()) {
716    default: return false;
717    // Store Byte
718    case Hexagon::STrib_nv_V4:
719    case Hexagon::STrib_indexed_nv_V4:
720    case Hexagon::STrib_indexed_shl_nv_V4:
721    case Hexagon::STrib_shl_nv_V4:
722    case Hexagon::STb_GP_nv_V4:
723    case Hexagon::POST_STbri_nv_V4:
724    case Hexagon::STrib_cPt_nv_V4:
725    case Hexagon::STrib_cdnPt_nv_V4:
726    case Hexagon::STrib_cNotPt_nv_V4:
727    case Hexagon::STrib_cdnNotPt_nv_V4:
728    case Hexagon::STrib_indexed_cPt_nv_V4:
729    case Hexagon::STrib_indexed_cdnPt_nv_V4:
730    case Hexagon::STrib_indexed_cNotPt_nv_V4:
731    case Hexagon::STrib_indexed_cdnNotPt_nv_V4:
732    case Hexagon::STrib_indexed_shl_cPt_nv_V4:
733    case Hexagon::STrib_indexed_shl_cdnPt_nv_V4:
734    case Hexagon::STrib_indexed_shl_cNotPt_nv_V4:
735    case Hexagon::STrib_indexed_shl_cdnNotPt_nv_V4:
736    case Hexagon::POST_STbri_cPt_nv_V4:
737    case Hexagon::POST_STbri_cdnPt_nv_V4:
738    case Hexagon::POST_STbri_cNotPt_nv_V4:
739    case Hexagon::POST_STbri_cdnNotPt_nv_V4:
740    case Hexagon::STb_GP_cPt_nv_V4:
741    case Hexagon::STb_GP_cNotPt_nv_V4:
742    case Hexagon::STb_GP_cdnPt_nv_V4:
743    case Hexagon::STb_GP_cdnNotPt_nv_V4:
744    case Hexagon::STrib_abs_nv_V4:
745    case Hexagon::STrib_abs_cPt_nv_V4:
746    case Hexagon::STrib_abs_cdnPt_nv_V4:
747    case Hexagon::STrib_abs_cNotPt_nv_V4:
748    case Hexagon::STrib_abs_cdnNotPt_nv_V4:
749    case Hexagon::STrib_imm_abs_nv_V4:
750    case Hexagon::STrib_imm_abs_cPt_nv_V4:
751    case Hexagon::STrib_imm_abs_cdnPt_nv_V4:
752    case Hexagon::STrib_imm_abs_cNotPt_nv_V4:
753    case Hexagon::STrib_imm_abs_cdnNotPt_nv_V4:
754
755    // Store Halfword
756    case Hexagon::STrih_nv_V4:
757    case Hexagon::STrih_indexed_nv_V4:
758    case Hexagon::STrih_indexed_shl_nv_V4:
759    case Hexagon::STrih_shl_nv_V4:
760    case Hexagon::STh_GP_nv_V4:
761    case Hexagon::POST_SThri_nv_V4:
762    case Hexagon::STrih_cPt_nv_V4:
763    case Hexagon::STrih_cdnPt_nv_V4:
764    case Hexagon::STrih_cNotPt_nv_V4:
765    case Hexagon::STrih_cdnNotPt_nv_V4:
766    case Hexagon::STrih_indexed_cPt_nv_V4:
767    case Hexagon::STrih_indexed_cdnPt_nv_V4:
768    case Hexagon::STrih_indexed_cNotPt_nv_V4:
769    case Hexagon::STrih_indexed_cdnNotPt_nv_V4:
770    case Hexagon::STrih_indexed_shl_cPt_nv_V4:
771    case Hexagon::STrih_indexed_shl_cdnPt_nv_V4:
772    case Hexagon::STrih_indexed_shl_cNotPt_nv_V4:
773    case Hexagon::STrih_indexed_shl_cdnNotPt_nv_V4:
774    case Hexagon::POST_SThri_cPt_nv_V4:
775    case Hexagon::POST_SThri_cdnPt_nv_V4:
776    case Hexagon::POST_SThri_cNotPt_nv_V4:
777    case Hexagon::POST_SThri_cdnNotPt_nv_V4:
778    case Hexagon::STh_GP_cPt_nv_V4:
779    case Hexagon::STh_GP_cNotPt_nv_V4:
780    case Hexagon::STh_GP_cdnPt_nv_V4:
781    case Hexagon::STh_GP_cdnNotPt_nv_V4:
782    case Hexagon::STrih_abs_nv_V4:
783    case Hexagon::STrih_abs_cPt_nv_V4:
784    case Hexagon::STrih_abs_cdnPt_nv_V4:
785    case Hexagon::STrih_abs_cNotPt_nv_V4:
786    case Hexagon::STrih_abs_cdnNotPt_nv_V4:
787    case Hexagon::STrih_imm_abs_nv_V4:
788    case Hexagon::STrih_imm_abs_cPt_nv_V4:
789    case Hexagon::STrih_imm_abs_cdnPt_nv_V4:
790    case Hexagon::STrih_imm_abs_cNotPt_nv_V4:
791    case Hexagon::STrih_imm_abs_cdnNotPt_nv_V4:
792
793    // Store Word
794    case Hexagon::STriw_nv_V4:
795    case Hexagon::STriw_indexed_nv_V4:
796    case Hexagon::STriw_indexed_shl_nv_V4:
797    case Hexagon::STriw_shl_nv_V4:
798    case Hexagon::STw_GP_nv_V4:
799    case Hexagon::POST_STwri_nv_V4:
800    case Hexagon::STriw_cPt_nv_V4:
801    case Hexagon::STriw_cdnPt_nv_V4:
802    case Hexagon::STriw_cNotPt_nv_V4:
803    case Hexagon::STriw_cdnNotPt_nv_V4:
804    case Hexagon::STriw_indexed_cPt_nv_V4:
805    case Hexagon::STriw_indexed_cdnPt_nv_V4:
806    case Hexagon::STriw_indexed_cNotPt_nv_V4:
807    case Hexagon::STriw_indexed_cdnNotPt_nv_V4:
808    case Hexagon::STriw_indexed_shl_cPt_nv_V4:
809    case Hexagon::STriw_indexed_shl_cdnPt_nv_V4:
810    case Hexagon::STriw_indexed_shl_cNotPt_nv_V4:
811    case Hexagon::STriw_indexed_shl_cdnNotPt_nv_V4:
812    case Hexagon::POST_STwri_cPt_nv_V4:
813    case Hexagon::POST_STwri_cdnPt_nv_V4:
814    case Hexagon::POST_STwri_cNotPt_nv_V4:
815    case Hexagon::POST_STwri_cdnNotPt_nv_V4:
816    case Hexagon::STw_GP_cPt_nv_V4:
817    case Hexagon::STw_GP_cNotPt_nv_V4:
818    case Hexagon::STw_GP_cdnPt_nv_V4:
819    case Hexagon::STw_GP_cdnNotPt_nv_V4:
820    case Hexagon::STriw_abs_nv_V4:
821    case Hexagon::STriw_abs_cPt_nv_V4:
822    case Hexagon::STriw_abs_cdnPt_nv_V4:
823    case Hexagon::STriw_abs_cNotPt_nv_V4:
824    case Hexagon::STriw_abs_cdnNotPt_nv_V4:
825    case Hexagon::STriw_imm_abs_nv_V4:
826    case Hexagon::STriw_imm_abs_cPt_nv_V4:
827    case Hexagon::STriw_imm_abs_cdnPt_nv_V4:
828    case Hexagon::STriw_imm_abs_cNotPt_nv_V4:
829    case Hexagon::STriw_imm_abs_cdnNotPt_nv_V4:
830      return true;
831  }
832}
833
834bool HexagonInstrInfo::isPostIncrement (const MachineInstr* MI) const {
835  switch (MI->getOpcode())
836  {
837    default: return false;
838    // Load Byte
839    case Hexagon::POST_LDrib:
840    case Hexagon::POST_LDrib_cPt:
841    case Hexagon::POST_LDrib_cNotPt:
842    case Hexagon::POST_LDrib_cdnPt_V4:
843    case Hexagon::POST_LDrib_cdnNotPt_V4:
844
845    // Load unsigned byte
846    case Hexagon::POST_LDriub:
847    case Hexagon::POST_LDriub_cPt:
848    case Hexagon::POST_LDriub_cNotPt:
849    case Hexagon::POST_LDriub_cdnPt_V4:
850    case Hexagon::POST_LDriub_cdnNotPt_V4:
851
852    // Load halfword
853    case Hexagon::POST_LDrih:
854    case Hexagon::POST_LDrih_cPt:
855    case Hexagon::POST_LDrih_cNotPt:
856    case Hexagon::POST_LDrih_cdnPt_V4:
857    case Hexagon::POST_LDrih_cdnNotPt_V4:
858
859    // Load unsigned halfword
860    case Hexagon::POST_LDriuh:
861    case Hexagon::POST_LDriuh_cPt:
862    case Hexagon::POST_LDriuh_cNotPt:
863    case Hexagon::POST_LDriuh_cdnPt_V4:
864    case Hexagon::POST_LDriuh_cdnNotPt_V4:
865
866    // Load word
867    case Hexagon::POST_LDriw:
868    case Hexagon::POST_LDriw_cPt:
869    case Hexagon::POST_LDriw_cNotPt:
870    case Hexagon::POST_LDriw_cdnPt_V4:
871    case Hexagon::POST_LDriw_cdnNotPt_V4:
872
873    // Load double word
874    case Hexagon::POST_LDrid:
875    case Hexagon::POST_LDrid_cPt:
876    case Hexagon::POST_LDrid_cNotPt:
877    case Hexagon::POST_LDrid_cdnPt_V4:
878    case Hexagon::POST_LDrid_cdnNotPt_V4:
879
880    // Store byte
881    case Hexagon::POST_STbri:
882    case Hexagon::POST_STbri_cPt:
883    case Hexagon::POST_STbri_cNotPt:
884    case Hexagon::POST_STbri_cdnPt_V4:
885    case Hexagon::POST_STbri_cdnNotPt_V4:
886
887    // Store halfword
888    case Hexagon::POST_SThri:
889    case Hexagon::POST_SThri_cPt:
890    case Hexagon::POST_SThri_cNotPt:
891    case Hexagon::POST_SThri_cdnPt_V4:
892    case Hexagon::POST_SThri_cdnNotPt_V4:
893
894    // Store word
895    case Hexagon::POST_STwri:
896    case Hexagon::POST_STwri_cPt:
897    case Hexagon::POST_STwri_cNotPt:
898    case Hexagon::POST_STwri_cdnPt_V4:
899    case Hexagon::POST_STwri_cdnNotPt_V4:
900
901    // Store double word
902    case Hexagon::POST_STdri:
903    case Hexagon::POST_STdri_cPt:
904    case Hexagon::POST_STdri_cNotPt:
905    case Hexagon::POST_STdri_cdnPt_V4:
906    case Hexagon::POST_STdri_cdnNotPt_V4:
907      return true;
908  }
909}
910
911bool HexagonInstrInfo::isNewValueInst(const MachineInstr *MI) const {
912  if (isNewValueJump(MI))
913    return true;
914
915  if (isNewValueStore(MI))
916    return true;
917
918  return false;
919}
920
921bool HexagonInstrInfo::isSaveCalleeSavedRegsCall(const MachineInstr *MI) const {
922  return MI->getOpcode() == Hexagon::SAVE_REGISTERS_CALL_V4;
923}
924
925bool HexagonInstrInfo::isPredicable(MachineInstr *MI) const {
926  bool isPred = MI->getDesc().isPredicable();
927
928  if (!isPred)
929    return false;
930
931  const int Opc = MI->getOpcode();
932
933  switch(Opc) {
934  case Hexagon::TFRI:
935    return isInt<12>(MI->getOperand(1).getImm());
936
937  case Hexagon::STrid:
938  case Hexagon::STrid_indexed:
939    return isShiftedUInt<6,3>(MI->getOperand(1).getImm());
940
941  case Hexagon::STriw:
942  case Hexagon::STriw_indexed:
943  case Hexagon::STriw_nv_V4:
944    return isShiftedUInt<6,2>(MI->getOperand(1).getImm());
945
946  case Hexagon::STrih:
947  case Hexagon::STrih_indexed:
948  case Hexagon::STrih_nv_V4:
949    return isShiftedUInt<6,1>(MI->getOperand(1).getImm());
950
951  case Hexagon::STrib:
952  case Hexagon::STrib_indexed:
953  case Hexagon::STrib_nv_V4:
954    return isUInt<6>(MI->getOperand(1).getImm());
955
956  case Hexagon::LDrid:
957  case Hexagon::LDrid_indexed:
958    return isShiftedUInt<6,3>(MI->getOperand(2).getImm());
959
960  case Hexagon::LDriw:
961  case Hexagon::LDriw_indexed:
962    return isShiftedUInt<6,2>(MI->getOperand(2).getImm());
963
964  case Hexagon::LDrih:
965  case Hexagon::LDriuh:
966  case Hexagon::LDrih_indexed:
967  case Hexagon::LDriuh_indexed:
968    return isShiftedUInt<6,1>(MI->getOperand(2).getImm());
969
970  case Hexagon::LDrib:
971  case Hexagon::LDriub:
972  case Hexagon::LDrib_indexed:
973  case Hexagon::LDriub_indexed:
974    return isUInt<6>(MI->getOperand(2).getImm());
975
976  case Hexagon::POST_LDrid:
977    return isShiftedInt<4,3>(MI->getOperand(3).getImm());
978
979  case Hexagon::POST_LDriw:
980    return isShiftedInt<4,2>(MI->getOperand(3).getImm());
981
982  case Hexagon::POST_LDrih:
983  case Hexagon::POST_LDriuh:
984    return isShiftedInt<4,1>(MI->getOperand(3).getImm());
985
986  case Hexagon::POST_LDrib:
987  case Hexagon::POST_LDriub:
988    return isInt<4>(MI->getOperand(3).getImm());
989
990  case Hexagon::STrib_imm_V4:
991  case Hexagon::STrih_imm_V4:
992  case Hexagon::STriw_imm_V4:
993    return (isUInt<6>(MI->getOperand(1).getImm()) &&
994            isInt<6>(MI->getOperand(2).getImm()));
995
996  case Hexagon::ADD_ri:
997    return isInt<8>(MI->getOperand(2).getImm());
998
999  case Hexagon::ASLH:
1000  case Hexagon::ASRH:
1001  case Hexagon::SXTB:
1002  case Hexagon::SXTH:
1003  case Hexagon::ZXTB:
1004  case Hexagon::ZXTH:
1005    return Subtarget.hasV4TOps();
1006
1007  case Hexagon::JMPR:
1008    return false;
1009  }
1010
1011  return true;
1012}
1013
1014// This function performs the following inversiones:
1015//
1016//  cPt    ---> cNotPt
1017//  cNotPt ---> cPt
1018//
1019// however, these inversiones are NOT included:
1020//
1021//  cdnPt      -X-> cdnNotPt
1022//  cdnNotPt   -X-> cdnPt
1023//  cPt_nv     -X-> cNotPt_nv (new value stores)
1024//  cNotPt_nv  -X-> cPt_nv    (new value stores)
1025//
1026// because only the following transformations are allowed:
1027//
1028//  cNotPt  ---> cdnNotPt
1029//  cPt     ---> cdnPt
1030//  cNotPt  ---> cNotPt_nv
1031//  cPt     ---> cPt_nv
1032unsigned HexagonInstrInfo::getInvertedPredicatedOpcode(const int Opc) const {
1033  switch(Opc) {
1034    default: llvm_unreachable("Unexpected predicated instruction");
1035    case Hexagon::TFR_cPt:
1036      return Hexagon::TFR_cNotPt;
1037    case Hexagon::TFR_cNotPt:
1038      return Hexagon::TFR_cPt;
1039
1040    case Hexagon::TFRI_cPt:
1041      return Hexagon::TFRI_cNotPt;
1042    case Hexagon::TFRI_cNotPt:
1043      return Hexagon::TFRI_cPt;
1044
1045    case Hexagon::JMP_c:
1046      return Hexagon::JMP_cNot;
1047    case Hexagon::JMP_cNot:
1048      return Hexagon::JMP_c;
1049
1050    case Hexagon::ADD_ri_cPt:
1051      return Hexagon::ADD_ri_cNotPt;
1052    case Hexagon::ADD_ri_cNotPt:
1053      return Hexagon::ADD_ri_cPt;
1054
1055    case Hexagon::ADD_rr_cPt:
1056      return Hexagon::ADD_rr_cNotPt;
1057    case Hexagon::ADD_rr_cNotPt:
1058      return Hexagon::ADD_rr_cPt;
1059
1060    case Hexagon::XOR_rr_cPt:
1061      return Hexagon::XOR_rr_cNotPt;
1062    case Hexagon::XOR_rr_cNotPt:
1063      return Hexagon::XOR_rr_cPt;
1064
1065    case Hexagon::AND_rr_cPt:
1066      return Hexagon::AND_rr_cNotPt;
1067    case Hexagon::AND_rr_cNotPt:
1068      return Hexagon::AND_rr_cPt;
1069
1070    case Hexagon::OR_rr_cPt:
1071      return Hexagon::OR_rr_cNotPt;
1072    case Hexagon::OR_rr_cNotPt:
1073      return Hexagon::OR_rr_cPt;
1074
1075    case Hexagon::SUB_rr_cPt:
1076      return Hexagon::SUB_rr_cNotPt;
1077    case Hexagon::SUB_rr_cNotPt:
1078      return Hexagon::SUB_rr_cPt;
1079
1080    case Hexagon::COMBINE_rr_cPt:
1081      return Hexagon::COMBINE_rr_cNotPt;
1082    case Hexagon::COMBINE_rr_cNotPt:
1083      return Hexagon::COMBINE_rr_cPt;
1084
1085    case Hexagon::ASLH_cPt_V4:
1086      return Hexagon::ASLH_cNotPt_V4;
1087    case Hexagon::ASLH_cNotPt_V4:
1088      return Hexagon::ASLH_cPt_V4;
1089
1090    case Hexagon::ASRH_cPt_V4:
1091      return Hexagon::ASRH_cNotPt_V4;
1092    case Hexagon::ASRH_cNotPt_V4:
1093      return Hexagon::ASRH_cPt_V4;
1094
1095    case Hexagon::SXTB_cPt_V4:
1096      return Hexagon::SXTB_cNotPt_V4;
1097    case Hexagon::SXTB_cNotPt_V4:
1098      return Hexagon::SXTB_cPt_V4;
1099
1100    case Hexagon::SXTH_cPt_V4:
1101      return Hexagon::SXTH_cNotPt_V4;
1102    case Hexagon::SXTH_cNotPt_V4:
1103      return Hexagon::SXTH_cPt_V4;
1104
1105    case Hexagon::ZXTB_cPt_V4:
1106      return Hexagon::ZXTB_cNotPt_V4;
1107    case Hexagon::ZXTB_cNotPt_V4:
1108      return Hexagon::ZXTB_cPt_V4;
1109
1110    case Hexagon::ZXTH_cPt_V4:
1111      return Hexagon::ZXTH_cNotPt_V4;
1112    case Hexagon::ZXTH_cNotPt_V4:
1113      return Hexagon::ZXTH_cPt_V4;
1114
1115
1116    case Hexagon::JMPR_cPt:
1117      return Hexagon::JMPR_cNotPt;
1118    case Hexagon::JMPR_cNotPt:
1119      return Hexagon::JMPR_cPt;
1120
1121  // V4 indexed+scaled load.
1122    case Hexagon::LDrid_indexed_shl_cPt_V4:
1123      return Hexagon::LDrid_indexed_shl_cNotPt_V4;
1124    case Hexagon::LDrid_indexed_shl_cNotPt_V4:
1125      return Hexagon::LDrid_indexed_shl_cPt_V4;
1126
1127    case Hexagon::LDrib_indexed_shl_cPt_V4:
1128      return Hexagon::LDrib_indexed_shl_cNotPt_V4;
1129    case Hexagon::LDrib_indexed_shl_cNotPt_V4:
1130      return Hexagon::LDrib_indexed_shl_cPt_V4;
1131
1132    case Hexagon::LDriub_indexed_shl_cPt_V4:
1133      return Hexagon::LDriub_indexed_shl_cNotPt_V4;
1134    case Hexagon::LDriub_indexed_shl_cNotPt_V4:
1135      return Hexagon::LDriub_indexed_shl_cPt_V4;
1136
1137    case Hexagon::LDrih_indexed_shl_cPt_V4:
1138      return Hexagon::LDrih_indexed_shl_cNotPt_V4;
1139    case Hexagon::LDrih_indexed_shl_cNotPt_V4:
1140      return Hexagon::LDrih_indexed_shl_cPt_V4;
1141
1142    case Hexagon::LDriuh_indexed_shl_cPt_V4:
1143      return Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1144    case Hexagon::LDriuh_indexed_shl_cNotPt_V4:
1145      return Hexagon::LDriuh_indexed_shl_cPt_V4;
1146
1147    case Hexagon::LDriw_indexed_shl_cPt_V4:
1148      return Hexagon::LDriw_indexed_shl_cNotPt_V4;
1149    case Hexagon::LDriw_indexed_shl_cNotPt_V4:
1150      return Hexagon::LDriw_indexed_shl_cPt_V4;
1151
1152    // Byte.
1153    case Hexagon::POST_STbri_cPt:
1154      return Hexagon::POST_STbri_cNotPt;
1155    case Hexagon::POST_STbri_cNotPt:
1156      return Hexagon::POST_STbri_cPt;
1157
1158    case Hexagon::STrib_cPt:
1159      return Hexagon::STrib_cNotPt;
1160    case Hexagon::STrib_cNotPt:
1161      return Hexagon::STrib_cPt;
1162
1163    case Hexagon::STrib_indexed_cPt:
1164      return Hexagon::STrib_indexed_cNotPt;
1165    case Hexagon::STrib_indexed_cNotPt:
1166      return Hexagon::STrib_indexed_cPt;
1167
1168    case Hexagon::STrib_imm_cPt_V4:
1169      return Hexagon::STrib_imm_cNotPt_V4;
1170    case Hexagon::STrib_imm_cNotPt_V4:
1171      return Hexagon::STrib_imm_cPt_V4;
1172
1173    case Hexagon::STrib_indexed_shl_cPt_V4:
1174      return Hexagon::STrib_indexed_shl_cNotPt_V4;
1175    case Hexagon::STrib_indexed_shl_cNotPt_V4:
1176      return Hexagon::STrib_indexed_shl_cPt_V4;
1177
1178  // Halfword.
1179    case Hexagon::POST_SThri_cPt:
1180      return Hexagon::POST_SThri_cNotPt;
1181    case Hexagon::POST_SThri_cNotPt:
1182      return Hexagon::POST_SThri_cPt;
1183
1184    case Hexagon::STrih_cPt:
1185      return Hexagon::STrih_cNotPt;
1186    case Hexagon::STrih_cNotPt:
1187      return Hexagon::STrih_cPt;
1188
1189    case Hexagon::STrih_indexed_cPt:
1190      return Hexagon::STrih_indexed_cNotPt;
1191    case Hexagon::STrih_indexed_cNotPt:
1192      return Hexagon::STrih_indexed_cPt;
1193
1194    case Hexagon::STrih_imm_cPt_V4:
1195      return Hexagon::STrih_imm_cNotPt_V4;
1196    case Hexagon::STrih_imm_cNotPt_V4:
1197      return Hexagon::STrih_imm_cPt_V4;
1198
1199    case Hexagon::STrih_indexed_shl_cPt_V4:
1200      return Hexagon::STrih_indexed_shl_cNotPt_V4;
1201    case Hexagon::STrih_indexed_shl_cNotPt_V4:
1202      return Hexagon::STrih_indexed_shl_cPt_V4;
1203
1204  // Word.
1205    case Hexagon::POST_STwri_cPt:
1206      return Hexagon::POST_STwri_cNotPt;
1207    case Hexagon::POST_STwri_cNotPt:
1208      return Hexagon::POST_STwri_cPt;
1209
1210    case Hexagon::STriw_cPt:
1211      return Hexagon::STriw_cNotPt;
1212    case Hexagon::STriw_cNotPt:
1213      return Hexagon::STriw_cPt;
1214
1215    case Hexagon::STriw_indexed_cPt:
1216      return Hexagon::STriw_indexed_cNotPt;
1217    case Hexagon::STriw_indexed_cNotPt:
1218      return Hexagon::STriw_indexed_cPt;
1219
1220    case Hexagon::STriw_indexed_shl_cPt_V4:
1221      return Hexagon::STriw_indexed_shl_cNotPt_V4;
1222    case Hexagon::STriw_indexed_shl_cNotPt_V4:
1223      return Hexagon::STriw_indexed_shl_cPt_V4;
1224
1225    case Hexagon::STriw_imm_cPt_V4:
1226      return Hexagon::STriw_imm_cNotPt_V4;
1227    case Hexagon::STriw_imm_cNotPt_V4:
1228      return Hexagon::STriw_imm_cPt_V4;
1229
1230  // Double word.
1231    case Hexagon::POST_STdri_cPt:
1232      return Hexagon::POST_STdri_cNotPt;
1233    case Hexagon::POST_STdri_cNotPt:
1234      return Hexagon::POST_STdri_cPt;
1235
1236    case Hexagon::STrid_cPt:
1237      return Hexagon::STrid_cNotPt;
1238    case Hexagon::STrid_cNotPt:
1239      return Hexagon::STrid_cPt;
1240
1241    case Hexagon::STrid_indexed_cPt:
1242      return Hexagon::STrid_indexed_cNotPt;
1243    case Hexagon::STrid_indexed_cNotPt:
1244      return Hexagon::STrid_indexed_cPt;
1245
1246    case Hexagon::STrid_indexed_shl_cPt_V4:
1247      return Hexagon::STrid_indexed_shl_cNotPt_V4;
1248    case Hexagon::STrid_indexed_shl_cNotPt_V4:
1249      return Hexagon::STrid_indexed_shl_cPt_V4;
1250
1251    // V4 Store to global address.
1252    case Hexagon::STd_GP_cPt_V4:
1253      return Hexagon::STd_GP_cNotPt_V4;
1254    case Hexagon::STd_GP_cNotPt_V4:
1255      return Hexagon::STd_GP_cPt_V4;
1256
1257    case Hexagon::STb_GP_cPt_V4:
1258      return Hexagon::STb_GP_cNotPt_V4;
1259    case Hexagon::STb_GP_cNotPt_V4:
1260      return Hexagon::STb_GP_cPt_V4;
1261
1262    case Hexagon::STh_GP_cPt_V4:
1263      return Hexagon::STh_GP_cNotPt_V4;
1264    case Hexagon::STh_GP_cNotPt_V4:
1265      return Hexagon::STh_GP_cPt_V4;
1266
1267    case Hexagon::STw_GP_cPt_V4:
1268      return Hexagon::STw_GP_cNotPt_V4;
1269    case Hexagon::STw_GP_cNotPt_V4:
1270      return Hexagon::STw_GP_cPt_V4;
1271
1272  // Load.
1273    case Hexagon::LDrid_cPt:
1274      return Hexagon::LDrid_cNotPt;
1275    case Hexagon::LDrid_cNotPt:
1276      return Hexagon::LDrid_cPt;
1277
1278    case Hexagon::LDriw_cPt:
1279      return Hexagon::LDriw_cNotPt;
1280    case Hexagon::LDriw_cNotPt:
1281      return Hexagon::LDriw_cPt;
1282
1283    case Hexagon::LDrih_cPt:
1284      return Hexagon::LDrih_cNotPt;
1285    case Hexagon::LDrih_cNotPt:
1286      return Hexagon::LDrih_cPt;
1287
1288    case Hexagon::LDriuh_cPt:
1289      return Hexagon::LDriuh_cNotPt;
1290    case Hexagon::LDriuh_cNotPt:
1291      return Hexagon::LDriuh_cPt;
1292
1293    case Hexagon::LDrib_cPt:
1294      return Hexagon::LDrib_cNotPt;
1295    case Hexagon::LDrib_cNotPt:
1296      return Hexagon::LDrib_cPt;
1297
1298    case Hexagon::LDriub_cPt:
1299      return Hexagon::LDriub_cNotPt;
1300    case Hexagon::LDriub_cNotPt:
1301      return Hexagon::LDriub_cPt;
1302
1303 // Load Indexed.
1304    case Hexagon::LDrid_indexed_cPt:
1305      return Hexagon::LDrid_indexed_cNotPt;
1306    case Hexagon::LDrid_indexed_cNotPt:
1307      return Hexagon::LDrid_indexed_cPt;
1308
1309    case Hexagon::LDriw_indexed_cPt:
1310      return Hexagon::LDriw_indexed_cNotPt;
1311    case Hexagon::LDriw_indexed_cNotPt:
1312      return Hexagon::LDriw_indexed_cPt;
1313
1314    case Hexagon::LDrih_indexed_cPt:
1315      return Hexagon::LDrih_indexed_cNotPt;
1316    case Hexagon::LDrih_indexed_cNotPt:
1317      return Hexagon::LDrih_indexed_cPt;
1318
1319    case Hexagon::LDriuh_indexed_cPt:
1320      return Hexagon::LDriuh_indexed_cNotPt;
1321    case Hexagon::LDriuh_indexed_cNotPt:
1322      return Hexagon::LDriuh_indexed_cPt;
1323
1324    case Hexagon::LDrib_indexed_cPt:
1325      return Hexagon::LDrib_indexed_cNotPt;
1326    case Hexagon::LDrib_indexed_cNotPt:
1327      return Hexagon::LDrib_indexed_cPt;
1328
1329    case Hexagon::LDriub_indexed_cPt:
1330      return Hexagon::LDriub_indexed_cNotPt;
1331    case Hexagon::LDriub_indexed_cNotPt:
1332      return Hexagon::LDriub_indexed_cPt;
1333
1334  // Post Inc Load.
1335    case Hexagon::POST_LDrid_cPt:
1336      return Hexagon::POST_LDrid_cNotPt;
1337    case Hexagon::POST_LDriw_cNotPt:
1338      return Hexagon::POST_LDriw_cPt;
1339
1340    case Hexagon::POST_LDrih_cPt:
1341      return Hexagon::POST_LDrih_cNotPt;
1342    case Hexagon::POST_LDrih_cNotPt:
1343      return Hexagon::POST_LDrih_cPt;
1344
1345    case Hexagon::POST_LDriuh_cPt:
1346      return Hexagon::POST_LDriuh_cNotPt;
1347    case Hexagon::POST_LDriuh_cNotPt:
1348      return Hexagon::POST_LDriuh_cPt;
1349
1350    case Hexagon::POST_LDrib_cPt:
1351      return Hexagon::POST_LDrib_cNotPt;
1352    case Hexagon::POST_LDrib_cNotPt:
1353      return Hexagon::POST_LDrib_cPt;
1354
1355    case Hexagon::POST_LDriub_cPt:
1356      return Hexagon::POST_LDriub_cNotPt;
1357    case Hexagon::POST_LDriub_cNotPt:
1358      return Hexagon::POST_LDriub_cPt;
1359
1360  // Dealloc_return.
1361    case Hexagon::DEALLOC_RET_cPt_V4:
1362      return Hexagon::DEALLOC_RET_cNotPt_V4;
1363    case Hexagon::DEALLOC_RET_cNotPt_V4:
1364      return Hexagon::DEALLOC_RET_cPt_V4;
1365
1366   // New Value Jump.
1367   // JMPEQ_ri - with -1.
1368    case Hexagon::JMP_EQriPtneg_nv_V4:
1369      return Hexagon::JMP_EQriNotPtneg_nv_V4;
1370    case Hexagon::JMP_EQriNotPtneg_nv_V4:
1371      return Hexagon::JMP_EQriPtneg_nv_V4;
1372
1373    case Hexagon::JMP_EQriPntneg_nv_V4:
1374      return Hexagon::JMP_EQriNotPntneg_nv_V4;
1375    case Hexagon::JMP_EQriNotPntneg_nv_V4:
1376      return Hexagon::JMP_EQriPntneg_nv_V4;
1377
1378   // JMPEQ_ri.
1379     case Hexagon::JMP_EQriPt_nv_V4:
1380      return Hexagon::JMP_EQriNotPt_nv_V4;
1381    case Hexagon::JMP_EQriNotPt_nv_V4:
1382      return Hexagon::JMP_EQriPt_nv_V4;
1383
1384     case Hexagon::JMP_EQriPnt_nv_V4:
1385      return Hexagon::JMP_EQriNotPnt_nv_V4;
1386    case Hexagon::JMP_EQriNotPnt_nv_V4:
1387      return Hexagon::JMP_EQriPnt_nv_V4;
1388
1389   // JMPEQ_rr.
1390     case Hexagon::JMP_EQrrPt_nv_V4:
1391      return Hexagon::JMP_EQrrNotPt_nv_V4;
1392    case Hexagon::JMP_EQrrNotPt_nv_V4:
1393      return Hexagon::JMP_EQrrPt_nv_V4;
1394
1395     case Hexagon::JMP_EQrrPnt_nv_V4:
1396      return Hexagon::JMP_EQrrNotPnt_nv_V4;
1397    case Hexagon::JMP_EQrrNotPnt_nv_V4:
1398      return Hexagon::JMP_EQrrPnt_nv_V4;
1399
1400   // JMPGT_ri - with -1.
1401    case Hexagon::JMP_GTriPtneg_nv_V4:
1402      return Hexagon::JMP_GTriNotPtneg_nv_V4;
1403    case Hexagon::JMP_GTriNotPtneg_nv_V4:
1404      return Hexagon::JMP_GTriPtneg_nv_V4;
1405
1406    case Hexagon::JMP_GTriPntneg_nv_V4:
1407      return Hexagon::JMP_GTriNotPntneg_nv_V4;
1408    case Hexagon::JMP_GTriNotPntneg_nv_V4:
1409      return Hexagon::JMP_GTriPntneg_nv_V4;
1410
1411   // JMPGT_ri.
1412     case Hexagon::JMP_GTriPt_nv_V4:
1413      return Hexagon::JMP_GTriNotPt_nv_V4;
1414    case Hexagon::JMP_GTriNotPt_nv_V4:
1415      return Hexagon::JMP_GTriPt_nv_V4;
1416
1417     case Hexagon::JMP_GTriPnt_nv_V4:
1418      return Hexagon::JMP_GTriNotPnt_nv_V4;
1419    case Hexagon::JMP_GTriNotPnt_nv_V4:
1420      return Hexagon::JMP_GTriPnt_nv_V4;
1421
1422   // JMPGT_rr.
1423     case Hexagon::JMP_GTrrPt_nv_V4:
1424      return Hexagon::JMP_GTrrNotPt_nv_V4;
1425    case Hexagon::JMP_GTrrNotPt_nv_V4:
1426      return Hexagon::JMP_GTrrPt_nv_V4;
1427
1428     case Hexagon::JMP_GTrrPnt_nv_V4:
1429      return Hexagon::JMP_GTrrNotPnt_nv_V4;
1430    case Hexagon::JMP_GTrrNotPnt_nv_V4:
1431      return Hexagon::JMP_GTrrPnt_nv_V4;
1432
1433   // JMPGT_rrdn.
1434     case Hexagon::JMP_GTrrdnPt_nv_V4:
1435      return Hexagon::JMP_GTrrdnNotPt_nv_V4;
1436    case Hexagon::JMP_GTrrdnNotPt_nv_V4:
1437      return Hexagon::JMP_GTrrdnPt_nv_V4;
1438
1439     case Hexagon::JMP_GTrrdnPnt_nv_V4:
1440      return Hexagon::JMP_GTrrdnNotPnt_nv_V4;
1441    case Hexagon::JMP_GTrrdnNotPnt_nv_V4:
1442      return Hexagon::JMP_GTrrdnPnt_nv_V4;
1443
1444   // JMPGTU_ri.
1445     case Hexagon::JMP_GTUriPt_nv_V4:
1446      return Hexagon::JMP_GTUriNotPt_nv_V4;
1447    case Hexagon::JMP_GTUriNotPt_nv_V4:
1448      return Hexagon::JMP_GTUriPt_nv_V4;
1449
1450     case Hexagon::JMP_GTUriPnt_nv_V4:
1451      return Hexagon::JMP_GTUriNotPnt_nv_V4;
1452    case Hexagon::JMP_GTUriNotPnt_nv_V4:
1453      return Hexagon::JMP_GTUriPnt_nv_V4;
1454
1455   // JMPGTU_rr.
1456     case Hexagon::JMP_GTUrrPt_nv_V4:
1457      return Hexagon::JMP_GTUrrNotPt_nv_V4;
1458    case Hexagon::JMP_GTUrrNotPt_nv_V4:
1459      return Hexagon::JMP_GTUrrPt_nv_V4;
1460
1461     case Hexagon::JMP_GTUrrPnt_nv_V4:
1462      return Hexagon::JMP_GTUrrNotPnt_nv_V4;
1463    case Hexagon::JMP_GTUrrNotPnt_nv_V4:
1464      return Hexagon::JMP_GTUrrPnt_nv_V4;
1465
1466   // JMPGTU_rrdn.
1467     case Hexagon::JMP_GTUrrdnPt_nv_V4:
1468      return Hexagon::JMP_GTUrrdnNotPt_nv_V4;
1469    case Hexagon::JMP_GTUrrdnNotPt_nv_V4:
1470      return Hexagon::JMP_GTUrrdnPt_nv_V4;
1471
1472     case Hexagon::JMP_GTUrrdnPnt_nv_V4:
1473      return Hexagon::JMP_GTUrrdnNotPnt_nv_V4;
1474    case Hexagon::JMP_GTUrrdnNotPnt_nv_V4:
1475      return Hexagon::JMP_GTUrrdnPnt_nv_V4;
1476  }
1477}
1478
1479
1480int HexagonInstrInfo::
1481getMatchingCondBranchOpcode(int Opc, bool invertPredicate) const {
1482  enum Hexagon::PredSense inPredSense;
1483  inPredSense = invertPredicate ? Hexagon::PredSense_false :
1484                                  Hexagon::PredSense_true;
1485  int CondOpcode = Hexagon::getPredOpcode(Opc, inPredSense);
1486  if (CondOpcode >= 0) // Valid Conditional opcode/instruction
1487    return CondOpcode;
1488
1489  // This switch case will be removed once all the instructions have been
1490  // modified to use relation maps.
1491  switch(Opc) {
1492  case Hexagon::TFR:
1493    return !invertPredicate ? Hexagon::TFR_cPt :
1494                              Hexagon::TFR_cNotPt;
1495  case Hexagon::TFRI_f:
1496    return !invertPredicate ? Hexagon::TFRI_cPt_f :
1497                              Hexagon::TFRI_cNotPt_f;
1498  case Hexagon::TFRI:
1499    return !invertPredicate ? Hexagon::TFRI_cPt :
1500                              Hexagon::TFRI_cNotPt;
1501  case Hexagon::JMP:
1502    return !invertPredicate ? Hexagon::JMP_c :
1503                              Hexagon::JMP_cNot;
1504  case Hexagon::JMP_EQrrPt_nv_V4:
1505    return !invertPredicate ? Hexagon::JMP_EQrrPt_nv_V4 :
1506                              Hexagon::JMP_EQrrNotPt_nv_V4;
1507  case Hexagon::JMP_EQriPt_nv_V4:
1508    return !invertPredicate ? Hexagon::JMP_EQriPt_nv_V4 :
1509                              Hexagon::JMP_EQriNotPt_nv_V4;
1510  case Hexagon::COMBINE_rr:
1511    return !invertPredicate ? Hexagon::COMBINE_rr_cPt :
1512                              Hexagon::COMBINE_rr_cNotPt;
1513  case Hexagon::ASLH:
1514    return !invertPredicate ? Hexagon::ASLH_cPt_V4 :
1515                              Hexagon::ASLH_cNotPt_V4;
1516  case Hexagon::ASRH:
1517    return !invertPredicate ? Hexagon::ASRH_cPt_V4 :
1518                              Hexagon::ASRH_cNotPt_V4;
1519  case Hexagon::SXTB:
1520    return !invertPredicate ? Hexagon::SXTB_cPt_V4 :
1521                              Hexagon::SXTB_cNotPt_V4;
1522  case Hexagon::SXTH:
1523    return !invertPredicate ? Hexagon::SXTH_cPt_V4 :
1524                              Hexagon::SXTH_cNotPt_V4;
1525  case Hexagon::ZXTB:
1526    return !invertPredicate ? Hexagon::ZXTB_cPt_V4 :
1527                              Hexagon::ZXTB_cNotPt_V4;
1528  case Hexagon::ZXTH:
1529    return !invertPredicate ? Hexagon::ZXTH_cPt_V4 :
1530                              Hexagon::ZXTH_cNotPt_V4;
1531
1532  case Hexagon::JMPR:
1533    return !invertPredicate ? Hexagon::JMPR_cPt :
1534                              Hexagon::JMPR_cNotPt;
1535
1536  // V4 indexed+scaled load.
1537  case Hexagon::LDrid_indexed_shl_V4:
1538    return !invertPredicate ? Hexagon::LDrid_indexed_shl_cPt_V4 :
1539                              Hexagon::LDrid_indexed_shl_cNotPt_V4;
1540  case Hexagon::LDrib_indexed_shl_V4:
1541    return !invertPredicate ? Hexagon::LDrib_indexed_shl_cPt_V4 :
1542                              Hexagon::LDrib_indexed_shl_cNotPt_V4;
1543  case Hexagon::LDriub_indexed_shl_V4:
1544    return !invertPredicate ? Hexagon::LDriub_indexed_shl_cPt_V4 :
1545                              Hexagon::LDriub_indexed_shl_cNotPt_V4;
1546  case Hexagon::LDrih_indexed_shl_V4:
1547    return !invertPredicate ? Hexagon::LDrih_indexed_shl_cPt_V4 :
1548                              Hexagon::LDrih_indexed_shl_cNotPt_V4;
1549  case Hexagon::LDriuh_indexed_shl_V4:
1550    return !invertPredicate ? Hexagon::LDriuh_indexed_shl_cPt_V4 :
1551                              Hexagon::LDriuh_indexed_shl_cNotPt_V4;
1552  case Hexagon::LDriw_indexed_shl_V4:
1553    return !invertPredicate ? Hexagon::LDriw_indexed_shl_cPt_V4 :
1554                              Hexagon::LDriw_indexed_shl_cNotPt_V4;
1555
1556  // V4 Load from global address
1557  case Hexagon::LDd_GP_V4:
1558    return !invertPredicate ? Hexagon::LDd_GP_cPt_V4 :
1559                              Hexagon::LDd_GP_cNotPt_V4;
1560  case Hexagon::LDb_GP_V4:
1561    return !invertPredicate ? Hexagon::LDb_GP_cPt_V4 :
1562                              Hexagon::LDb_GP_cNotPt_V4;
1563  case Hexagon::LDub_GP_V4:
1564    return !invertPredicate ? Hexagon::LDub_GP_cPt_V4 :
1565                              Hexagon::LDub_GP_cNotPt_V4;
1566  case Hexagon::LDh_GP_V4:
1567    return !invertPredicate ? Hexagon::LDh_GP_cPt_V4 :
1568                              Hexagon::LDh_GP_cNotPt_V4;
1569  case Hexagon::LDuh_GP_V4:
1570    return !invertPredicate ? Hexagon::LDuh_GP_cPt_V4 :
1571                              Hexagon::LDuh_GP_cNotPt_V4;
1572  case Hexagon::LDw_GP_V4:
1573    return !invertPredicate ? Hexagon::LDw_GP_cPt_V4 :
1574                              Hexagon::LDw_GP_cNotPt_V4;
1575
1576    // Byte.
1577  case Hexagon::POST_STbri:
1578    return !invertPredicate ? Hexagon::POST_STbri_cPt :
1579                              Hexagon::POST_STbri_cNotPt;
1580  case Hexagon::STrib:
1581    return !invertPredicate ? Hexagon::STrib_cPt :
1582                              Hexagon::STrib_cNotPt;
1583  case Hexagon::STrib_indexed:
1584    return !invertPredicate ? Hexagon::STrib_indexed_cPt :
1585                              Hexagon::STrib_indexed_cNotPt;
1586  case Hexagon::STrib_imm_V4:
1587    return !invertPredicate ? Hexagon::STrib_imm_cPt_V4 :
1588                              Hexagon::STrib_imm_cNotPt_V4;
1589  case Hexagon::STrib_indexed_shl_V4:
1590    return !invertPredicate ? Hexagon::STrib_indexed_shl_cPt_V4 :
1591                              Hexagon::STrib_indexed_shl_cNotPt_V4;
1592  // Halfword.
1593  case Hexagon::POST_SThri:
1594    return !invertPredicate ? Hexagon::POST_SThri_cPt :
1595                              Hexagon::POST_SThri_cNotPt;
1596  case Hexagon::STrih:
1597    return !invertPredicate ? Hexagon::STrih_cPt :
1598                              Hexagon::STrih_cNotPt;
1599  case Hexagon::STrih_indexed:
1600    return !invertPredicate ? Hexagon::STrih_indexed_cPt :
1601                              Hexagon::STrih_indexed_cNotPt;
1602  case Hexagon::STrih_imm_V4:
1603    return !invertPredicate ? Hexagon::STrih_imm_cPt_V4 :
1604                              Hexagon::STrih_imm_cNotPt_V4;
1605  case Hexagon::STrih_indexed_shl_V4:
1606    return !invertPredicate ? Hexagon::STrih_indexed_shl_cPt_V4 :
1607                              Hexagon::STrih_indexed_shl_cNotPt_V4;
1608  // Word.
1609  case Hexagon::POST_STwri:
1610    return !invertPredicate ? Hexagon::POST_STwri_cPt :
1611                              Hexagon::POST_STwri_cNotPt;
1612  case Hexagon::STriw:
1613    return !invertPredicate ? Hexagon::STriw_cPt :
1614                              Hexagon::STriw_cNotPt;
1615  case Hexagon::STriw_indexed:
1616    return !invertPredicate ? Hexagon::STriw_indexed_cPt :
1617                              Hexagon::STriw_indexed_cNotPt;
1618  case Hexagon::STriw_indexed_shl_V4:
1619    return !invertPredicate ? Hexagon::STriw_indexed_shl_cPt_V4 :
1620                              Hexagon::STriw_indexed_shl_cNotPt_V4;
1621  case Hexagon::STriw_imm_V4:
1622    return !invertPredicate ? Hexagon::STriw_imm_cPt_V4 :
1623                              Hexagon::STriw_imm_cNotPt_V4;
1624  // Double word.
1625  case Hexagon::POST_STdri:
1626    return !invertPredicate ? Hexagon::POST_STdri_cPt :
1627                              Hexagon::POST_STdri_cNotPt;
1628  case Hexagon::STrid:
1629    return !invertPredicate ? Hexagon::STrid_cPt :
1630                              Hexagon::STrid_cNotPt;
1631  case Hexagon::STrid_indexed:
1632    return !invertPredicate ? Hexagon::STrid_indexed_cPt :
1633                              Hexagon::STrid_indexed_cNotPt;
1634  case Hexagon::STrid_indexed_shl_V4:
1635    return !invertPredicate ? Hexagon::STrid_indexed_shl_cPt_V4 :
1636                              Hexagon::STrid_indexed_shl_cNotPt_V4;
1637
1638  // V4 Store to global address
1639  case Hexagon::STd_GP_V4:
1640    return !invertPredicate ? Hexagon::STd_GP_cPt_V4 :
1641                              Hexagon::STd_GP_cNotPt_V4;
1642  case Hexagon::STb_GP_V4:
1643    return !invertPredicate ? Hexagon::STb_GP_cPt_V4 :
1644                              Hexagon::STb_GP_cNotPt_V4;
1645  case Hexagon::STh_GP_V4:
1646    return !invertPredicate ? Hexagon::STh_GP_cPt_V4 :
1647                              Hexagon::STh_GP_cNotPt_V4;
1648  case Hexagon::STw_GP_V4:
1649    return !invertPredicate ? Hexagon::STw_GP_cPt_V4 :
1650                              Hexagon::STw_GP_cNotPt_V4;
1651
1652  // Load.
1653  case Hexagon::LDrid:
1654    return !invertPredicate ? Hexagon::LDrid_cPt :
1655                              Hexagon::LDrid_cNotPt;
1656  case Hexagon::LDriw:
1657    return !invertPredicate ? Hexagon::LDriw_cPt :
1658                              Hexagon::LDriw_cNotPt;
1659  case Hexagon::LDrih:
1660    return !invertPredicate ? Hexagon::LDrih_cPt :
1661                              Hexagon::LDrih_cNotPt;
1662  case Hexagon::LDriuh:
1663    return !invertPredicate ? Hexagon::LDriuh_cPt :
1664                              Hexagon::LDriuh_cNotPt;
1665  case Hexagon::LDrib:
1666    return !invertPredicate ? Hexagon::LDrib_cPt :
1667                              Hexagon::LDrib_cNotPt;
1668  case Hexagon::LDriub:
1669    return !invertPredicate ? Hexagon::LDriub_cPt :
1670                              Hexagon::LDriub_cNotPt;
1671 // Load Indexed.
1672  case Hexagon::LDrid_indexed:
1673    return !invertPredicate ? Hexagon::LDrid_indexed_cPt :
1674                              Hexagon::LDrid_indexed_cNotPt;
1675  case Hexagon::LDriw_indexed:
1676    return !invertPredicate ? Hexagon::LDriw_indexed_cPt :
1677                              Hexagon::LDriw_indexed_cNotPt;
1678  case Hexagon::LDrih_indexed:
1679    return !invertPredicate ? Hexagon::LDrih_indexed_cPt :
1680                              Hexagon::LDrih_indexed_cNotPt;
1681  case Hexagon::LDriuh_indexed:
1682    return !invertPredicate ? Hexagon::LDriuh_indexed_cPt :
1683                              Hexagon::LDriuh_indexed_cNotPt;
1684  case Hexagon::LDrib_indexed:
1685    return !invertPredicate ? Hexagon::LDrib_indexed_cPt :
1686                              Hexagon::LDrib_indexed_cNotPt;
1687  case Hexagon::LDriub_indexed:
1688    return !invertPredicate ? Hexagon::LDriub_indexed_cPt :
1689                              Hexagon::LDriub_indexed_cNotPt;
1690  // Post Increment Load.
1691  case Hexagon::POST_LDrid:
1692    return !invertPredicate ? Hexagon::POST_LDrid_cPt :
1693                              Hexagon::POST_LDrid_cNotPt;
1694  case Hexagon::POST_LDriw:
1695    return !invertPredicate ? Hexagon::POST_LDriw_cPt :
1696                              Hexagon::POST_LDriw_cNotPt;
1697  case Hexagon::POST_LDrih:
1698    return !invertPredicate ? Hexagon::POST_LDrih_cPt :
1699                              Hexagon::POST_LDrih_cNotPt;
1700  case Hexagon::POST_LDriuh:
1701    return !invertPredicate ? Hexagon::POST_LDriuh_cPt :
1702                              Hexagon::POST_LDriuh_cNotPt;
1703  case Hexagon::POST_LDrib:
1704    return !invertPredicate ? Hexagon::POST_LDrib_cPt :
1705                              Hexagon::POST_LDrib_cNotPt;
1706  case Hexagon::POST_LDriub:
1707    return !invertPredicate ? Hexagon::POST_LDriub_cPt :
1708                              Hexagon::POST_LDriub_cNotPt;
1709  // DEALLOC_RETURN.
1710  case Hexagon::DEALLOC_RET_V4:
1711    return !invertPredicate ? Hexagon::DEALLOC_RET_cPt_V4 :
1712                              Hexagon::DEALLOC_RET_cNotPt_V4;
1713  }
1714  llvm_unreachable("Unexpected predicable instruction");
1715}
1716
1717
1718bool HexagonInstrInfo::
1719PredicateInstruction(MachineInstr *MI,
1720                     const SmallVectorImpl<MachineOperand> &Cond) const {
1721  int Opc = MI->getOpcode();
1722  assert (isPredicable(MI) && "Expected predicable instruction");
1723  bool invertJump = (!Cond.empty() && Cond[0].isImm() &&
1724                     (Cond[0].getImm() == 0));
1725
1726  // This will change MI's opcode to its predicate version.
1727  // However, its operand list is still the old one, i.e. the
1728  // non-predicate one.
1729  MI->setDesc(get(getMatchingCondBranchOpcode(Opc, invertJump)));
1730
1731  int oper = -1;
1732  unsigned int GAIdx = 0;
1733
1734  // Indicates whether the current MI has a GlobalAddress operand
1735  bool hasGAOpnd = false;
1736  std::vector<MachineOperand> tmpOpnds;
1737
1738  // Indicates whether we need to shift operands to right.
1739  bool needShift = true;
1740
1741  // The predicate is ALWAYS the FIRST input operand !!!
1742  if (MI->getNumOperands() == 0) {
1743    // The non-predicate version of MI does not take any operands,
1744    // i.e. no outs and no ins. In this condition, the predicate
1745    // operand will be directly placed at Operands[0]. No operand
1746    // shift is needed.
1747    // Example: BARRIER
1748    needShift = false;
1749    oper = -1;
1750  }
1751  else if (   MI->getOperand(MI->getNumOperands()-1).isReg()
1752           && MI->getOperand(MI->getNumOperands()-1).isDef()
1753           && !MI->getOperand(MI->getNumOperands()-1).isImplicit()) {
1754    // The non-predicate version of MI does not have any input operands.
1755    // In this condition, we extend the length of Operands[] by one and
1756    // copy the original last operand to the newly allocated slot.
1757    // At this moment, it is just a place holder. Later, we will put
1758    // predicate operand directly into it. No operand shift is needed.
1759    // Example: r0=BARRIER (this is a faked insn used here for illustration)
1760    MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
1761    needShift = false;
1762    oper = MI->getNumOperands() - 2;
1763  }
1764  else {
1765    // We need to right shift all input operands by one. Duplicate the
1766    // last operand into the newly allocated slot.
1767    MI->addOperand(MI->getOperand(MI->getNumOperands()-1));
1768  }
1769
1770  if (needShift)
1771  {
1772    // Operands[ MI->getNumOperands() - 2 ] has been copied into
1773    // Operands[ MI->getNumOperands() - 1 ], so we start from
1774    // Operands[ MI->getNumOperands() - 3 ].
1775    // oper is a signed int.
1776    // It is ok if "MI->getNumOperands()-3" is -3, -2, or -1.
1777    for (oper = MI->getNumOperands() - 3; oper >= 0; --oper)
1778    {
1779      MachineOperand &MO = MI->getOperand(oper);
1780
1781      // Opnd[0] Opnd[1] Opnd[2] Opnd[3] Opnd[4]   Opnd[5]   Opnd[6]   Opnd[7]
1782      // <Def0>  <Def1>  <Use0>  <Use1>  <ImpDef0> <ImpDef1> <ImpUse0> <ImpUse1>
1783      //               /\~
1784      //              /||\~
1785      //               ||
1786      //        Predicate Operand here
1787      if (MO.isReg() && !MO.isUse() && !MO.isImplicit()) {
1788        break;
1789      }
1790      if (MO.isReg()) {
1791        MI->getOperand(oper+1).ChangeToRegister(MO.getReg(), MO.isDef(),
1792                                                MO.isImplicit(), MO.isKill(),
1793                                                MO.isDead(), MO.isUndef(),
1794                                                MO.isDebug());
1795      }
1796      else if (MO.isImm()) {
1797        MI->getOperand(oper+1).ChangeToImmediate(MO.getImm());
1798      }
1799      else if (MO.isGlobal()) {
1800        // MI can not have more than one GlobalAddress operand.
1801        assert(hasGAOpnd == false && "MI can only have one GlobalAddress opnd");
1802
1803        // There is no member function called "ChangeToGlobalAddress" in the
1804        // MachineOperand class (not like "ChangeToRegister" and
1805        // "ChangeToImmediate"). So we have to remove them from Operands[] list
1806        // first, and then add them back after we have inserted the predicate
1807        // operand. tmpOpnds[] is to remember these operands before we remove
1808        // them.
1809        tmpOpnds.push_back(MO);
1810
1811        // Operands[oper] is a GlobalAddress operand;
1812        // Operands[oper+1] has been copied into Operands[oper+2];
1813        hasGAOpnd = true;
1814        GAIdx = oper;
1815        continue;
1816      }
1817      else {
1818        assert(false && "Unexpected operand type");
1819      }
1820    }
1821  }
1822
1823  int regPos = invertJump ? 1 : 0;
1824  MachineOperand PredMO = Cond[regPos];
1825
1826  // [oper] now points to the last explicit Def. Predicate operand must be
1827  // located at [oper+1]. See diagram above.
1828  // This assumes that the predicate is always the first operand,
1829  // i.e. Operands[0+numResults], in the set of inputs
1830  // It is better to have an assert here to check this. But I don't know how
1831  // to write this assert because findFirstPredOperandIdx() would return -1
1832  if (oper < -1) oper = -1;
1833  MI->getOperand(oper+1).ChangeToRegister(PredMO.getReg(), PredMO.isDef(),
1834                                          PredMO.isImplicit(), PredMO.isKill(),
1835                                          PredMO.isDead(), PredMO.isUndef(),
1836                                          PredMO.isDebug());
1837
1838  if (hasGAOpnd)
1839  {
1840    unsigned int i;
1841
1842    // Operands[GAIdx] is the original GlobalAddress operand, which is
1843    // already copied into tmpOpnds[0].
1844    // Operands[GAIdx] now stores a copy of Operands[GAIdx-1]
1845    // Operands[GAIdx+1] has already been copied into Operands[GAIdx+2],
1846    // so we start from [GAIdx+2]
1847    for (i = GAIdx + 2; i < MI->getNumOperands(); ++i)
1848      tmpOpnds.push_back(MI->getOperand(i));
1849
1850    // Remove all operands in range [ (GAIdx+1) ... (MI->getNumOperands()-1) ]
1851    // It is very important that we always remove from the end of Operands[]
1852    // MI->getNumOperands() is at least 2 if program goes to here.
1853    for (i = MI->getNumOperands() - 1; i > GAIdx; --i)
1854      MI->RemoveOperand(i);
1855
1856    for (i = 0; i < tmpOpnds.size(); ++i)
1857      MI->addOperand(tmpOpnds[i]);
1858  }
1859
1860  return true;
1861}
1862
1863
1864bool
1865HexagonInstrInfo::
1866isProfitableToIfCvt(MachineBasicBlock &MBB,
1867                    unsigned NumCycles,
1868                    unsigned ExtraPredCycles,
1869                    const BranchProbability &Probability) const {
1870  return true;
1871}
1872
1873
1874bool
1875HexagonInstrInfo::
1876isProfitableToIfCvt(MachineBasicBlock &TMBB,
1877                    unsigned NumTCycles,
1878                    unsigned ExtraTCycles,
1879                    MachineBasicBlock &FMBB,
1880                    unsigned NumFCycles,
1881                    unsigned ExtraFCycles,
1882                    const BranchProbability &Probability) const {
1883  return true;
1884}
1885
1886
1887bool HexagonInstrInfo::isPredicated(const MachineInstr *MI) const {
1888  const uint64_t F = MI->getDesc().TSFlags;
1889
1890  return ((F >> HexagonII::PredicatedPos) & HexagonII::PredicatedMask);
1891}
1892
1893bool HexagonInstrInfo::isPredicatedNew(const MachineInstr *MI) const {
1894  const uint64_t F = MI->getDesc().TSFlags;
1895
1896  assert(isPredicated(MI));
1897  return ((F >> HexagonII::PredicatedNewPos) & HexagonII::PredicatedNewMask);
1898}
1899
1900bool
1901HexagonInstrInfo::DefinesPredicate(MachineInstr *MI,
1902                                   std::vector<MachineOperand> &Pred) const {
1903  for (unsigned oper = 0; oper < MI->getNumOperands(); ++oper) {
1904    MachineOperand MO = MI->getOperand(oper);
1905    if (MO.isReg() && MO.isDef()) {
1906      const TargetRegisterClass* RC = RI.getMinimalPhysRegClass(MO.getReg());
1907      if (RC == &Hexagon::PredRegsRegClass) {
1908        Pred.push_back(MO);
1909        return true;
1910      }
1911    }
1912  }
1913  return false;
1914}
1915
1916
1917bool
1918HexagonInstrInfo::
1919SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
1920                  const SmallVectorImpl<MachineOperand> &Pred2) const {
1921  // TODO: Fix this
1922  return false;
1923}
1924
1925
1926//
1927// We indicate that we want to reverse the branch by
1928// inserting a 0 at the beginning of the Cond vector.
1929//
1930bool HexagonInstrInfo::
1931ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
1932  if (!Cond.empty() && Cond[0].isImm() && Cond[0].getImm() == 0) {
1933    Cond.erase(Cond.begin());
1934  } else {
1935    Cond.insert(Cond.begin(), MachineOperand::CreateImm(0));
1936  }
1937  return false;
1938}
1939
1940
1941bool HexagonInstrInfo::
1942isProfitableToDupForIfCvt(MachineBasicBlock &MBB,unsigned NumInstrs,
1943                          const BranchProbability &Probability) const {
1944  return (NumInstrs <= 4);
1945}
1946
1947bool HexagonInstrInfo::isDeallocRet(const MachineInstr *MI) const {
1948  switch (MI->getOpcode()) {
1949  default: return false;
1950  case Hexagon::DEALLOC_RET_V4 :
1951  case Hexagon::DEALLOC_RET_cPt_V4 :
1952  case Hexagon::DEALLOC_RET_cNotPt_V4 :
1953  case Hexagon::DEALLOC_RET_cdnPnt_V4 :
1954  case Hexagon::DEALLOC_RET_cNotdnPnt_V4 :
1955  case Hexagon::DEALLOC_RET_cdnPt_V4 :
1956  case Hexagon::DEALLOC_RET_cNotdnPt_V4 :
1957   return true;
1958  }
1959}
1960
1961
1962bool HexagonInstrInfo::
1963isValidOffset(const int Opcode, const int Offset) const {
1964  // This function is to check whether the "Offset" is in the correct range of
1965  // the given "Opcode". If "Offset" is not in the correct range, "ADD_ri" is
1966  // inserted to calculate the final address. Due to this reason, the function
1967  // assumes that the "Offset" has correct alignment.
1968  // We used to assert if the offset was not properly aligned, however,
1969  // there are cases where a misaligned pointer recast can cause this
1970  // problem, and we need to allow for it. The front end warns of such
1971  // misaligns with respect to load size.
1972
1973  switch(Opcode) {
1974
1975  case Hexagon::LDriw:
1976  case Hexagon::LDriw_indexed:
1977  case Hexagon::LDriw_f:
1978  case Hexagon::STriw_indexed:
1979  case Hexagon::STriw:
1980  case Hexagon::STriw_f:
1981    return (Offset >= Hexagon_MEMW_OFFSET_MIN) &&
1982      (Offset <= Hexagon_MEMW_OFFSET_MAX);
1983
1984  case Hexagon::LDrid:
1985  case Hexagon::LDrid_indexed:
1986  case Hexagon::LDrid_f:
1987  case Hexagon::STrid:
1988  case Hexagon::STrid_indexed:
1989  case Hexagon::STrid_f:
1990    return (Offset >= Hexagon_MEMD_OFFSET_MIN) &&
1991      (Offset <= Hexagon_MEMD_OFFSET_MAX);
1992
1993  case Hexagon::LDrih:
1994  case Hexagon::LDriuh:
1995  case Hexagon::STrih:
1996    return (Offset >= Hexagon_MEMH_OFFSET_MIN) &&
1997      (Offset <= Hexagon_MEMH_OFFSET_MAX);
1998
1999  case Hexagon::LDrib:
2000  case Hexagon::STrib:
2001  case Hexagon::LDriub:
2002    return (Offset >= Hexagon_MEMB_OFFSET_MIN) &&
2003      (Offset <= Hexagon_MEMB_OFFSET_MAX);
2004
2005  case Hexagon::ADD_ri:
2006  case Hexagon::TFR_FI:
2007    return (Offset >= Hexagon_ADDI_OFFSET_MIN) &&
2008      (Offset <= Hexagon_ADDI_OFFSET_MAX);
2009
2010  case Hexagon::MemOPw_ADDi_V4 :
2011  case Hexagon::MemOPw_SUBi_V4 :
2012  case Hexagon::MemOPw_ADDr_V4 :
2013  case Hexagon::MemOPw_SUBr_V4 :
2014  case Hexagon::MemOPw_ANDr_V4 :
2015  case Hexagon::MemOPw_ORr_V4 :
2016    return (0 <= Offset && Offset <= 255);
2017
2018  case Hexagon::MemOPh_ADDi_V4 :
2019  case Hexagon::MemOPh_SUBi_V4 :
2020  case Hexagon::MemOPh_ADDr_V4 :
2021  case Hexagon::MemOPh_SUBr_V4 :
2022  case Hexagon::MemOPh_ANDr_V4 :
2023  case Hexagon::MemOPh_ORr_V4 :
2024    return (0 <= Offset && Offset <= 127);
2025
2026  case Hexagon::MemOPb_ADDi_V4 :
2027  case Hexagon::MemOPb_SUBi_V4 :
2028  case Hexagon::MemOPb_ADDr_V4 :
2029  case Hexagon::MemOPb_SUBr_V4 :
2030  case Hexagon::MemOPb_ANDr_V4 :
2031  case Hexagon::MemOPb_ORr_V4 :
2032    return (0 <= Offset && Offset <= 63);
2033
2034  // LDri_pred and STriw_pred are pseudo operations, so it has to take offset of
2035  // any size. Later pass knows how to handle it.
2036  case Hexagon::STriw_pred:
2037  case Hexagon::LDriw_pred:
2038    return true;
2039
2040  case Hexagon::LOOP0_i:
2041    return isUInt<10>(Offset);
2042
2043  // INLINEASM is very special.
2044  case Hexagon::INLINEASM:
2045    return true;
2046  }
2047
2048  llvm_unreachable("No offset range is defined for this opcode. "
2049                   "Please define it in the above switch statement!");
2050}
2051
2052
2053//
2054// Check if the Offset is a valid auto-inc imm by Load/Store Type.
2055//
2056bool HexagonInstrInfo::
2057isValidAutoIncImm(const EVT VT, const int Offset) const {
2058
2059  if (VT == MVT::i64) {
2060      return (Offset >= Hexagon_MEMD_AUTOINC_MIN &&
2061              Offset <= Hexagon_MEMD_AUTOINC_MAX &&
2062              (Offset & 0x7) == 0);
2063  }
2064  if (VT == MVT::i32) {
2065      return (Offset >= Hexagon_MEMW_AUTOINC_MIN &&
2066              Offset <= Hexagon_MEMW_AUTOINC_MAX &&
2067              (Offset & 0x3) == 0);
2068  }
2069  if (VT == MVT::i16) {
2070      return (Offset >= Hexagon_MEMH_AUTOINC_MIN &&
2071              Offset <= Hexagon_MEMH_AUTOINC_MAX &&
2072              (Offset & 0x1) == 0);
2073  }
2074  if (VT == MVT::i8) {
2075      return (Offset >= Hexagon_MEMB_AUTOINC_MIN &&
2076              Offset <= Hexagon_MEMB_AUTOINC_MAX);
2077  }
2078  llvm_unreachable("Not an auto-inc opc!");
2079}
2080
2081
2082bool HexagonInstrInfo::
2083isMemOp(const MachineInstr *MI) const {
2084  switch (MI->getOpcode())
2085  {
2086    default: return false;
2087    case Hexagon::MemOPw_ADDi_V4 :
2088    case Hexagon::MemOPw_SUBi_V4 :
2089    case Hexagon::MemOPw_ADDr_V4 :
2090    case Hexagon::MemOPw_SUBr_V4 :
2091    case Hexagon::MemOPw_ANDr_V4 :
2092    case Hexagon::MemOPw_ORr_V4 :
2093    case Hexagon::MemOPh_ADDi_V4 :
2094    case Hexagon::MemOPh_SUBi_V4 :
2095    case Hexagon::MemOPh_ADDr_V4 :
2096    case Hexagon::MemOPh_SUBr_V4 :
2097    case Hexagon::MemOPh_ANDr_V4 :
2098    case Hexagon::MemOPh_ORr_V4 :
2099    case Hexagon::MemOPb_ADDi_V4 :
2100    case Hexagon::MemOPb_SUBi_V4 :
2101    case Hexagon::MemOPb_ADDr_V4 :
2102    case Hexagon::MemOPb_SUBr_V4 :
2103    case Hexagon::MemOPb_ANDr_V4 :
2104    case Hexagon::MemOPb_ORr_V4 :
2105    case Hexagon::MemOPb_SETBITi_V4:
2106    case Hexagon::MemOPh_SETBITi_V4:
2107    case Hexagon::MemOPw_SETBITi_V4:
2108    case Hexagon::MemOPb_CLRBITi_V4:
2109    case Hexagon::MemOPh_CLRBITi_V4:
2110    case Hexagon::MemOPw_CLRBITi_V4:
2111    return true;
2112  }
2113  return false;
2114}
2115
2116
2117bool HexagonInstrInfo::
2118isSpillPredRegOp(const MachineInstr *MI) const {
2119  switch (MI->getOpcode()) {
2120    default: return false;
2121    case Hexagon::STriw_pred :
2122    case Hexagon::LDriw_pred :
2123      return true;
2124  }
2125}
2126
2127bool HexagonInstrInfo::isNewValueJumpCandidate(const MachineInstr *MI) const {
2128  switch (MI->getOpcode()) {
2129    default: return false;
2130    case Hexagon::CMPEQrr:
2131    case Hexagon::CMPEQri:
2132    case Hexagon::CMPLTrr:
2133    case Hexagon::CMPGTrr:
2134    case Hexagon::CMPGTri:
2135    case Hexagon::CMPLTUrr:
2136    case Hexagon::CMPGTUrr:
2137    case Hexagon::CMPGTUri:
2138    case Hexagon::CMPGEri:
2139    case Hexagon::CMPGEUri:
2140      return true;
2141  }
2142}
2143
2144bool HexagonInstrInfo::
2145isConditionalTransfer (const MachineInstr *MI) const {
2146  switch (MI->getOpcode()) {
2147    default: return false;
2148    case Hexagon::TFR_cPt:
2149    case Hexagon::TFR_cNotPt:
2150    case Hexagon::TFRI_cPt:
2151    case Hexagon::TFRI_cNotPt:
2152    case Hexagon::TFR_cdnPt:
2153    case Hexagon::TFR_cdnNotPt:
2154    case Hexagon::TFRI_cdnPt:
2155    case Hexagon::TFRI_cdnNotPt:
2156      return true;
2157  }
2158}
2159
2160bool HexagonInstrInfo::isConditionalALU32 (const MachineInstr* MI) const {
2161  const HexagonRegisterInfo& QRI = getRegisterInfo();
2162  switch (MI->getOpcode())
2163  {
2164    default: return false;
2165    case Hexagon::ADD_ri_cPt:
2166    case Hexagon::ADD_ri_cNotPt:
2167    case Hexagon::ADD_rr_cPt:
2168    case Hexagon::ADD_rr_cNotPt:
2169    case Hexagon::XOR_rr_cPt:
2170    case Hexagon::XOR_rr_cNotPt:
2171    case Hexagon::AND_rr_cPt:
2172    case Hexagon::AND_rr_cNotPt:
2173    case Hexagon::OR_rr_cPt:
2174    case Hexagon::OR_rr_cNotPt:
2175    case Hexagon::SUB_rr_cPt:
2176    case Hexagon::SUB_rr_cNotPt:
2177    case Hexagon::COMBINE_rr_cPt:
2178    case Hexagon::COMBINE_rr_cNotPt:
2179      return true;
2180    case Hexagon::ASLH_cPt_V4:
2181    case Hexagon::ASLH_cNotPt_V4:
2182    case Hexagon::ASRH_cPt_V4:
2183    case Hexagon::ASRH_cNotPt_V4:
2184    case Hexagon::SXTB_cPt_V4:
2185    case Hexagon::SXTB_cNotPt_V4:
2186    case Hexagon::SXTH_cPt_V4:
2187    case Hexagon::SXTH_cNotPt_V4:
2188    case Hexagon::ZXTB_cPt_V4:
2189    case Hexagon::ZXTB_cNotPt_V4:
2190    case Hexagon::ZXTH_cPt_V4:
2191    case Hexagon::ZXTH_cNotPt_V4:
2192      return QRI.Subtarget.hasV4TOps();
2193  }
2194}
2195
2196bool HexagonInstrInfo::
2197isConditionalLoad (const MachineInstr* MI) const {
2198  const HexagonRegisterInfo& QRI = getRegisterInfo();
2199  switch (MI->getOpcode())
2200  {
2201    default: return false;
2202    case Hexagon::LDrid_cPt :
2203    case Hexagon::LDrid_cNotPt :
2204    case Hexagon::LDrid_indexed_cPt :
2205    case Hexagon::LDrid_indexed_cNotPt :
2206    case Hexagon::LDriw_cPt :
2207    case Hexagon::LDriw_cNotPt :
2208    case Hexagon::LDriw_indexed_cPt :
2209    case Hexagon::LDriw_indexed_cNotPt :
2210    case Hexagon::LDrih_cPt :
2211    case Hexagon::LDrih_cNotPt :
2212    case Hexagon::LDrih_indexed_cPt :
2213    case Hexagon::LDrih_indexed_cNotPt :
2214    case Hexagon::LDrib_cPt :
2215    case Hexagon::LDrib_cNotPt :
2216    case Hexagon::LDrib_indexed_cPt :
2217    case Hexagon::LDrib_indexed_cNotPt :
2218    case Hexagon::LDriuh_cPt :
2219    case Hexagon::LDriuh_cNotPt :
2220    case Hexagon::LDriuh_indexed_cPt :
2221    case Hexagon::LDriuh_indexed_cNotPt :
2222    case Hexagon::LDriub_cPt :
2223    case Hexagon::LDriub_cNotPt :
2224    case Hexagon::LDriub_indexed_cPt :
2225    case Hexagon::LDriub_indexed_cNotPt :
2226      return true;
2227    case Hexagon::POST_LDrid_cPt :
2228    case Hexagon::POST_LDrid_cNotPt :
2229    case Hexagon::POST_LDriw_cPt :
2230    case Hexagon::POST_LDriw_cNotPt :
2231    case Hexagon::POST_LDrih_cPt :
2232    case Hexagon::POST_LDrih_cNotPt :
2233    case Hexagon::POST_LDrib_cPt :
2234    case Hexagon::POST_LDrib_cNotPt :
2235    case Hexagon::POST_LDriuh_cPt :
2236    case Hexagon::POST_LDriuh_cNotPt :
2237    case Hexagon::POST_LDriub_cPt :
2238    case Hexagon::POST_LDriub_cNotPt :
2239      return QRI.Subtarget.hasV4TOps();
2240    case Hexagon::LDrid_indexed_shl_cPt_V4 :
2241    case Hexagon::LDrid_indexed_shl_cNotPt_V4 :
2242    case Hexagon::LDrib_indexed_shl_cPt_V4 :
2243    case Hexagon::LDrib_indexed_shl_cNotPt_V4 :
2244    case Hexagon::LDriub_indexed_shl_cPt_V4 :
2245    case Hexagon::LDriub_indexed_shl_cNotPt_V4 :
2246    case Hexagon::LDrih_indexed_shl_cPt_V4 :
2247    case Hexagon::LDrih_indexed_shl_cNotPt_V4 :
2248    case Hexagon::LDriuh_indexed_shl_cPt_V4 :
2249    case Hexagon::LDriuh_indexed_shl_cNotPt_V4 :
2250    case Hexagon::LDriw_indexed_shl_cPt_V4 :
2251    case Hexagon::LDriw_indexed_shl_cNotPt_V4 :
2252      return QRI.Subtarget.hasV4TOps();
2253  }
2254}
2255
2256// Returns true if an instruction is a conditional store.
2257//
2258// Note: It doesn't include conditional new-value stores as they can't be
2259// converted to .new predicate.
2260//
2261//               p.new NV store [ if(p0.new)memw(R0+#0)=R2.new ]
2262//                ^           ^
2263//               /             \ (not OK. it will cause new-value store to be
2264//              /               X conditional on p0.new while R2 producer is
2265//             /                 \ on p0)
2266//            /                   \.
2267//     p.new store                 p.old NV store
2268// [if(p0.new)memw(R0+#0)=R2]    [if(p0)memw(R0+#0)=R2.new]
2269//            ^                  ^
2270//             \                /
2271//              \              /
2272//               \            /
2273//                 p.old store
2274//             [if (p0)memw(R0+#0)=R2]
2275//
2276// The above diagram shows the steps involoved in the conversion of a predicated
2277// store instruction to its .new predicated new-value form.
2278//
2279// The following set of instructions further explains the scenario where
2280// conditional new-value store becomes invalid when promoted to .new predicate
2281// form.
2282//
2283// { 1) if (p0) r0 = add(r1, r2)
2284//   2) p0 = cmp.eq(r3, #0) }
2285//
2286//   3) if (p0) memb(r1+#0) = r0  --> this instruction can't be grouped with
2287// the first two instructions because in instr 1, r0 is conditional on old value
2288// of p0 but its use in instr 3 is conditional on p0 modified by instr 2 which
2289// is not valid for new-value stores.
2290bool HexagonInstrInfo::
2291isConditionalStore (const MachineInstr* MI) const {
2292  const HexagonRegisterInfo& QRI = getRegisterInfo();
2293  switch (MI->getOpcode())
2294  {
2295    default: return false;
2296    case Hexagon::STrib_imm_cPt_V4 :
2297    case Hexagon::STrib_imm_cNotPt_V4 :
2298    case Hexagon::STrib_indexed_shl_cPt_V4 :
2299    case Hexagon::STrib_indexed_shl_cNotPt_V4 :
2300    case Hexagon::STrib_cPt :
2301    case Hexagon::STrib_cNotPt :
2302    case Hexagon::POST_STbri_cPt :
2303    case Hexagon::POST_STbri_cNotPt :
2304    case Hexagon::STrid_indexed_cPt :
2305    case Hexagon::STrid_indexed_cNotPt :
2306    case Hexagon::STrid_indexed_shl_cPt_V4 :
2307    case Hexagon::POST_STdri_cPt :
2308    case Hexagon::POST_STdri_cNotPt :
2309    case Hexagon::STrih_cPt :
2310    case Hexagon::STrih_cNotPt :
2311    case Hexagon::STrih_indexed_cPt :
2312    case Hexagon::STrih_indexed_cNotPt :
2313    case Hexagon::STrih_imm_cPt_V4 :
2314    case Hexagon::STrih_imm_cNotPt_V4 :
2315    case Hexagon::STrih_indexed_shl_cPt_V4 :
2316    case Hexagon::STrih_indexed_shl_cNotPt_V4 :
2317    case Hexagon::POST_SThri_cPt :
2318    case Hexagon::POST_SThri_cNotPt :
2319    case Hexagon::STriw_cPt :
2320    case Hexagon::STriw_cNotPt :
2321    case Hexagon::STriw_indexed_cPt :
2322    case Hexagon::STriw_indexed_cNotPt :
2323    case Hexagon::STriw_imm_cPt_V4 :
2324    case Hexagon::STriw_imm_cNotPt_V4 :
2325    case Hexagon::STriw_indexed_shl_cPt_V4 :
2326    case Hexagon::STriw_indexed_shl_cNotPt_V4 :
2327    case Hexagon::POST_STwri_cPt :
2328    case Hexagon::POST_STwri_cNotPt :
2329      return QRI.Subtarget.hasV4TOps();
2330
2331    // V4 global address store before promoting to dot new.
2332    case Hexagon::STd_GP_cPt_V4 :
2333    case Hexagon::STd_GP_cNotPt_V4 :
2334    case Hexagon::STb_GP_cPt_V4 :
2335    case Hexagon::STb_GP_cNotPt_V4 :
2336    case Hexagon::STh_GP_cPt_V4 :
2337    case Hexagon::STh_GP_cNotPt_V4 :
2338    case Hexagon::STw_GP_cPt_V4 :
2339    case Hexagon::STw_GP_cNotPt_V4 :
2340      return QRI.Subtarget.hasV4TOps();
2341
2342    // Predicated new value stores (i.e. if (p0) memw(..)=r0.new) are excluded
2343    // from the "Conditional Store" list. Because a predicated new value store
2344    // would NOT be promoted to a double dot new store. See diagram below:
2345    // This function returns yes for those stores that are predicated but not
2346    // yet promoted to predicate dot new instructions.
2347    //
2348    //                          +---------------------+
2349    //                    /-----| if (p0) memw(..)=r0 |---------\~
2350    //                   ||     +---------------------+         ||
2351    //          promote  ||       /\       /\                   ||  promote
2352    //                   ||      /||\     /||\                  ||
2353    //                  \||/    demote     ||                  \||/
2354    //                   \/       ||       ||                   \/
2355    //       +-------------------------+   ||   +-------------------------+
2356    //       | if (p0.new) memw(..)=r0 |   ||   | if (p0) memw(..)=r0.new |
2357    //       +-------------------------+   ||   +-------------------------+
2358    //                        ||           ||         ||
2359    //                        ||         demote      \||/
2360    //                      promote        ||         \/ NOT possible
2361    //                        ||           ||         /\~
2362    //                       \||/          ||        /||\~
2363    //                        \/           ||         ||
2364    //                      +-----------------------------+
2365    //                      | if (p0.new) memw(..)=r0.new |
2366    //                      +-----------------------------+
2367    //                           Double Dot New Store
2368    //
2369  }
2370}
2371
2372// Returns true, if any one of the operands is a dot new
2373// insn, whether it is predicated dot new or register dot new.
2374bool HexagonInstrInfo::isDotNewInst (const MachineInstr* MI) const {
2375  return (isNewValueInst(MI) ||
2376     (isPredicated(MI) && isPredicatedNew(MI)));
2377}
2378
2379unsigned HexagonInstrInfo::getAddrMode(const MachineInstr* MI) const {
2380  const uint64_t F = MI->getDesc().TSFlags;
2381
2382  return((F >> HexagonII::AddrModePos) & HexagonII::AddrModeMask);
2383}
2384
2385/// immediateExtend - Changes the instruction in place to one using an immediate
2386/// extender.
2387void HexagonInstrInfo::immediateExtend(MachineInstr *MI) const {
2388  assert((isExtendable(MI)||isConstExtended(MI)) &&
2389                               "Instruction must be extendable");
2390  // Find which operand is extendable.
2391  short ExtOpNum = getCExtOpNum(MI);
2392  MachineOperand &MO = MI->getOperand(ExtOpNum);
2393  // This needs to be something we understand.
2394  assert((MO.isMBB() || MO.isImm()) &&
2395         "Branch with unknown extendable field type");
2396  // Mark given operand as extended.
2397  MO.addTargetFlag(HexagonII::HMOTF_ConstExtended);
2398}
2399
2400DFAPacketizer *HexagonInstrInfo::
2401CreateTargetScheduleState(const TargetMachine *TM,
2402                           const ScheduleDAG *DAG) const {
2403  const InstrItineraryData *II = TM->getInstrItineraryData();
2404  return TM->getSubtarget<HexagonGenSubtargetInfo>().createDFAPacketizer(II);
2405}
2406
2407bool HexagonInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
2408                                            const MachineBasicBlock *MBB,
2409                                            const MachineFunction &MF) const {
2410  // Debug info is never a scheduling boundary. It's necessary to be explicit
2411  // due to the special treatment of IT instructions below, otherwise a
2412  // dbg_value followed by an IT will result in the IT instruction being
2413  // considered a scheduling hazard, which is wrong. It should be the actual
2414  // instruction preceding the dbg_value instruction(s), just like it is
2415  // when debug info is not present.
2416  if (MI->isDebugValue())
2417    return false;
2418
2419  // Terminators and labels can't be scheduled around.
2420  if (MI->getDesc().isTerminator() || MI->isLabel() || MI->isInlineAsm())
2421    return true;
2422
2423  return false;
2424}
2425
2426bool HexagonInstrInfo::isConstExtended(MachineInstr *MI) const {
2427
2428  // Constant extenders are allowed only for V4 and above.
2429  if (!Subtarget.hasV4TOps())
2430    return false;
2431
2432  const uint64_t F = MI->getDesc().TSFlags;
2433  unsigned isExtended = (F >> HexagonII::ExtendedPos) & HexagonII::ExtendedMask;
2434  if (isExtended) // Instruction must be extended.
2435    return true;
2436
2437  unsigned isExtendable = (F >> HexagonII::ExtendablePos)
2438                          & HexagonII::ExtendableMask;
2439  if (!isExtendable)
2440    return false;
2441
2442  short ExtOpNum = getCExtOpNum(MI);
2443  const MachineOperand &MO = MI->getOperand(ExtOpNum);
2444  // Use MO operand flags to determine if MO
2445  // has the HMOTF_ConstExtended flag set.
2446  if (MO.getTargetFlags() && HexagonII::HMOTF_ConstExtended)
2447    return true;
2448  // If this is a Machine BB address we are talking about, and it is
2449  // not marked as extended, say so.
2450  if (MO.isMBB())
2451    return false;
2452
2453  // We could be using an instruction with an extendable immediate and shoehorn
2454  // a global address into it. If it is a global address it will be constant
2455  // extended. We do this for COMBINE.
2456  // We currently only handle isGlobal() because it is the only kind of
2457  // object we are going to end up with here for now.
2458  // In the future we probably should add isSymbol(), etc.
2459  if (MO.isGlobal() || MO.isSymbol())
2460    return true;
2461
2462  // If the extendable operand is not 'Immediate' type, the instruction should
2463  // have 'isExtended' flag set.
2464  assert(MO.isImm() && "Extendable operand must be Immediate type");
2465
2466  int MinValue = getMinValue(MI);
2467  int MaxValue = getMaxValue(MI);
2468  int ImmValue = MO.getImm();
2469
2470  return (ImmValue < MinValue || ImmValue > MaxValue);
2471}
2472
2473// Returns true if a particular operand is extendable for an instruction.
2474bool HexagonInstrInfo::isOperandExtended(const MachineInstr *MI,
2475                                         unsigned short OperandNum) const {
2476  // Constant extenders are allowed only for V4 and above.
2477  if (!Subtarget.hasV4TOps())
2478    return false;
2479
2480  const uint64_t F = MI->getDesc().TSFlags;
2481
2482  return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask)
2483          == OperandNum;
2484}
2485
2486// Returns Operand Index for the constant extended instruction.
2487unsigned short HexagonInstrInfo::getCExtOpNum(const MachineInstr *MI) const {
2488  const uint64_t F = MI->getDesc().TSFlags;
2489  return ((F >> HexagonII::ExtendableOpPos) & HexagonII::ExtendableOpMask);
2490}
2491
2492// Returns the min value that doesn't need to be extended.
2493int HexagonInstrInfo::getMinValue(const MachineInstr *MI) const {
2494  const uint64_t F = MI->getDesc().TSFlags;
2495  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
2496                    & HexagonII::ExtentSignedMask;
2497  unsigned bits =  (F >> HexagonII::ExtentBitsPos)
2498                    & HexagonII::ExtentBitsMask;
2499
2500  if (isSigned) // if value is signed
2501    return -1 << (bits - 1);
2502  else
2503    return 0;
2504}
2505
2506// Returns the max value that doesn't need to be extended.
2507int HexagonInstrInfo::getMaxValue(const MachineInstr *MI) const {
2508  const uint64_t F = MI->getDesc().TSFlags;
2509  unsigned isSigned = (F >> HexagonII::ExtentSignedPos)
2510                    & HexagonII::ExtentSignedMask;
2511  unsigned bits =  (F >> HexagonII::ExtentBitsPos)
2512                    & HexagonII::ExtentBitsMask;
2513
2514  if (isSigned) // if value is signed
2515    return ~(-1 << (bits - 1));
2516  else
2517    return ~(-1 << bits);
2518}
2519
2520// Returns true if an instruction can be converted into a non-extended
2521// equivalent instruction.
2522bool HexagonInstrInfo::NonExtEquivalentExists (const MachineInstr *MI) const {
2523
2524  short NonExtOpcode;
2525  // Check if the instruction has a register form that uses register in place
2526  // of the extended operand, if so return that as the non-extended form.
2527  if (Hexagon::getRegForm(MI->getOpcode()) >= 0)
2528    return true;
2529
2530  if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2531    // Check addressing mode and retreive non-ext equivalent instruction.
2532
2533    switch (getAddrMode(MI)) {
2534    case HexagonII::Absolute :
2535      // Load/store with absolute addressing mode can be converted into
2536      // base+offset mode.
2537      NonExtOpcode = Hexagon::getBasedWithImmOffset(MI->getOpcode());
2538      break;
2539    case HexagonII::BaseImmOffset :
2540      // Load/store with base+offset addressing mode can be converted into
2541      // base+register offset addressing mode. However left shift operand should
2542      // be set to 0.
2543      NonExtOpcode = Hexagon::getBaseWithRegOffset(MI->getOpcode());
2544      break;
2545    default:
2546      return false;
2547    }
2548    if (NonExtOpcode < 0)
2549      return false;
2550    return true;
2551  }
2552  return false;
2553}
2554
2555// Returns opcode of the non-extended equivalent instruction.
2556short HexagonInstrInfo::getNonExtOpcode (const MachineInstr *MI) const {
2557
2558  // Check if the instruction has a register form that uses register in place
2559  // of the extended operand, if so return that as the non-extended form.
2560  short NonExtOpcode = Hexagon::getRegForm(MI->getOpcode());
2561    if (NonExtOpcode >= 0)
2562      return NonExtOpcode;
2563
2564  if (MI->getDesc().mayLoad() || MI->getDesc().mayStore()) {
2565    // Check addressing mode and retreive non-ext equivalent instruction.
2566    switch (getAddrMode(MI)) {
2567    case HexagonII::Absolute :
2568      return Hexagon::getBasedWithImmOffset(MI->getOpcode());
2569    case HexagonII::BaseImmOffset :
2570      return Hexagon::getBaseWithRegOffset(MI->getOpcode());
2571    default:
2572      return -1;
2573    }
2574  }
2575  return -1;
2576}
2577