HexagonExpandPredSpillCode.cpp revision 251662
1234285Sdim//===-- HexagonExpandPredSpillCode.cpp - Expand Predicate Spill Code ------===// 2234285Sdim// 3234285Sdim// The LLVM Compiler Infrastructure 4234285Sdim// 5234285Sdim// This file is distributed under the University of Illinois Open Source 6234285Sdim// License. See LICENSE.TXT for details. 7234285Sdim// 8234285Sdim//===----------------------------------------------------------------------===// 9234285Sdim// The Hexagon processor has no instructions that load or store predicate 10239462Sdim// registers directly. So, when these registers must be spilled a general 11239462Sdim// purpose register must be found and the value copied to/from it from/to 12239462Sdim// the predicate register. This code currently does not use the register 13234285Sdim// scavenger mechanism available in the allocator. There are two registers 14234285Sdim// reserved to allow spilling/restoring predicate registers. One is used to 15234285Sdim// hold the predicate value. The other is used when stack frame offsets are 16234285Sdim// too large. 17234285Sdim// 18234285Sdim//===----------------------------------------------------------------------===// 19234285Sdim 20249423Sdim#include "Hexagon.h" 21249423Sdim#include "HexagonMachineFunctionInfo.h" 22249423Sdim#include "HexagonSubtarget.h" 23234285Sdim#include "HexagonTargetMachine.h" 24234285Sdim#include "llvm/ADT/Statistic.h" 25234285Sdim#include "llvm/CodeGen/LatencyPriorityQueue.h" 26234285Sdim#include "llvm/CodeGen/MachineDominators.h" 27234285Sdim#include "llvm/CodeGen/MachineFunctionPass.h" 28234285Sdim#include "llvm/CodeGen/MachineInstrBuilder.h" 29234285Sdim#include "llvm/CodeGen/MachineLoopInfo.h" 30234285Sdim#include "llvm/CodeGen/MachineRegisterInfo.h" 31234285Sdim#include "llvm/CodeGen/Passes.h" 32234285Sdim#include "llvm/CodeGen/ScheduleHazardRecognizer.h" 33234285Sdim#include "llvm/CodeGen/SchedulerRegistry.h" 34234285Sdim#include "llvm/Support/Compiler.h" 35234285Sdim#include "llvm/Support/Debug.h" 36234285Sdim#include "llvm/Support/MathExtras.h" 37249423Sdim#include "llvm/Target/TargetInstrInfo.h" 38249423Sdim#include "llvm/Target/TargetMachine.h" 39249423Sdim#include "llvm/Target/TargetRegisterInfo.h" 40234285Sdim 41234285Sdimusing namespace llvm; 42234285Sdim 43234285Sdim 44251662Sdimnamespace llvm { 45251662Sdim void initializeHexagonExpandPredSpillCodePass(PassRegistry&); 46251662Sdim} 47251662Sdim 48251662Sdim 49234285Sdimnamespace { 50234285Sdim 51234285Sdimclass HexagonExpandPredSpillCode : public MachineFunctionPass { 52251662Sdim const HexagonTargetMachine& QTM; 53234285Sdim const HexagonSubtarget &QST; 54234285Sdim 55234285Sdim public: 56234285Sdim static char ID; 57251662Sdim HexagonExpandPredSpillCode(const HexagonTargetMachine& TM) : 58251662Sdim MachineFunctionPass(ID), QTM(TM), QST(*TM.getSubtargetImpl()) { 59251662Sdim PassRegistry &Registry = *PassRegistry::getPassRegistry(); 60251662Sdim initializeHexagonExpandPredSpillCodePass(Registry); 61251662Sdim } 62234285Sdim 63234285Sdim const char *getPassName() const { 64234285Sdim return "Hexagon Expand Predicate Spill Code"; 65234285Sdim } 66234285Sdim bool runOnMachineFunction(MachineFunction &Fn); 67234285Sdim}; 68234285Sdim 69234285Sdim 70234285Sdimchar HexagonExpandPredSpillCode::ID = 0; 71234285Sdim 72234285Sdim 73234285Sdimbool HexagonExpandPredSpillCode::runOnMachineFunction(MachineFunction &Fn) { 74234285Sdim 75234285Sdim const HexagonInstrInfo *TII = QTM.getInstrInfo(); 76234285Sdim 77234285Sdim // Loop over all of the basic blocks. 78234285Sdim for (MachineFunction::iterator MBBb = Fn.begin(), MBBe = Fn.end(); 79234285Sdim MBBb != MBBe; ++MBBb) { 80234285Sdim MachineBasicBlock* MBB = MBBb; 81234285Sdim // Traverse the basic block. 82234285Sdim for (MachineBasicBlock::iterator MII = MBB->begin(); MII != MBB->end(); 83234285Sdim ++MII) { 84234285Sdim MachineInstr *MI = MII; 85234285Sdim int Opc = MI->getOpcode(); 86234285Sdim if (Opc == Hexagon::STriw_pred) { 87234285Sdim // STriw_pred [R30], ofst, SrcReg; 88234285Sdim unsigned FP = MI->getOperand(0).getReg(); 89234285Sdim assert(FP == QTM.getRegisterInfo()->getFrameRegister() && 90234285Sdim "Not a Frame Pointer, Nor a Spill Slot"); 91234285Sdim assert(MI->getOperand(1).isImm() && "Not an offset"); 92234285Sdim int Offset = MI->getOperand(1).getImm(); 93234285Sdim int SrcReg = MI->getOperand(2).getReg(); 94234285Sdim assert(Hexagon::PredRegsRegClass.contains(SrcReg) && 95234285Sdim "Not a predicate register"); 96239462Sdim if (!TII->isValidOffset(Hexagon::STriw_indexed, Offset)) { 97234285Sdim if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) { 98234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), 99234285Sdim TII->get(Hexagon::CONST32_Int_Real), 100234285Sdim HEXAGON_RESERVED_REG_1).addImm(Offset); 101234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr), 102234285Sdim HEXAGON_RESERVED_REG_1) 103234285Sdim .addReg(FP).addReg(HEXAGON_RESERVED_REG_1); 104234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), 105234285Sdim HEXAGON_RESERVED_REG_2).addReg(SrcReg); 106234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), 107239462Sdim TII->get(Hexagon::STriw_indexed)) 108234285Sdim .addReg(HEXAGON_RESERVED_REG_1) 109234285Sdim .addImm(0).addReg(HEXAGON_RESERVED_REG_2); 110234285Sdim } else { 111234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri), 112234285Sdim HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); 113234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), 114234285Sdim HEXAGON_RESERVED_REG_2).addReg(SrcReg); 115239462Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), 116239462Sdim TII->get(Hexagon::STriw_indexed)) 117234285Sdim .addReg(HEXAGON_RESERVED_REG_1) 118234285Sdim .addImm(0) 119234285Sdim .addReg(HEXAGON_RESERVED_REG_2); 120234285Sdim } 121234285Sdim } else { 122234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_RsPd), 123234285Sdim HEXAGON_RESERVED_REG_2).addReg(SrcReg); 124239462Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), 125239462Sdim TII->get(Hexagon::STriw_indexed)). 126234285Sdim addReg(FP).addImm(Offset).addReg(HEXAGON_RESERVED_REG_2); 127234285Sdim } 128234285Sdim MII = MBB->erase(MI); 129234285Sdim --MII; 130234285Sdim } else if (Opc == Hexagon::LDriw_pred) { 131234285Sdim // DstReg = LDriw_pred [R30], ofst. 132234285Sdim int DstReg = MI->getOperand(0).getReg(); 133234285Sdim assert(Hexagon::PredRegsRegClass.contains(DstReg) && 134234285Sdim "Not a predicate register"); 135234285Sdim unsigned FP = MI->getOperand(1).getReg(); 136234285Sdim assert(FP == QTM.getRegisterInfo()->getFrameRegister() && 137234285Sdim "Not a Frame Pointer, Nor a Spill Slot"); 138234285Sdim assert(MI->getOperand(2).isImm() && "Not an offset"); 139234285Sdim int Offset = MI->getOperand(2).getImm(); 140234285Sdim if (!TII->isValidOffset(Hexagon::LDriw, Offset)) { 141234285Sdim if (!TII->isValidOffset(Hexagon::ADD_ri, Offset)) { 142234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), 143234285Sdim TII->get(Hexagon::CONST32_Int_Real), 144234285Sdim HEXAGON_RESERVED_REG_1).addImm(Offset); 145234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_rr), 146234285Sdim HEXAGON_RESERVED_REG_1) 147234285Sdim .addReg(FP) 148234285Sdim .addReg(HEXAGON_RESERVED_REG_1); 149234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw), 150234285Sdim HEXAGON_RESERVED_REG_2) 151234285Sdim .addReg(HEXAGON_RESERVED_REG_1) 152234285Sdim .addImm(0); 153234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs), 154234285Sdim DstReg).addReg(HEXAGON_RESERVED_REG_2); 155234285Sdim } else { 156234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::ADD_ri), 157234285Sdim HEXAGON_RESERVED_REG_1).addReg(FP).addImm(Offset); 158234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw), 159234285Sdim HEXAGON_RESERVED_REG_2) 160234285Sdim .addReg(HEXAGON_RESERVED_REG_1) 161234285Sdim .addImm(0); 162234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs), 163234285Sdim DstReg).addReg(HEXAGON_RESERVED_REG_2); 164234285Sdim } 165234285Sdim } else { 166234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::LDriw), 167234285Sdim HEXAGON_RESERVED_REG_2).addReg(FP).addImm(Offset); 168234285Sdim BuildMI(*MBB, MII, MI->getDebugLoc(), TII->get(Hexagon::TFR_PdRs), 169234285Sdim DstReg).addReg(HEXAGON_RESERVED_REG_2); 170234285Sdim } 171234285Sdim MII = MBB->erase(MI); 172234285Sdim --MII; 173234285Sdim } 174234285Sdim } 175234285Sdim } 176234285Sdim 177234285Sdim return true; 178234285Sdim} 179234285Sdim 180234285Sdim} 181234285Sdim 182234285Sdim//===----------------------------------------------------------------------===// 183234285Sdim// Public Constructor Functions 184234285Sdim//===----------------------------------------------------------------------===// 185234285Sdim 186251662Sdimstatic void initializePassOnce(PassRegistry &Registry) { 187251662Sdim const char *Name = "Hexagon Expand Predicate Spill Code"; 188251662Sdim PassInfo *PI = new PassInfo(Name, "hexagon-spill-pred", 189251662Sdim &HexagonExpandPredSpillCode::ID, 190251662Sdim 0, false, false); 191251662Sdim Registry.registerPass(*PI, true); 192251662Sdim} 193251662Sdim 194251662Sdimvoid llvm::initializeHexagonExpandPredSpillCodePass(PassRegistry &Registry) { 195251662Sdim CALL_ONCE_INITIALIZATION(initializePassOnce) 196251662Sdim} 197251662Sdim 198251662SdimFunctionPass* 199251662Sdimllvm::createHexagonExpandPredSpillCode(const HexagonTargetMachine &TM) { 200234285Sdim return new HexagonExpandPredSpillCode(TM); 201234285Sdim} 202