ARMTargetMachine.h revision 224145 
1//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetMachine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMTARGETMACHINE_H
15#define ARMTARGETMACHINE_H
16
17#include "ARMInstrInfo.h"
18#include "ARMELFWriterInfo.h"
19#include "ARMFrameLowering.h"
20#include "ARMJITInfo.h"
21#include "ARMSubtarget.h"
22#include "ARMISelLowering.h"
23#include "ARMSelectionDAGInfo.h"
24#include "Thumb1InstrInfo.h"
25#include "Thumb1FrameLowering.h"
26#include "Thumb2InstrInfo.h"
27#include "llvm/Target/TargetMachine.h"
28#include "llvm/Target/TargetData.h"
29#include "llvm/MC/MCStreamer.h"
30#include "llvm/ADT/OwningPtr.h"
31
32namespace llvm {
33
34class ARMBaseTargetMachine : public LLVMTargetMachine {
35protected:
36  ARMSubtarget        Subtarget;
37private:
38  ARMJITInfo          JITInfo;
39  InstrItineraryData  InstrItins;
40  Reloc::Model        DefRelocModel;    // Reloc model before it's overridden.
41
42public:
43  ARMBaseTargetMachine(const Target &T, const std::string &TT,
44                       const std::string &CPU, const std::string &FS);
45
46  virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
47  virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
48  virtual const InstrItineraryData *getInstrItineraryData() const {
49    return &InstrItins;
50  }
51
52  // Pass Pipeline Configuration
53  virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55  virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
56  virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
57  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
58  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
59                              JITCodeEmitter &MCE);
60};
61
62/// ARMTargetMachine - ARM target machine.
63///
64class ARMTargetMachine : public ARMBaseTargetMachine {
65  ARMInstrInfo        InstrInfo;
66  const TargetData    DataLayout;       // Calculates type size & alignment
67  ARMELFWriterInfo    ELFWriterInfo;
68  ARMTargetLowering   TLInfo;
69  ARMSelectionDAGInfo TSInfo;
70  ARMFrameLowering    FrameLowering;
71 public:
72  ARMTargetMachine(const Target &T, const std::string &TT,
73                   const std::string &CPU, const std::string &FS);
74
75  virtual const ARMRegisterInfo  *getRegisterInfo() const {
76    return &InstrInfo.getRegisterInfo();
77  }
78
79  virtual const ARMTargetLowering *getTargetLowering() const {
80    return &TLInfo;
81  }
82
83  virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
84    return &TSInfo;
85  }
86  virtual const ARMFrameLowering *getFrameLowering() const {
87    return &FrameLowering;
88  }
89
90  virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
91  virtual const TargetData       *getTargetData() const { return &DataLayout; }
92  virtual const ARMELFWriterInfo *getELFWriterInfo() const {
93    return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
94  }
95};
96
97/// ThumbTargetMachine - Thumb target machine.
98/// Due to the way architectures are handled, this represents both
99///   Thumb-1 and Thumb-2.
100///
101class ThumbTargetMachine : public ARMBaseTargetMachine {
102  // Either Thumb1InstrInfo or Thumb2InstrInfo.
103  OwningPtr<ARMBaseInstrInfo> InstrInfo;
104  const TargetData    DataLayout;   // Calculates type size & alignment
105  ARMELFWriterInfo    ELFWriterInfo;
106  ARMTargetLowering   TLInfo;
107  ARMSelectionDAGInfo TSInfo;
108  // Either Thumb1FrameLowering or ARMFrameLowering.
109  OwningPtr<ARMFrameLowering> FrameLowering;
110public:
111  ThumbTargetMachine(const Target &T, const std::string &TT,
112                     const std::string &CPU, const std::string &FS);
113
114  /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
115  virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
116    return &InstrInfo->getRegisterInfo();
117  }
118
119  virtual const ARMTargetLowering *getTargetLowering() const {
120    return &TLInfo;
121  }
122
123  virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
124    return &TSInfo;
125  }
126
127  /// returns either Thumb1InstrInfo or Thumb2InstrInfo
128  virtual const ARMBaseInstrInfo *getInstrInfo() const {
129    return InstrInfo.get();
130  }
131  /// returns either Thumb1FrameLowering or ARMFrameLowering
132  virtual const ARMFrameLowering *getFrameLowering() const {
133    return FrameLowering.get();
134  }
135  virtual const TargetData       *getTargetData() const { return &DataLayout; }
136  virtual const ARMELFWriterInfo *getELFWriterInfo() const {
137    return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
138  }
139};
140
141} // end namespace llvm
142
143#endif
144