ARMTargetMachine.h revision 212904 
1//===-- ARMTargetMachine.h - Define TargetMachine for ARM -------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetMachine.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMTARGETMACHINE_H
15#define ARMTARGETMACHINE_H
16
17#include "llvm/Target/TargetMachine.h"
18#include "llvm/Target/TargetData.h"
19#include "ARMInstrInfo.h"
20#include "ARMFrameInfo.h"
21#include "ARMJITInfo.h"
22#include "ARMSubtarget.h"
23#include "ARMISelLowering.h"
24#include "ARMSelectionDAGInfo.h"
25#include "Thumb1InstrInfo.h"
26#include "Thumb2InstrInfo.h"
27#include "llvm/ADT/OwningPtr.h"
28
29namespace llvm {
30
31class ARMBaseTargetMachine : public LLVMTargetMachine {
32protected:
33  ARMSubtarget        Subtarget;
34
35private:
36  ARMFrameInfo        FrameInfo;
37  ARMJITInfo          JITInfo;
38  InstrItineraryData  InstrItins;
39  Reloc::Model        DefRelocModel;    // Reloc model before it's overridden.
40
41public:
42  ARMBaseTargetMachine(const Target &T, const std::string &TT,
43                       const std::string &FS, bool isThumb);
44
45  virtual const ARMFrameInfo     *getFrameInfo() const { return &FrameInfo; }
46  virtual       ARMJITInfo       *getJITInfo()         { return &JITInfo; }
47  virtual const ARMSubtarget  *getSubtargetImpl() const { return &Subtarget; }
48  virtual const InstrItineraryData getInstrItineraryData() const {
49    return InstrItins;
50  }
51
52  // Pass Pipeline Configuration
53  virtual bool addPreISel(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
54  virtual bool addInstSelector(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
55  virtual bool addPreRegAlloc(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
56  virtual bool addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
57  virtual bool addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel);
58  virtual bool addCodeEmitter(PassManagerBase &PM, CodeGenOpt::Level OptLevel,
59                              JITCodeEmitter &MCE);
60};
61
62/// ARMTargetMachine - ARM target machine.
63///
64class ARMTargetMachine : public ARMBaseTargetMachine {
65  ARMInstrInfo        InstrInfo;
66  const TargetData    DataLayout;       // Calculates type size & alignment
67  ARMTargetLowering   TLInfo;
68  ARMSelectionDAGInfo TSInfo;
69public:
70  ARMTargetMachine(const Target &T, const std::string &TT,
71                   const std::string &FS);
72
73  virtual const ARMRegisterInfo  *getRegisterInfo() const {
74    return &InstrInfo.getRegisterInfo();
75  }
76
77  virtual const ARMTargetLowering *getTargetLowering() const {
78    return &TLInfo;
79  }
80
81  virtual const ARMSelectionDAGInfo* getSelectionDAGInfo() const {
82    return &TSInfo;
83  }
84
85  virtual const ARMInstrInfo     *getInstrInfo() const { return &InstrInfo; }
86  virtual const TargetData       *getTargetData() const { return &DataLayout; }
87};
88
89/// ThumbTargetMachine - Thumb target machine.
90/// Due to the way architectures are handled, this represents both
91///   Thumb-1 and Thumb-2.
92///
93class ThumbTargetMachine : public ARMBaseTargetMachine {
94  // Either Thumb1InstrInfo or Thumb2InstrInfo.
95  OwningPtr<ARMBaseInstrInfo> InstrInfo;
96  const TargetData    DataLayout;   // Calculates type size & alignment
97  ARMTargetLowering   TLInfo;
98  ARMSelectionDAGInfo TSInfo;
99public:
100  ThumbTargetMachine(const Target &T, const std::string &TT,
101                     const std::string &FS);
102
103  /// returns either Thumb1RegisterInfo or Thumb2RegisterInfo
104  virtual const ARMBaseRegisterInfo *getRegisterInfo() const {
105    return &InstrInfo->getRegisterInfo();
106  }
107
108  virtual const ARMTargetLowering *getTargetLowering() const {
109    return &TLInfo;
110  }
111
112  virtual const ARMSelectionDAGInfo *getSelectionDAGInfo() const {
113    return &TSInfo;
114  }
115
116  /// returns either Thumb1InstrInfo or Thumb2InstrInfo
117  virtual const ARMBaseInstrInfo *getInstrInfo() const {
118    return InstrInfo.get();
119  }
120  virtual const TargetData       *getTargetData() const { return &DataLayout; }
121};
122
123} // end namespace llvm
124
125#endif
126