ARMSubtarget.h revision 251662
1//===-- ARMSubtarget.h - Define Subtarget for the ARM ----------*- C++ -*--===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file declares the ARM specific subclass of TargetSubtargetInfo. 11// 12//===----------------------------------------------------------------------===// 13 14#ifndef ARMSUBTARGET_H 15#define ARMSUBTARGET_H 16 17#include "MCTargetDesc/ARMMCTargetDesc.h" 18#include "llvm/ADT/Triple.h" 19#include "llvm/MC/MCInstrItineraries.h" 20#include "llvm/Target/TargetSubtargetInfo.h" 21#include <string> 22 23#define GET_SUBTARGETINFO_HEADER 24#include "ARMGenSubtargetInfo.inc" 25 26namespace llvm { 27class GlobalValue; 28class StringRef; 29class TargetOptions; 30 31class ARMSubtarget : public ARMGenSubtargetInfo { 32protected: 33 enum ARMProcFamilyEnum { 34 Others, CortexA5, CortexA8, CortexA9, CortexA15, CortexR5, Swift 35 }; 36 37 /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others. 38 ARMProcFamilyEnum ARMProcFamily; 39 40 /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops - 41 /// Specify whether target support specific ARM ISA variants. 42 bool HasV4TOps; 43 bool HasV5TOps; 44 bool HasV5TEOps; 45 bool HasV6Ops; 46 bool HasV6T2Ops; 47 bool HasV7Ops; 48 49 /// HasVFPv2, HasVFPv3, HasVFPv4, HasNEON - Specify what 50 /// floating point ISAs are supported. 51 bool HasVFPv2; 52 bool HasVFPv3; 53 bool HasVFPv4; 54 bool HasNEON; 55 56 /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 57 /// specified. Use the method useNEONForSinglePrecisionFP() to 58 /// determine if NEON should actually be used. 59 bool UseNEONForSinglePrecisionFP; 60 61 /// UseMulOps - True if non-microcoded fused integer multiply-add and 62 /// multiply-subtract instructions should be used. 63 bool UseMulOps; 64 65 /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates 66 /// whether the FP VML[AS] instructions are slow (if so, don't use them). 67 bool SlowFPVMLx; 68 69 /// HasVMLxForwarding - If true, NEON has special multiplier accumulator 70 /// forwarding to allow mul + mla being issued back to back. 71 bool HasVMLxForwarding; 72 73 /// SlowFPBrcc - True if floating point compare + branch is slow. 74 bool SlowFPBrcc; 75 76 /// InThumbMode - True if compiling for Thumb, false for ARM. 77 bool InThumbMode; 78 79 /// HasThumb2 - True if Thumb2 instructions are supported. 80 bool HasThumb2; 81 82 /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs - 83 /// v6m, v7m for example. 84 bool IsMClass; 85 86 /// NoARM - True if subtarget does not support ARM mode execution. 87 bool NoARM; 88 89 /// PostRAScheduler - True if using post-register-allocation scheduler. 90 bool PostRAScheduler; 91 92 /// IsR9Reserved - True if R9 is a not available as general purpose register. 93 bool IsR9Reserved; 94 95 /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit 96 /// imms (including global addresses). 97 bool UseMovt; 98 99 /// SupportsTailCall - True if the OS supports tail call. The dynamic linker 100 /// must be able to synthesize call stubs for interworking between ARM and 101 /// Thumb. 102 bool SupportsTailCall; 103 104 /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF 105 /// only so far) 106 bool HasFP16; 107 108 /// HasD16 - True if subtarget is limited to 16 double precision 109 /// FP registers for VFPv3. 110 bool HasD16; 111 112 /// HasHardwareDivide - True if subtarget supports [su]div 113 bool HasHardwareDivide; 114 115 /// HasHardwareDivideInARM - True if subtarget supports [su]div in ARM mode 116 bool HasHardwareDivideInARM; 117 118 /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack 119 /// instructions. 120 bool HasT2ExtractPack; 121 122 /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier 123 /// instructions. 124 bool HasDataBarrier; 125 126 /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions 127 /// over 16-bit ones. 128 bool Pref32BitThumb; 129 130 /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions 131 /// that partially update CPSR and add false dependency on the previous 132 /// CPSR setting instruction. 133 bool AvoidCPSRPartialUpdate; 134 135 /// AvoidMOVsShifterOperand - If true, codegen should avoid using flag setting 136 /// movs with shifter operand (i.e. asr, lsl, lsr). 137 bool AvoidMOVsShifterOperand; 138 139 /// HasRAS - Some processors perform return stack prediction. CodeGen should 140 /// avoid issue "normal" call instructions to callees which do not return. 141 bool HasRAS; 142 143 /// HasMPExtension - True if the subtarget supports Multiprocessing 144 /// extension (ARMv7 only). 145 bool HasMPExtension; 146 147 /// FPOnlySP - If true, the floating point unit only supports single 148 /// precision. 149 bool FPOnlySP; 150 151 /// HasTrustZone - if true, processor supports TrustZone security extensions 152 bool HasTrustZone; 153 154 /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory 155 /// accesses for some types. For details, see 156 /// ARMTargetLowering::allowsUnalignedMemoryAccesses(). 157 bool AllowsUnalignedMem; 158 159 /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith 160 /// and such) instructions in Thumb2 code. 161 bool Thumb2DSP; 162 163 /// NaCl TRAP instruction is generated instead of the regular TRAP. 164 bool UseNaClTrap; 165 166 /// Target machine allowed unsafe FP math (such as use of NEON fp) 167 bool UnsafeFPMath; 168 169 /// stackAlignment - The minimum alignment known to hold of the stack frame on 170 /// entry to the function and which must be maintained by every function. 171 unsigned stackAlignment; 172 173 /// CPUString - String name of used CPU. 174 std::string CPUString; 175 176 /// TargetTriple - What processor and OS we're targeting. 177 Triple TargetTriple; 178 179 /// SchedModel - Processor specific instruction costs. 180 const MCSchedModel *SchedModel; 181 182 /// Selected instruction itineraries (one entry per itinerary class.) 183 InstrItineraryData InstrItins; 184 185 /// Options passed via command line that could influence the target 186 const TargetOptions &Options; 187 188 public: 189 enum { 190 isELF, isDarwin 191 } TargetType; 192 193 enum { 194 ARM_ABI_APCS, 195 ARM_ABI_AAPCS // ARM EABI 196 } TargetABI; 197 198 /// This constructor initializes the data members to match that 199 /// of the specified triple. 200 /// 201 ARMSubtarget(const std::string &TT, const std::string &CPU, 202 const std::string &FS, const TargetOptions &Options); 203 204 /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 205 /// that still makes it profitable to inline the call. 206 unsigned getMaxInlineSizeThreshold() const { 207 // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1. 208 // Change this once Thumb1 ldmia / stmia support is added. 209 return isThumb1Only() ? 0 : 64; 210 } 211 /// ParseSubtargetFeatures - Parses features string setting specified 212 /// subtarget options. Definition of function is auto generated by tblgen. 213 void ParseSubtargetFeatures(StringRef CPU, StringRef FS); 214 215 /// \brief Reset the features for the ARM target. 216 virtual void resetSubtargetFeatures(const MachineFunction *MF); 217private: 218 void initializeEnvironment(); 219 void resetSubtargetFeatures(StringRef CPU, StringRef FS); 220public: 221 void computeIssueWidth(); 222 223 bool hasV4TOps() const { return HasV4TOps; } 224 bool hasV5TOps() const { return HasV5TOps; } 225 bool hasV5TEOps() const { return HasV5TEOps; } 226 bool hasV6Ops() const { return HasV6Ops; } 227 bool hasV6T2Ops() const { return HasV6T2Ops; } 228 bool hasV7Ops() const { return HasV7Ops; } 229 230 bool isCortexA5() const { return ARMProcFamily == CortexA5; } 231 bool isCortexA8() const { return ARMProcFamily == CortexA8; } 232 bool isCortexA9() const { return ARMProcFamily == CortexA9; } 233 bool isCortexA15() const { return ARMProcFamily == CortexA15; } 234 bool isSwift() const { return ARMProcFamily == Swift; } 235 bool isCortexM3() const { return CPUString == "cortex-m3"; } 236 bool isLikeA9() const { return isCortexA9() || isCortexA15(); } 237 bool isCortexR5() const { return ARMProcFamily == CortexR5; } 238 239 bool hasARMOps() const { return !NoARM; } 240 241 bool hasVFP2() const { return HasVFPv2; } 242 bool hasVFP3() const { return HasVFPv3; } 243 bool hasVFP4() const { return HasVFPv4; } 244 bool hasNEON() const { return HasNEON; } 245 bool useNEONForSinglePrecisionFP() const { 246 return hasNEON() && UseNEONForSinglePrecisionFP; } 247 248 bool hasDivide() const { return HasHardwareDivide; } 249 bool hasDivideInARMMode() const { return HasHardwareDivideInARM; } 250 bool hasT2ExtractPack() const { return HasT2ExtractPack; } 251 bool hasDataBarrier() const { return HasDataBarrier; } 252 bool useMulOps() const { return UseMulOps; } 253 bool useFPVMLx() const { return !SlowFPVMLx; } 254 bool hasVMLxForwarding() const { return HasVMLxForwarding; } 255 bool isFPBrccSlow() const { return SlowFPBrcc; } 256 bool isFPOnlySP() const { return FPOnlySP; } 257 bool hasTrustZone() const { return HasTrustZone; } 258 bool prefers32BitThumb() const { return Pref32BitThumb; } 259 bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; } 260 bool avoidMOVsShifterOperand() const { return AvoidMOVsShifterOperand; } 261 bool hasRAS() const { return HasRAS; } 262 bool hasMPExtension() const { return HasMPExtension; } 263 bool hasThumb2DSP() const { return Thumb2DSP; } 264 bool useNaClTrap() const { return UseNaClTrap; } 265 266 bool hasFP16() const { return HasFP16; } 267 bool hasD16() const { return HasD16; } 268 269 const Triple &getTargetTriple() const { return TargetTriple; } 270 271 bool isTargetIOS() const { return TargetTriple.getOS() == Triple::IOS; } 272 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 273 bool isTargetNaCl() const { 274 return TargetTriple.getOS() == Triple::NaCl; 275 } 276 bool isTargetELF() const { return !isTargetDarwin(); } 277 278 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } 279 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } 280 281 bool isThumb() const { return InThumbMode; } 282 bool isThumb1Only() const { return InThumbMode && !HasThumb2; } 283 bool isThumb2() const { return InThumbMode && HasThumb2; } 284 bool hasThumb2() const { return HasThumb2; } 285 bool isMClass() const { return IsMClass; } 286 bool isARClass() const { return !IsMClass; } 287 288 bool isR9Reserved() const { return IsR9Reserved; } 289 290 bool useMovt() const { return UseMovt && hasV6T2Ops(); } 291 bool supportsTailCall() const { return SupportsTailCall; } 292 293 bool allowsUnalignedMem() const { return AllowsUnalignedMem; } 294 295 const std::string & getCPUString() const { return CPUString; } 296 297 unsigned getMispredictionPenalty() const; 298 299 /// enablePostRAScheduler - True at 'More' optimization. 300 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 301 TargetSubtargetInfo::AntiDepBreakMode& Mode, 302 RegClassVector& CriticalPathRCs) const; 303 304 /// getInstrItins - Return the instruction itineraies based on subtarget 305 /// selection. 306 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 307 308 /// getStackAlignment - Returns the minimum alignment known to hold of the 309 /// stack frame on entry to the function and which must be maintained by every 310 /// function for this subtarget. 311 unsigned getStackAlignment() const { return stackAlignment; } 312 313 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect 314 /// symbol. 315 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const; 316}; 317} // End llvm namespace 318 319#endif // ARMSUBTARGET_H 320