ARMSubtarget.h revision 226633 
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtargetInfo.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "MCTargetDesc/ARMMCTargetDesc.h"
18#include "llvm/Target/TargetSubtargetInfo.h"
19#include "llvm/MC/MCInstrItineraries.h"
20#include "llvm/ADT/Triple.h"
21#include <string>
22
23#define GET_SUBTARGETINFO_HEADER
24#include "ARMGenSubtargetInfo.inc"
25
26namespace llvm {
27class GlobalValue;
28class StringRef;
29
30class ARMSubtarget : public ARMGenSubtargetInfo {
31protected:
32  enum ARMProcFamilyEnum {
33    Others, CortexA8, CortexA9
34  };
35
36  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
37  ARMProcFamilyEnum ARMProcFamily;
38
39  /// HasV4TOps, HasV5TOps, HasV5TEOps, HasV6Ops, HasV6T2Ops, HasV7Ops -
40  /// Specify whether target support specific ARM ISA variants.
41  bool HasV4TOps;
42  bool HasV5TOps;
43  bool HasV5TEOps;
44  bool HasV6Ops;
45  bool HasV6T2Ops;
46  bool HasV7Ops;
47
48  /// HasVFPv2, HasVFPv3, HasNEON - Specify what floating point ISAs are
49  /// supported.
50  bool HasVFPv2;
51  bool HasVFPv3;
52  bool HasNEON;
53
54  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
55  /// specified. Use the method useNEONForSinglePrecisionFP() to
56  /// determine if NEON should actually be used.
57  bool UseNEONForSinglePrecisionFP;
58
59  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
60  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
61  bool SlowFPVMLx;
62
63  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
64  /// forwarding to allow mul + mla being issued back to back.
65  bool HasVMLxForwarding;
66
67  /// SlowFPBrcc - True if floating point compare + branch is slow.
68  bool SlowFPBrcc;
69
70  /// InThumbMode - True if compiling for Thumb, false for ARM.
71  bool InThumbMode;
72
73  /// InNaClMode - True if targeting Native Client
74  bool InNaClMode;
75
76  /// HasThumb2 - True if Thumb2 instructions are supported.
77  bool HasThumb2;
78
79  /// IsMClass - True if the subtarget belongs to the 'M' profile of CPUs -
80  /// v6m, v7m for example.
81  bool IsMClass;
82
83  /// NoARM - True if subtarget does not support ARM mode execution.
84  bool NoARM;
85
86  /// PostRAScheduler - True if using post-register-allocation scheduler.
87  bool PostRAScheduler;
88
89  /// IsR9Reserved - True if R9 is a not available as general purpose register.
90  bool IsR9Reserved;
91
92  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
93  /// imms (including global addresses).
94  bool UseMovt;
95
96  /// SupportsTailCall - True if the OS supports tail call. The dynamic linker
97  /// must be able to synthesize call stubs for interworking between ARM and
98  /// Thumb.
99  bool SupportsTailCall;
100
101  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
102  /// only so far)
103  bool HasFP16;
104
105  /// HasD16 - True if subtarget is limited to 16 double precision
106  /// FP registers for VFPv3.
107  bool HasD16;
108
109  /// HasHardwareDivide - True if subtarget supports [su]div
110  bool HasHardwareDivide;
111
112  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
113  /// instructions.
114  bool HasT2ExtractPack;
115
116  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
117  /// instructions.
118  bool HasDataBarrier;
119
120  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
121  /// over 16-bit ones.
122  bool Pref32BitThumb;
123
124  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
125  /// that partially update CPSR and add false dependency on the previous
126  /// CPSR setting instruction.
127  bool AvoidCPSRPartialUpdate;
128
129  /// HasMPExtension - True if the subtarget supports Multiprocessing
130  /// extension (ARMv7 only).
131  bool HasMPExtension;
132
133  /// FPOnlySP - If true, the floating point unit only supports single
134  /// precision.
135  bool FPOnlySP;
136
137  /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
138  /// accesses for some types.  For details, see
139  /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
140  bool AllowsUnalignedMem;
141
142  /// Thumb2DSP - If true, the subtarget supports the v7 DSP (saturating arith
143  /// and such) instructions in Thumb2 code.
144  bool Thumb2DSP;
145
146  /// stackAlignment - The minimum alignment known to hold of the stack frame on
147  /// entry to the function and which must be maintained by every function.
148  unsigned stackAlignment;
149
150  /// CPUString - String name of used CPU.
151  std::string CPUString;
152
153  /// TargetTriple - What processor and OS we're targeting.
154  Triple TargetTriple;
155
156  /// Selected instruction itineraries (one entry per itinerary class.)
157  InstrItineraryData InstrItins;
158
159 public:
160  enum {
161    isELF, isDarwin
162  } TargetType;
163
164  enum {
165    ARM_ABI_APCS,
166    ARM_ABI_AAPCS // ARM EABI
167  } TargetABI;
168
169  /// This constructor initializes the data members to match that
170  /// of the specified triple.
171  ///
172  ARMSubtarget(const std::string &TT, const std::string &CPU,
173               const std::string &FS);
174
175  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
176  /// that still makes it profitable to inline the call.
177  unsigned getMaxInlineSizeThreshold() const {
178    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
179    // Change this once Thumb1 ldmia / stmia support is added.
180    return isThumb1Only() ? 0 : 64;
181  }
182  /// ParseSubtargetFeatures - Parses features string setting specified
183  /// subtarget options.  Definition of function is auto generated by tblgen.
184  void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
185
186  void computeIssueWidth();
187
188  bool hasV4TOps()  const { return HasV4TOps;  }
189  bool hasV5TOps()  const { return HasV5TOps;  }
190  bool hasV5TEOps() const { return HasV5TEOps; }
191  bool hasV6Ops()   const { return HasV6Ops;   }
192  bool hasV6T2Ops() const { return HasV6T2Ops; }
193  bool hasV7Ops()   const { return HasV7Ops;  }
194
195  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
196  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
197
198  bool hasARMOps() const { return !NoARM; }
199
200  bool hasVFP2() const { return HasVFPv2; }
201  bool hasVFP3() const { return HasVFPv3; }
202  bool hasNEON() const { return HasNEON;  }
203  bool useNEONForSinglePrecisionFP() const {
204    return hasNEON() && UseNEONForSinglePrecisionFP; }
205
206  bool hasDivide() const { return HasHardwareDivide; }
207  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
208  bool hasDataBarrier() const { return HasDataBarrier; }
209  bool useFPVMLx() const { return !SlowFPVMLx; }
210  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
211  bool isFPBrccSlow() const { return SlowFPBrcc; }
212  bool isFPOnlySP() const { return FPOnlySP; }
213  bool prefers32BitThumb() const { return Pref32BitThumb; }
214  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
215  bool hasMPExtension() const { return HasMPExtension; }
216  bool hasThumb2DSP() const { return Thumb2DSP; }
217
218  bool hasFP16() const { return HasFP16; }
219  bool hasD16() const { return HasD16; }
220
221  const Triple &getTargetTriple() const { return TargetTriple; }
222
223  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
224  bool isTargetNaCl() const {
225    return TargetTriple.getOS() == Triple::NativeClient;
226  }
227  bool isTargetELF() const { return !isTargetDarwin(); }
228
229  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
230  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
231
232  bool isThumb() const { return InThumbMode; }
233  bool isThumb1Only() const { return InThumbMode && !HasThumb2; }
234  bool isThumb2() const { return InThumbMode && HasThumb2; }
235  bool hasThumb2() const { return HasThumb2; }
236  bool isMClass() const { return IsMClass; }
237  bool isARClass() const { return !IsMClass; }
238
239  bool isR9Reserved() const { return IsR9Reserved; }
240
241  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
242  bool supportsTailCall() const { return SupportsTailCall; }
243
244  bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
245
246  const std::string & getCPUString() const { return CPUString; }
247
248  unsigned getMispredictionPenalty() const;
249
250  /// enablePostRAScheduler - True at 'More' optimization.
251  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
252                             TargetSubtargetInfo::AntiDepBreakMode& Mode,
253                             RegClassVector& CriticalPathRCs) const;
254
255  /// getInstrItins - Return the instruction itineraies based on subtarget
256  /// selection.
257  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
258
259  /// getStackAlignment - Returns the minimum alignment known to hold of the
260  /// stack frame on entry to the function and which must be maintained by every
261  /// function for this subtarget.
262  unsigned getStackAlignment() const { return stackAlignment; }
263
264  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
265  /// symbol.
266  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
267};
268} // End llvm namespace
269
270#endif  // ARMSUBTARGET_H
271