ARMSubtarget.h revision 221345 
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "llvm/Target/TargetInstrItineraries.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetSubtarget.h"
20#include "llvm/ADT/Triple.h"
21#include <string>
22
23namespace llvm {
24class GlobalValue;
25
26class ARMSubtarget : public TargetSubtarget {
27protected:
28  enum ARMArchEnum {
29    V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
30  };
31
32  enum ARMProcFamilyEnum {
33    Others, CortexA8, CortexA9
34  };
35
36  enum ARMFPEnum {
37    None, VFPv2, VFPv3, NEON
38  };
39
40  enum ThumbTypeEnum {
41    Thumb1,
42    Thumb2
43  };
44
45  /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
46  /// V6, V6T2, V7A, V7M.
47  ARMArchEnum ARMArchVersion;
48
49  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
50  ARMProcFamilyEnum ARMProcFamily;
51
52  /// ARMFPUType - Floating Point Unit type.
53  ARMFPEnum ARMFPUType;
54
55  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
56  /// specified. Use the method useNEONForSinglePrecisionFP() to
57  /// determine if NEON should actually be used.
58  bool UseNEONForSinglePrecisionFP;
59
60  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
61  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
62  bool SlowFPVMLx;
63
64  /// HasVMLxForwarding - If true, NEON has special multiplier accumulator
65  /// forwarding to allow mul + mla being issued back to back.
66  bool HasVMLxForwarding;
67
68  /// SlowFPBrcc - True if floating point compare + branch is slow.
69  bool SlowFPBrcc;
70
71  /// IsThumb - True if we are in thumb mode, false if in ARM mode.
72  bool IsThumb;
73
74  /// ThumbMode - Indicates supported Thumb version.
75  ThumbTypeEnum ThumbMode;
76
77  /// NoARM - True if subtarget does not support ARM mode execution.
78  bool NoARM;
79
80  /// PostRAScheduler - True if using post-register-allocation scheduler.
81  bool PostRAScheduler;
82
83  /// IsR9Reserved - True if R9 is a not available as general purpose register.
84  bool IsR9Reserved;
85
86  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
87  /// imms (including global addresses).
88  bool UseMovt;
89
90  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
91  /// only so far)
92  bool HasFP16;
93
94  /// HasD16 - True if subtarget is limited to 16 double precision
95  /// FP registers for VFPv3.
96  bool HasD16;
97
98  /// HasHardwareDivide - True if subtarget supports [su]div
99  bool HasHardwareDivide;
100
101  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
102  /// instructions.
103  bool HasT2ExtractPack;
104
105  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
106  /// instructions.
107  bool HasDataBarrier;
108
109  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
110  /// over 16-bit ones.
111  bool Pref32BitThumb;
112
113  /// AvoidCPSRPartialUpdate - If true, codegen would avoid using instructions
114  /// that partially update CPSR and add false dependency on the previous
115  /// CPSR setting instruction.
116  bool AvoidCPSRPartialUpdate;
117
118  /// HasMPExtension - True if the subtarget supports Multiprocessing
119  /// extension (ARMv7 only).
120  bool HasMPExtension;
121
122  /// FPOnlySP - If true, the floating point unit only supports single
123  /// precision.
124  bool FPOnlySP;
125
126  /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
127  /// accesses for some types.  For details, see
128  /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
129  bool AllowsUnalignedMem;
130
131  /// stackAlignment - The minimum alignment known to hold of the stack frame on
132  /// entry to the function and which must be maintained by every function.
133  unsigned stackAlignment;
134
135  /// CPUString - String name of used CPU.
136  std::string CPUString;
137
138  /// TargetTriple - What processor and OS we're targeting.
139  Triple TargetTriple;
140
141  /// Selected instruction itineraries (one entry per itinerary class.)
142  InstrItineraryData InstrItins;
143
144 public:
145  enum {
146    isELF, isDarwin
147  } TargetType;
148
149  enum {
150    ARM_ABI_APCS,
151    ARM_ABI_AAPCS // ARM EABI
152  } TargetABI;
153
154  /// This constructor initializes the data members to match that
155  /// of the specified triple.
156  ///
157  ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
158
159  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
160  /// that still makes it profitable to inline the call.
161  unsigned getMaxInlineSizeThreshold() const {
162    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
163    // Change this once Thumb1 ldmia / stmia support is added.
164    return isThumb1Only() ? 0 : 64;
165  }
166  /// ParseSubtargetFeatures - Parses features string setting specified
167  /// subtarget options.  Definition of function is auto generated by tblgen.
168  std::string ParseSubtargetFeatures(const std::string &FS,
169                                     const std::string &CPU);
170
171  void computeIssueWidth();
172
173  bool hasV4TOps()  const { return ARMArchVersion >= V4T;  }
174  bool hasV5TOps()  const { return ARMArchVersion >= V5T;  }
175  bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
176  bool hasV6Ops()   const { return ARMArchVersion >= V6;   }
177  bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
178  bool hasV7Ops()   const { return ARMArchVersion >= V7A;  }
179
180  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
181  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
182
183  bool hasARMOps() const { return !NoARM; }
184
185  bool hasVFP2() const { return ARMFPUType >= VFPv2; }
186  bool hasVFP3() const { return ARMFPUType >= VFPv3; }
187  bool hasNEON() const { return ARMFPUType >= NEON;  }
188  bool useNEONForSinglePrecisionFP() const {
189    return hasNEON() && UseNEONForSinglePrecisionFP; }
190  bool hasDivide() const { return HasHardwareDivide; }
191  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
192  bool hasDataBarrier() const { return HasDataBarrier; }
193  bool useFPVMLx() const { return !SlowFPVMLx; }
194  bool hasVMLxForwarding() const { return HasVMLxForwarding; }
195  bool isFPBrccSlow() const { return SlowFPBrcc; }
196  bool isFPOnlySP() const { return FPOnlySP; }
197  bool prefers32BitThumb() const { return Pref32BitThumb; }
198  bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
199  bool hasMPExtension() const { return HasMPExtension; }
200
201  bool hasFP16() const { return HasFP16; }
202  bool hasD16() const { return HasD16; }
203
204  const Triple &getTargetTriple() const { return TargetTriple; }
205
206  bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
207  bool isTargetELF() const { return !isTargetDarwin(); }
208
209  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
210  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
211
212  bool isThumb() const { return IsThumb; }
213  bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
214  bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
215  bool hasThumb2() const { return ThumbMode >= Thumb2; }
216
217  bool isR9Reserved() const { return IsR9Reserved; }
218
219  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
220
221  bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
222
223  const std::string & getCPUString() const { return CPUString; }
224
225  unsigned getMispredictionPenalty() const;
226
227  /// enablePostRAScheduler - True at 'More' optimization.
228  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
229                             TargetSubtarget::AntiDepBreakMode& Mode,
230                             RegClassVector& CriticalPathRCs) const;
231
232  /// getInstrItins - Return the instruction itineraies based on subtarget
233  /// selection.
234  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
235
236  /// getStackAlignment - Returns the minimum alignment known to hold of the
237  /// stack frame on entry to the function and which must be maintained by every
238  /// function for this subtarget.
239  unsigned getStackAlignment() const { return stackAlignment; }
240
241  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
242  /// symbol.
243  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
244};
245} // End llvm namespace
246
247#endif  // ARMSUBTARGET_H
248