ARMSubtarget.h revision 218893 
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "llvm/Target/TargetInstrItineraries.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetSubtarget.h"
20#include "llvm/ADT/Triple.h"
21#include <string>
22
23namespace llvm {
24class GlobalValue;
25
26class ARMSubtarget : public TargetSubtarget {
27protected:
28  enum ARMArchEnum {
29    V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
30  };
31
32  enum ARMProcFamilyEnum {
33    Others, CortexA8, CortexA9
34  };
35
36  enum ARMFPEnum {
37    None, VFPv2, VFPv3, NEON
38  };
39
40  enum ThumbTypeEnum {
41    Thumb1,
42    Thumb2
43  };
44
45  /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
46  /// V6, V6T2, V7A, V7M.
47  ARMArchEnum ARMArchVersion;
48
49  /// ARMProcFamily - ARM processor family: Cortex-A8, Cortex-A9, and others.
50  ARMProcFamilyEnum ARMProcFamily;
51
52  /// ARMFPUType - Floating Point Unit type.
53  ARMFPEnum ARMFPUType;
54
55  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
56  /// specified. Use the method useNEONForSinglePrecisionFP() to
57  /// determine if NEON should actually be used.
58  bool UseNEONForSinglePrecisionFP;
59
60  /// SlowFPVMLx - If the VFP2 / NEON instructions are available, indicates
61  /// whether the FP VML[AS] instructions are slow (if so, don't use them).
62  bool SlowFPVMLx;
63
64  /// SlowFPBrcc - True if floating point compare + branch is slow.
65  bool SlowFPBrcc;
66
67  /// IsThumb - True if we are in thumb mode, false if in ARM mode.
68  bool IsThumb;
69
70  /// ThumbMode - Indicates supported Thumb version.
71  ThumbTypeEnum ThumbMode;
72
73  /// NoARM - True if subtarget does not support ARM mode execution.
74  bool NoARM;
75
76  /// PostRAScheduler - True if using post-register-allocation scheduler.
77  bool PostRAScheduler;
78
79  /// IsR9Reserved - True if R9 is a not available as general purpose register.
80  bool IsR9Reserved;
81
82  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
83  /// imms (including global addresses).
84  bool UseMovt;
85
86  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
87  /// only so far)
88  bool HasFP16;
89
90  /// HasD16 - True if subtarget is limited to 16 double precision
91  /// FP registers for VFPv3.
92  bool HasD16;
93
94  /// HasHardwareDivide - True if subtarget supports [su]div
95  bool HasHardwareDivide;
96
97  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
98  /// instructions.
99  bool HasT2ExtractPack;
100
101  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
102  /// instructions.
103  bool HasDataBarrier;
104
105  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
106  /// over 16-bit ones.
107  bool Pref32BitThumb;
108
109  /// HasMPExtension - True if the subtarget supports Multiprocessing
110  /// extension (ARMv7 only).
111  bool HasMPExtension;
112
113  /// FPOnlySP - If true, the floating point unit only supports single
114  /// precision.
115  bool FPOnlySP;
116
117  /// AllowsUnalignedMem - If true, the subtarget allows unaligned memory
118  /// accesses for some types.  For details, see
119  /// ARMTargetLowering::allowsUnalignedMemoryAccesses().
120  bool AllowsUnalignedMem;
121
122  /// stackAlignment - The minimum alignment known to hold of the stack frame on
123  /// entry to the function and which must be maintained by every function.
124  unsigned stackAlignment;
125
126  /// CPUString - String name of used CPU.
127  std::string CPUString;
128
129  /// TargetTriple - What processor and OS we're targeting.
130  Triple TargetTriple;
131
132  /// Selected instruction itineraries (one entry per itinerary class.)
133  InstrItineraryData InstrItins;
134
135 public:
136  enum {
137    isELF, isDarwin
138  } TargetType;
139
140  enum {
141    ARM_ABI_APCS,
142    ARM_ABI_AAPCS // ARM EABI
143  } TargetABI;
144
145  /// This constructor initializes the data members to match that
146  /// of the specified triple.
147  ///
148  ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
149
150  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
151  /// that still makes it profitable to inline the call.
152  unsigned getMaxInlineSizeThreshold() const {
153    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
154    // Change this once Thumb1 ldmia / stmia support is added.
155    return isThumb1Only() ? 0 : 64;
156  }
157  /// ParseSubtargetFeatures - Parses features string setting specified
158  /// subtarget options.  Definition of function is auto generated by tblgen.
159  std::string ParseSubtargetFeatures(const std::string &FS,
160                                     const std::string &CPU);
161
162  void computeIssueWidth();
163
164  bool hasV4TOps()  const { return ARMArchVersion >= V4T;  }
165  bool hasV5TOps()  const { return ARMArchVersion >= V5T;  }
166  bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
167  bool hasV6Ops()   const { return ARMArchVersion >= V6;   }
168  bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
169  bool hasV7Ops()   const { return ARMArchVersion >= V7A;  }
170
171  bool isCortexA8() const { return ARMProcFamily == CortexA8; }
172  bool isCortexA9() const { return ARMProcFamily == CortexA9; }
173
174  bool hasARMOps() const { return !NoARM; }
175
176  bool hasVFP2() const { return ARMFPUType >= VFPv2; }
177  bool hasVFP3() const { return ARMFPUType >= VFPv3; }
178  bool hasNEON() const { return ARMFPUType >= NEON;  }
179  bool useNEONForSinglePrecisionFP() const {
180    return hasNEON() && UseNEONForSinglePrecisionFP; }
181  bool hasDivide() const { return HasHardwareDivide; }
182  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
183  bool hasDataBarrier() const { return HasDataBarrier; }
184  bool useFPVMLx() const { return !SlowFPVMLx; }
185  bool isFPBrccSlow() const { return SlowFPBrcc; }
186  bool isFPOnlySP() const { return FPOnlySP; }
187  bool prefers32BitThumb() const { return Pref32BitThumb; }
188  bool hasMPExtension() const { return HasMPExtension; }
189
190  bool hasFP16() const { return HasFP16; }
191  bool hasD16() const { return HasD16; }
192
193  bool isTargetDarwin() const { return TargetTriple.getOS() == Triple::Darwin; }
194  bool isTargetELF() const { return !isTargetDarwin(); }
195
196  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
197  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
198
199  bool isThumb() const { return IsThumb; }
200  bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
201  bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
202  bool hasThumb2() const { return ThumbMode >= Thumb2; }
203
204  bool isR9Reserved() const { return IsR9Reserved; }
205
206  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
207
208  bool allowsUnalignedMem() const { return AllowsUnalignedMem; }
209
210  const std::string & getCPUString() const { return CPUString; }
211
212  unsigned getMispredictionPenalty() const;
213
214  /// enablePostRAScheduler - True at 'More' optimization.
215  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
216                             TargetSubtarget::AntiDepBreakMode& Mode,
217                             RegClassVector& CriticalPathRCs) const;
218
219  /// getInstrItins - Return the instruction itineraies based on subtarget
220  /// selection.
221  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
222
223  /// getStackAlignment - Returns the minimum alignment known to hold of the
224  /// stack frame on entry to the function and which must be maintained by every
225  /// function for this subtarget.
226  unsigned getStackAlignment() const { return stackAlignment; }
227
228  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
229  /// symbol.
230  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
231};
232} // End llvm namespace
233
234#endif  // ARMSUBTARGET_H
235