ARMSubtarget.h revision 212904 
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "llvm/Target/TargetInstrItineraries.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetSubtarget.h"
20#include "ARMBaseRegisterInfo.h"
21#include <string>
22
23namespace llvm {
24class GlobalValue;
25
26class ARMSubtarget : public TargetSubtarget {
27protected:
28  enum ARMArchEnum {
29    V4, V4T, V5T, V5TE, V6, V6M, V6T2, V7A, V7M
30  };
31
32  enum ARMFPEnum {
33    None, VFPv2, VFPv3, NEON
34  };
35
36  enum ThumbTypeEnum {
37    Thumb1,
38    Thumb2
39  };
40
41  /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
42  /// V6, V6T2, V7A, V7M.
43  ARMArchEnum ARMArchVersion;
44
45  /// ARMFPUType - Floating Point Unit type.
46  ARMFPEnum ARMFPUType;
47
48  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
49  /// specified. Use the method useNEONForSinglePrecisionFP() to
50  /// determine if NEON should actually be used.
51  bool UseNEONForSinglePrecisionFP;
52
53  /// SlowVMLx - If the VFP2 instructions are available, indicates whether
54  /// the VML[AS] instructions are slow (if so, don't use them).
55  bool SlowVMLx;
56
57  /// SlowFPBrcc - True if floating point compare + branch is slow.
58  bool SlowFPBrcc;
59
60  /// IsThumb - True if we are in thumb mode, false if in ARM mode.
61  bool IsThumb;
62
63  /// ThumbMode - Indicates supported Thumb version.
64  ThumbTypeEnum ThumbMode;
65
66  /// NoARM - True if subtarget does not support ARM mode execution.
67  bool NoARM;
68
69  /// PostRAScheduler - True if using post-register-allocation scheduler.
70  bool PostRAScheduler;
71
72  /// IsR9Reserved - True if R9 is a not available as general purpose register.
73  bool IsR9Reserved;
74
75  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
76  /// imms (including global addresses).
77  bool UseMovt;
78
79  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
80  /// only so far)
81  bool HasFP16;
82
83  /// HasHardwareDivide - True if subtarget supports [su]div
84  bool HasHardwareDivide;
85
86  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
87  /// instructions.
88  bool HasT2ExtractPack;
89
90  /// HasDataBarrier - True if the subtarget supports DMB / DSB data barrier
91  /// instructions.
92  bool HasDataBarrier;
93
94  /// Pref32BitThumb - If true, codegen would prefer 32-bit Thumb instructions
95  /// over 16-bit ones.
96  bool Pref32BitThumb;
97
98  /// FPOnlySP - If true, the floating point unit only supports single
99  /// precision.
100  bool FPOnlySP;
101
102  /// stackAlignment - The minimum alignment known to hold of the stack frame on
103  /// entry to the function and which must be maintained by every function.
104  unsigned stackAlignment;
105
106  /// CPUString - String name of used CPU.
107  std::string CPUString;
108
109  /// Selected instruction itineraries (one entry per itinerary class.)
110  InstrItineraryData InstrItins;
111
112 public:
113  enum {
114    isELF, isDarwin
115  } TargetType;
116
117  enum {
118    ARM_ABI_APCS,
119    ARM_ABI_AAPCS // ARM EABI
120  } TargetABI;
121
122  /// This constructor initializes the data members to match that
123  /// of the specified triple.
124  ///
125  ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
126
127  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
128  /// that still makes it profitable to inline the call.
129  unsigned getMaxInlineSizeThreshold() const {
130    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
131    // Change this once Thumb1 ldmia / stmia support is added.
132    return isThumb1Only() ? 0 : 64;
133  }
134  /// ParseSubtargetFeatures - Parses features string setting specified
135  /// subtarget options.  Definition of function is auto generated by tblgen.
136  std::string ParseSubtargetFeatures(const std::string &FS,
137                                     const std::string &CPU);
138
139  bool hasV4TOps()  const { return ARMArchVersion >= V4T;  }
140  bool hasV5TOps()  const { return ARMArchVersion >= V5T;  }
141  bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
142  bool hasV6Ops()   const { return ARMArchVersion >= V6;   }
143  bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
144  bool hasV7Ops()   const { return ARMArchVersion >= V7A;  }
145
146  bool hasARMOps() const { return !NoARM; }
147
148  bool hasVFP2() const { return ARMFPUType >= VFPv2; }
149  bool hasVFP3() const { return ARMFPUType >= VFPv3; }
150  bool hasNEON() const { return ARMFPUType >= NEON;  }
151  bool useNEONForSinglePrecisionFP() const {
152    return hasNEON() && UseNEONForSinglePrecisionFP; }
153  bool hasDivide() const { return HasHardwareDivide; }
154  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
155  bool hasDataBarrier() const { return HasDataBarrier; }
156  bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
157  bool isFPBrccSlow() const { return SlowFPBrcc; }
158  bool isFPOnlySP() const { return FPOnlySP; }
159  bool prefers32BitThumb() const { return Pref32BitThumb; }
160
161  bool hasFP16() const { return HasFP16; }
162
163  bool isTargetDarwin() const { return TargetType == isDarwin; }
164  bool isTargetELF() const { return TargetType == isELF; }
165
166  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
167  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
168
169  bool isThumb() const { return IsThumb; }
170  bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
171  bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
172  bool hasThumb2() const { return ThumbMode >= Thumb2; }
173
174  bool isR9Reserved() const { return IsR9Reserved; }
175
176  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
177
178  const std::string & getCPUString() const { return CPUString; }
179
180  /// enablePostRAScheduler - True at 'More' optimization.
181  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
182                             TargetSubtarget::AntiDepBreakMode& Mode,
183                             RegClassVector& CriticalPathRCs) const;
184
185  /// getInstrItins - Return the instruction itineraies based on subtarget
186  /// selection.
187  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
188
189  /// getStackAlignment - Returns the minimum alignment known to hold of the
190  /// stack frame on entry to the function and which must be maintained by every
191  /// function for this subtarget.
192  unsigned getStackAlignment() const { return stackAlignment; }
193
194  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
195  /// symbol.
196  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
197};
198} // End llvm namespace
199
200#endif  // ARMSUBTARGET_H
201