ARMSubtarget.h revision 210299 
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "llvm/Target/TargetInstrItineraries.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetSubtarget.h"
20#include "ARMBaseRegisterInfo.h"
21#include <string>
22
23namespace llvm {
24class GlobalValue;
25
26class ARMSubtarget : public TargetSubtarget {
27protected:
28  enum ARMArchEnum {
29    V4, V4T, V5T, V5TE, V6, V6T2, V7A, V7M
30  };
31
32  enum ARMFPEnum {
33    None, VFPv2, VFPv3, NEON
34  };
35
36  enum ThumbTypeEnum {
37    Thumb1,
38    Thumb2
39  };
40
41  /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
42  /// V6, V6T2, V7A, V7M.
43  ARMArchEnum ARMArchVersion;
44
45  /// ARMFPUType - Floating Point Unit type.
46  ARMFPEnum ARMFPUType;
47
48  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
49  /// specified. Use the method useNEONForSinglePrecisionFP() to
50  /// determine if NEON should actually be used.
51  bool UseNEONForSinglePrecisionFP;
52
53  /// SlowVMLx - If the VFP2 instructions are available, indicates whether
54  /// the VML[AS] instructions are slow (if so, don't use them).
55  bool SlowVMLx;
56
57  /// SlowFPBrcc - True if floating point compare + branch is slow.
58  bool SlowFPBrcc;
59
60  /// IsThumb - True if we are in thumb mode, false if in ARM mode.
61  bool IsThumb;
62
63  /// ThumbMode - Indicates supported Thumb version.
64  ThumbTypeEnum ThumbMode;
65
66  /// PostRAScheduler - True if using post-register-allocation scheduler.
67  bool PostRAScheduler;
68
69  /// IsR9Reserved - True if R9 is a not available as general purpose register.
70  bool IsR9Reserved;
71
72  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
73  /// imms (including global addresses).
74  bool UseMovt;
75
76  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
77  /// only so far)
78  bool HasFP16;
79
80  /// HasHardwareDivide - True if subtarget supports [su]div
81  bool HasHardwareDivide;
82
83  /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack
84  /// instructions.
85  bool HasT2ExtractPack;
86
87  /// stackAlignment - The minimum alignment known to hold of the stack frame on
88  /// entry to the function and which must be maintained by every function.
89  unsigned stackAlignment;
90
91  /// CPUString - String name of used CPU.
92  std::string CPUString;
93
94  /// Selected instruction itineraries (one entry per itinerary class.)
95  InstrItineraryData InstrItins;
96
97 public:
98  enum {
99    isELF, isDarwin
100  } TargetType;
101
102  enum {
103    ARM_ABI_APCS,
104    ARM_ABI_AAPCS // ARM EABI
105  } TargetABI;
106
107  /// This constructor initializes the data members to match that
108  /// of the specified triple.
109  ///
110  ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
111
112  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
113  /// that still makes it profitable to inline the call.
114  unsigned getMaxInlineSizeThreshold() const {
115    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
116    // Change this once Thumb1 ldmia / stmia support is added.
117    return isThumb1Only() ? 0 : 64;
118  }
119  /// ParseSubtargetFeatures - Parses features string setting specified
120  /// subtarget options.  Definition of function is auto generated by tblgen.
121  std::string ParseSubtargetFeatures(const std::string &FS,
122                                     const std::string &CPU);
123
124  bool hasV4TOps()  const { return ARMArchVersion >= V4T;  }
125  bool hasV5TOps()  const { return ARMArchVersion >= V5T;  }
126  bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
127  bool hasV6Ops()   const { return ARMArchVersion >= V6;   }
128  bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
129  bool hasV7Ops()   const { return ARMArchVersion >= V7A;  }
130
131  bool hasVFP2() const { return ARMFPUType >= VFPv2; }
132  bool hasVFP3() const { return ARMFPUType >= VFPv3; }
133  bool hasNEON() const { return ARMFPUType >= NEON;  }
134  bool useNEONForSinglePrecisionFP() const {
135    return hasNEON() && UseNEONForSinglePrecisionFP; }
136  bool hasDivide() const { return HasHardwareDivide; }
137  bool hasT2ExtractPack() const { return HasT2ExtractPack; }
138  bool useVMLx() const {return hasVFP2() && !SlowVMLx; }
139  bool isFPBrccSlow() const { return SlowFPBrcc; }
140
141  bool hasFP16() const { return HasFP16; }
142
143  bool isTargetDarwin() const { return TargetType == isDarwin; }
144  bool isTargetELF() const { return TargetType == isELF; }
145
146  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
147  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
148
149  bool isThumb() const { return IsThumb; }
150  bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
151  bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
152  bool hasThumb2() const { return ThumbMode >= Thumb2; }
153
154  bool isR9Reserved() const { return IsR9Reserved; }
155
156  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
157
158  const std::string & getCPUString() const { return CPUString; }
159
160  /// enablePostRAScheduler - True at 'More' optimization.
161  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
162                             TargetSubtarget::AntiDepBreakMode& Mode,
163                             RegClassVector& CriticalPathRCs) const;
164
165  /// getInstrItins - Return the instruction itineraies based on subtarget
166  /// selection.
167  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
168
169  /// getStackAlignment - Returns the minimum alignment known to hold of the
170  /// stack frame on entry to the function and which must be maintained by every
171  /// function for this subtarget.
172  unsigned getStackAlignment() const { return stackAlignment; }
173
174  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
175  /// symbol.
176  bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const;
177};
178} // End llvm namespace
179
180#endif  // ARMSUBTARGET_H
181