ARMSubtarget.h revision 208954
1353944Sdim//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====// 2353944Sdim// 3353944Sdim// The LLVM Compiler Infrastructure 4353944Sdim// 5353944Sdim// This file is distributed under the University of Illinois Open Source 6353944Sdim// License. See LICENSE.TXT for details. 7353944Sdim// 8353944Sdim//===----------------------------------------------------------------------===// 9353944Sdim// 10353944Sdim// This file declares the ARM specific subclass of TargetSubtarget. 11353944Sdim// 12353944Sdim//===----------------------------------------------------------------------===// 13353944Sdim 14353944Sdim#ifndef ARMSUBTARGET_H 15353944Sdim#define ARMSUBTARGET_H 16353944Sdim 17353944Sdim#include "llvm/Target/TargetInstrItineraries.h" 18353944Sdim#include "llvm/Target/TargetMachine.h" 19353944Sdim#include "llvm/Target/TargetSubtarget.h" 20353944Sdim#include "ARMBaseRegisterInfo.h" 21353944Sdim#include <string> 22353944Sdim 23353944Sdimnamespace llvm { 24353944Sdimclass GlobalValue; 25353944Sdim 26353944Sdimclass ARMSubtarget : public TargetSubtarget { 27353944Sdimprotected: 28353944Sdim enum ARMArchEnum { 29353944Sdim V4, V4T, V5T, V5TE, V6, V6T2, V7A, V7M 30353944Sdim }; 31353944Sdim 32353944Sdim enum ARMFPEnum { 33353944Sdim None, VFPv2, VFPv3, NEON 34353944Sdim }; 35353944Sdim 36353944Sdim enum ThumbTypeEnum { 37353944Sdim Thumb1, 38353944Sdim Thumb2 39353944Sdim }; 40353944Sdim 41353944Sdim /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE, 42353944Sdim /// V6, V6T2, V7A, V7M. 43353944Sdim ARMArchEnum ARMArchVersion; 44353944Sdim 45353944Sdim /// ARMFPUType - Floating Point Unit type. 46353944Sdim ARMFPEnum ARMFPUType; 47353944Sdim 48353944Sdim /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been 49353944Sdim /// specified. Use the method useNEONForSinglePrecisionFP() to 50353944Sdim /// determine if NEON should actually be used. 51353944Sdim bool UseNEONForSinglePrecisionFP; 52353944Sdim 53353944Sdim /// SlowVMLx - If the VFP2 instructions are available, indicates whether 54353944Sdim /// the VML[AS] instructions are slow (if so, don't use them). 55353944Sdim bool SlowVMLx; 56353944Sdim 57353944Sdim /// IsThumb - True if we are in thumb mode, false if in ARM mode. 58353944Sdim bool IsThumb; 59353944Sdim 60353944Sdim /// ThumbMode - Indicates supported Thumb version. 61353944Sdim ThumbTypeEnum ThumbMode; 62353944Sdim 63353944Sdim /// PostRAScheduler - True if using post-register-allocation scheduler. 64353944Sdim bool PostRAScheduler; 65353944Sdim 66353944Sdim /// IsR9Reserved - True if R9 is a not available as general purpose register. 67353944Sdim bool IsR9Reserved; 68353944Sdim 69353944Sdim /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit 70353944Sdim /// imms (including global addresses). 71353944Sdim bool UseMovt; 72353944Sdim 73353944Sdim /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF 74353944Sdim /// only so far) 75353944Sdim bool HasFP16; 76353944Sdim 77353944Sdim /// HasHardwareDivide - True if subtarget supports [su]div 78353944Sdim bool HasHardwareDivide; 79353944Sdim 80353944Sdim /// HasT2ExtractPack - True if subtarget supports thumb2 extract/pack 81353944Sdim /// instructions. 82353944Sdim bool HasT2ExtractPack; 83353944Sdim 84353944Sdim /// stackAlignment - The minimum alignment known to hold of the stack frame on 85353944Sdim /// entry to the function and which must be maintained by every function. 86353944Sdim unsigned stackAlignment; 87353944Sdim 88353944Sdim /// CPUString - String name of used CPU. 89353944Sdim std::string CPUString; 90353944Sdim 91353944Sdim /// Selected instruction itineraries (one entry per itinerary class.) 92353944Sdim InstrItineraryData InstrItins; 93353944Sdim 94353944Sdim public: 95353944Sdim enum { 96353944Sdim isELF, isDarwin 97353944Sdim } TargetType; 98353944Sdim 99353944Sdim enum { 100353944Sdim ARM_ABI_APCS, 101353944Sdim ARM_ABI_AAPCS // ARM EABI 102353944Sdim } TargetABI; 103353944Sdim 104353944Sdim /// This constructor initializes the data members to match that 105353944Sdim /// of the specified triple. 106353944Sdim /// 107353944Sdim ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb); 108353944Sdim 109353944Sdim /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size 110353944Sdim /// that still makes it profitable to inline the call. 111353944Sdim unsigned getMaxInlineSizeThreshold() const { 112353944Sdim // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1. 113 // Change this once Thumb1 ldmia / stmia support is added. 114 return isThumb1Only() ? 0 : 64; 115 } 116 /// ParseSubtargetFeatures - Parses features string setting specified 117 /// subtarget options. Definition of function is auto generated by tblgen. 118 std::string ParseSubtargetFeatures(const std::string &FS, 119 const std::string &CPU); 120 121 bool hasV4TOps() const { return ARMArchVersion >= V4T; } 122 bool hasV5TOps() const { return ARMArchVersion >= V5T; } 123 bool hasV5TEOps() const { return ARMArchVersion >= V5TE; } 124 bool hasV6Ops() const { return ARMArchVersion >= V6; } 125 bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; } 126 bool hasV7Ops() const { return ARMArchVersion >= V7A; } 127 128 bool hasVFP2() const { return ARMFPUType >= VFPv2; } 129 bool hasVFP3() const { return ARMFPUType >= VFPv3; } 130 bool hasNEON() const { return ARMFPUType >= NEON; } 131 bool useNEONForSinglePrecisionFP() const { 132 return hasNEON() && UseNEONForSinglePrecisionFP; } 133 bool hasDivide() const { return HasHardwareDivide; } 134 bool hasT2ExtractPack() const { return HasT2ExtractPack; } 135 bool useVMLx() const {return hasVFP2() && !SlowVMLx; } 136 137 bool hasFP16() const { return HasFP16; } 138 139 bool isTargetDarwin() const { return TargetType == isDarwin; } 140 bool isTargetELF() const { return TargetType == isELF; } 141 142 bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; } 143 bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; } 144 145 bool isThumb() const { return IsThumb; } 146 bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); } 147 bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); } 148 bool hasThumb2() const { return ThumbMode >= Thumb2; } 149 150 bool isR9Reserved() const { return IsR9Reserved; } 151 152 bool useMovt() const { return UseMovt && hasV6T2Ops(); } 153 154 const std::string & getCPUString() const { return CPUString; } 155 156 /// enablePostRAScheduler - True at 'More' optimization. 157 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel, 158 TargetSubtarget::AntiDepBreakMode& Mode, 159 RegClassVector& CriticalPathRCs) const; 160 161 /// getInstrItins - Return the instruction itineraies based on subtarget 162 /// selection. 163 const InstrItineraryData &getInstrItineraryData() const { return InstrItins; } 164 165 /// getStackAlignment - Returns the minimum alignment known to hold of the 166 /// stack frame on entry to the function and which must be maintained by every 167 /// function for this subtarget. 168 unsigned getStackAlignment() const { return stackAlignment; } 169 170 /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect 171 /// symbol. 172 bool GVIsIndirectSymbol(const GlobalValue *GV, Reloc::Model RelocM) const; 173}; 174} // End llvm namespace 175 176#endif // ARMSUBTARGET_H 177