ARMSubtarget.h revision 205218 
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "llvm/Target/TargetInstrItineraries.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetSubtarget.h"
20#include "ARMBaseRegisterInfo.h"
21#include <string>
22
23namespace llvm {
24class GlobalValue;
25
26class ARMSubtarget : public TargetSubtarget {
27protected:
28  enum ARMArchEnum {
29    V4, V4T, V5T, V5TE, V6, V6T2, V7A
30  };
31
32  enum ARMFPEnum {
33    None, VFPv2, VFPv3, NEON
34  };
35
36  enum ThumbTypeEnum {
37    Thumb1,
38    Thumb2
39  };
40
41  /// ARMArchVersion - ARM architecture version: V4, V4T (base), V5T, V5TE,
42  /// V6, V6T2, V7A.
43  ARMArchEnum ARMArchVersion;
44
45  /// ARMFPUType - Floating Point Unit type.
46  ARMFPEnum ARMFPUType;
47
48  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
49  /// specified. Use the method useNEONForSinglePrecisionFP() to
50  /// determine if NEON should actually be used.
51  bool UseNEONForSinglePrecisionFP;
52
53  /// IsThumb - True if we are in thumb mode, false if in ARM mode.
54  bool IsThumb;
55
56  /// ThumbMode - Indicates supported Thumb version.
57  ThumbTypeEnum ThumbMode;
58
59  /// PostRAScheduler - True if using post-register-allocation scheduler.
60  bool PostRAScheduler;
61
62  /// IsR9Reserved - True if R9 is a not available as general purpose register.
63  bool IsR9Reserved;
64
65  /// UseMovt - True if MOVT / MOVW pairs are used for materialization of 32-bit
66  /// imms (including global addresses).
67  bool UseMovt;
68
69  /// HasFP16 - True if subtarget supports half-precision FP (We support VFP+HF
70  /// only so far)
71  bool HasFP16;
72
73  /// stackAlignment - The minimum alignment known to hold of the stack frame on
74  /// entry to the function and which must be maintained by every function.
75  unsigned stackAlignment;
76
77  /// CPUString - String name of used CPU.
78  std::string CPUString;
79
80  /// Selected instruction itineraries (one entry per itinerary class.)
81  InstrItineraryData InstrItins;
82
83 public:
84  enum {
85    isELF, isDarwin
86  } TargetType;
87
88  enum {
89    ARM_ABI_APCS,
90    ARM_ABI_AAPCS // ARM EABI
91  } TargetABI;
92
93  /// This constructor initializes the data members to match that
94  /// of the specified triple.
95  ///
96  ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
97
98  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
99  /// that still makes it profitable to inline the call.
100  unsigned getMaxInlineSizeThreshold() const {
101    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb1.
102    // Change this once Thumb1 ldmia / stmia support is added.
103    return isThumb1Only() ? 0 : 64;
104  }
105  /// ParseSubtargetFeatures - Parses features string setting specified
106  /// subtarget options.  Definition of function is auto generated by tblgen.
107  std::string ParseSubtargetFeatures(const std::string &FS,
108                                     const std::string &CPU);
109
110  bool hasV4TOps()  const { return ARMArchVersion >= V4T;  }
111  bool hasV5TOps()  const { return ARMArchVersion >= V5T;  }
112  bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
113  bool hasV6Ops()   const { return ARMArchVersion >= V6;   }
114  bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
115  bool hasV7Ops()   const { return ARMArchVersion >= V7A;  }
116
117  bool hasVFP2() const { return ARMFPUType >= VFPv2; }
118  bool hasVFP3() const { return ARMFPUType >= VFPv3; }
119  bool hasNEON() const { return ARMFPUType >= NEON;  }
120  bool useNEONForSinglePrecisionFP() const {
121    return hasNEON() && UseNEONForSinglePrecisionFP; }
122
123  bool hasFP16() const { return HasFP16; }
124
125  bool isTargetDarwin() const { return TargetType == isDarwin; }
126  bool isTargetELF() const { return TargetType == isELF; }
127
128  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
129  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
130
131  bool isThumb() const { return IsThumb; }
132  bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
133  bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
134  bool hasThumb2() const { return ThumbMode >= Thumb2; }
135
136  bool isR9Reserved() const { return IsR9Reserved; }
137
138  bool useMovt() const { return UseMovt && hasV6T2Ops(); }
139
140  const std::string & getCPUString() const { return CPUString; }
141
142  /// enablePostRAScheduler - True at 'More' optimization.
143  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
144                             TargetSubtarget::AntiDepBreakMode& Mode,
145                             RegClassVector& CriticalPathRCs) const;
146
147  /// getInstrItins - Return the instruction itineraies based on subtarget
148  /// selection.
149  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
150
151  /// getStackAlignment - Returns the minimum alignment known to hold of the
152  /// stack frame on entry to the function and which must be maintained by every
153  /// function for this subtarget.
154  unsigned getStackAlignment() const { return stackAlignment; }
155
156  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
157  /// symbol.
158  bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) const;
159};
160} // End llvm namespace
161
162#endif  // ARMSUBTARGET_H
163