ARMSubtarget.h revision 199481 
1//=====---- ARMSubtarget.h - Define Subtarget for the ARM -----*- C++ -*--====//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file declares the ARM specific subclass of TargetSubtarget.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMSUBTARGET_H
15#define ARMSUBTARGET_H
16
17#include "llvm/Target/TargetInstrItineraries.h"
18#include "llvm/Target/TargetMachine.h"
19#include "llvm/Target/TargetSubtarget.h"
20#include "ARMBaseRegisterInfo.h"
21#include <string>
22
23namespace llvm {
24class GlobalValue;
25
26class ARMSubtarget : public TargetSubtarget {
27protected:
28  enum ARMArchEnum {
29    V4T, V5T, V5TE, V6, V6T2, V7A
30  };
31
32  enum ARMFPEnum {
33    None, VFPv2, VFPv3, NEON
34  };
35
36  enum ThumbTypeEnum {
37    Thumb1,
38    Thumb2
39  };
40
41  /// ARMArchVersion - ARM architecture version: V4T (base), V5T, V5TE,
42  /// V6, V6T2, V7A.
43  ARMArchEnum ARMArchVersion;
44
45  /// ARMFPUType - Floating Point Unit type.
46  ARMFPEnum ARMFPUType;
47
48  /// UseNEONForSinglePrecisionFP - if the NEONFP attribute has been
49  /// specified. Use the method useNEONForSinglePrecisionFP() to
50  /// determine if NEON should actually be used.
51  bool UseNEONForSinglePrecisionFP;
52
53  /// HasBranchTargetBuffer - True if processor can predict indirect branches.
54  bool HasBranchTargetBuffer;
55
56  /// IsThumb - True if we are in thumb mode, false if in ARM mode.
57  bool IsThumb;
58
59  /// ThumbMode - Indicates supported Thumb version.
60  ThumbTypeEnum ThumbMode;
61
62  /// PostRAScheduler - True if using post-register-allocation scheduler.
63  bool PostRAScheduler;
64
65  /// IsR9Reserved - True if R9 is a not available as general purpose register.
66  bool IsR9Reserved;
67
68  /// stackAlignment - The minimum alignment known to hold of the stack frame on
69  /// entry to the function and which must be maintained by every function.
70  unsigned stackAlignment;
71
72  /// CPUString - String name of used CPU.
73  std::string CPUString;
74
75  /// Selected instruction itineraries (one entry per itinerary class.)
76  InstrItineraryData InstrItins;
77
78 public:
79  enum {
80    isELF, isDarwin
81  } TargetType;
82
83  enum {
84    ARM_ABI_APCS,
85    ARM_ABI_AAPCS // ARM EABI
86  } TargetABI;
87
88  /// This constructor initializes the data members to match that
89  /// of the specified triple.
90  ///
91  ARMSubtarget(const std::string &TT, const std::string &FS, bool isThumb);
92
93  /// getMaxInlineSizeThreshold - Returns the maximum memset / memcpy size
94  /// that still makes it profitable to inline the call.
95  unsigned getMaxInlineSizeThreshold() const {
96    // FIXME: For now, we don't lower memcpy's to loads / stores for Thumb.
97    // Change this once Thumb ldmia / stmia support is added.
98    return isThumb() ? 0 : 64;
99  }
100  /// ParseSubtargetFeatures - Parses features string setting specified
101  /// subtarget options.  Definition of function is auto generated by tblgen.
102  std::string ParseSubtargetFeatures(const std::string &FS,
103                                     const std::string &CPU);
104
105  bool hasV4TOps()  const { return ARMArchVersion >= V4T;  }
106  bool hasV5TOps()  const { return ARMArchVersion >= V5T;  }
107  bool hasV5TEOps() const { return ARMArchVersion >= V5TE; }
108  bool hasV6Ops()   const { return ARMArchVersion >= V6;   }
109  bool hasV6T2Ops() const { return ARMArchVersion >= V6T2; }
110  bool hasV7Ops()   const { return ARMArchVersion >= V7A;  }
111
112  bool hasVFP2() const { return ARMFPUType >= VFPv2; }
113  bool hasVFP3() const { return ARMFPUType >= VFPv3; }
114  bool hasNEON() const { return ARMFPUType >= NEON;  }
115  bool useNEONForSinglePrecisionFP() const {
116    return hasNEON() && UseNEONForSinglePrecisionFP; }
117
118  bool isTargetDarwin() const { return TargetType == isDarwin; }
119  bool isTargetELF() const { return TargetType == isELF; }
120
121  bool isAPCS_ABI() const { return TargetABI == ARM_ABI_APCS; }
122  bool isAAPCS_ABI() const { return TargetABI == ARM_ABI_AAPCS; }
123
124  bool isThumb() const { return IsThumb; }
125  bool isThumb1Only() const { return IsThumb && (ThumbMode == Thumb1); }
126  bool isThumb2() const { return IsThumb && (ThumbMode == Thumb2); }
127  bool hasThumb2() const { return ThumbMode >= Thumb2; }
128
129  bool hasBranchTargetBuffer() const { return HasBranchTargetBuffer; }
130
131  bool isR9Reserved() const { return IsR9Reserved; }
132
133  const std::string & getCPUString() const { return CPUString; }
134
135  /// enablePostRAScheduler - True at 'More' optimization.
136  bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
137                             TargetSubtarget::AntiDepBreakMode& Mode,
138                             RegClassVector& CriticalPathRCs) const;
139
140  /// getInstrItins - Return the instruction itineraies based on subtarget
141  /// selection.
142  const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
143
144  /// getStackAlignment - Returns the minimum alignment known to hold of the
145  /// stack frame on entry to the function and which must be maintained by every
146  /// function for this subtarget.
147  unsigned getStackAlignment() const { return stackAlignment; }
148
149  /// GVIsIndirectSymbol - true if the GV will be accessed via an indirect
150  /// symbol.
151  bool GVIsIndirectSymbol(GlobalValue *GV, Reloc::Model RelocM) const;
152};
153} // End llvm namespace
154
155#endif  // ARMSUBTARGET_H
156