ARMRegisterInfo.h revision 194612 
1104862Sru//===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===//
275584Sru//
375584Sru//                     The LLVM Compiler Infrastructure
475584Sru//
5104862Sru// This file is distributed under the University of Illinois Open Source
6114402Sru// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the ARM implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#ifndef ARMREGISTERINFO_H
15#define ARMREGISTERINFO_H
16
17#include "llvm/Target/TargetRegisterInfo.h"
18#include "ARMGenRegisterInfo.h.inc"
19
20namespace llvm {
21  class ARMSubtarget;
22  class TargetInstrInfo;
23  class Type;
24
25/// Register allocation hints.
26namespace ARMRI {
27  enum {
28    RegPairOdd  = 1,
29    RegPairEven = 2
30  };
31}
32
33struct ARMRegisterInfo : public ARMGenRegisterInfo {
34  const TargetInstrInfo &TII;
35  const ARMSubtarget &STI;
36
37public:
38  ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI);
39
40  /// emitLoadConstPool - Emits a load from constpool to materialize the
41  /// specified immediate.
42  void emitLoadConstPool(MachineBasicBlock &MBB,
43                         MachineBasicBlock::iterator &MBBI,
44                         unsigned DestReg, int Val,
45                         unsigned Pred, unsigned PredReg,
46                         const TargetInstrInfo *TII, bool isThumb,
47                         DebugLoc dl) const;
48
49  /// getRegisterNumbering - Given the enum value for some register, e.g.
50  /// ARM::LR, return the number that it corresponds to (e.g. 14).
51  static unsigned getRegisterNumbering(unsigned RegEnum);
52
53  /// Same as previous getRegisterNumbering except it returns true in isSPVFP
54  /// if the register is a single precision VFP register.
55  static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP);
56
57  /// Code Generation virtual methods...
58  const TargetRegisterClass *
59    getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const;
60  const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
61
62  const TargetRegisterClass* const*
63  getCalleeSavedRegClasses(const MachineFunction *MF = 0) const;
64
65  BitVector getReservedRegs(const MachineFunction &MF) const;
66
67  bool isReservedReg(const MachineFunction &MF, unsigned Reg) const;
68
69  const TargetRegisterClass *getPointerRegClass() const;
70
71  std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
72  getAllocationOrder(const TargetRegisterClass *RC,
73                     unsigned HintType, unsigned HintReg,
74                     const MachineFunction &MF) const;
75
76  unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
77                               const MachineFunction &MF) const;
78
79  void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
80                          MachineFunction &MF) const;
81
82  bool requiresRegisterScavenging(const MachineFunction &MF) const;
83
84  bool hasFP(const MachineFunction &MF) const;
85
86  bool hasReservedCallFrame(MachineFunction &MF) const;
87
88  void eliminateCallFramePseudoInstr(MachineFunction &MF,
89                                     MachineBasicBlock &MBB,
90                                     MachineBasicBlock::iterator I) const;
91
92  void eliminateFrameIndex(MachineBasicBlock::iterator II,
93                           int SPAdj, RegScavenger *RS = NULL) const;
94
95  void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
96                                            RegScavenger *RS = NULL) const;
97
98  void emitPrologue(MachineFunction &MF) const;
99  void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
100
101  // Debug information queries.
102  unsigned getRARegister() const;
103  unsigned getFrameRegister(MachineFunction &MF) const;
104
105  // Exception handling queries.
106  unsigned getEHExceptionRegister() const;
107  unsigned getEHHandlerRegister() const;
108
109  int getDwarfRegNum(unsigned RegNum, bool isEH) const;
110
111  bool isLowRegister(unsigned Reg) const;
112
113private:
114  /// FramePtr - ARM physical register used as frame ptr.
115  unsigned FramePtr;
116
117  unsigned getRegisterPairEven(unsigned Reg, const MachineFunction &MF) const;
118
119  unsigned getRegisterPairOdd(unsigned Reg, const MachineFunction &MF) const;
120
121};
122
123} // end namespace llvm
124
125#endif
126