ARMRegisterInfo.h revision 193323
1254721Semaste//===- ARMRegisterInfo.h - ARM Register Information Impl --------*- C++ -*-===// 2254721Semaste// 3254721Semaste// The LLVM Compiler Infrastructure 4254721Semaste// 5254721Semaste// This file is distributed under the University of Illinois Open Source 6254721Semaste// License. See LICENSE.TXT for details. 7254721Semaste// 8254721Semaste//===----------------------------------------------------------------------===// 9254721Semaste// 10254721Semaste// This file contains the ARM implementation of the TargetRegisterInfo class. 11254721Semaste// 12254721Semaste//===----------------------------------------------------------------------===// 13254721Semaste 14254721Semaste#ifndef ARMREGISTERINFO_H 15254721Semaste#define ARMREGISTERINFO_H 16254721Semaste 17254721Semaste#include "llvm/Target/TargetRegisterInfo.h" 18254721Semaste#include "ARMGenRegisterInfo.h.inc" 19254721Semaste 20254721Semastenamespace llvm { 21254721Semaste class ARMSubtarget; 22254721Semaste class TargetInstrInfo; 23254721Semaste class Type; 24254721Semaste 25254721Semastestruct ARMRegisterInfo : public ARMGenRegisterInfo { 26254721Semaste const TargetInstrInfo &TII; 27254721Semaste const ARMSubtarget &STI; 28254721Semasteprivate: 29254721Semaste /// FramePtr - ARM physical register used as frame ptr. 30254721Semaste unsigned FramePtr; 31254721Semaste 32254721Semastepublic: 33254721Semaste ARMRegisterInfo(const TargetInstrInfo &tii, const ARMSubtarget &STI); 34254721Semaste 35254721Semaste /// emitLoadConstPool - Emits a load from constpool to materialize the 36254721Semaste /// specified immediate. 37254721Semaste void emitLoadConstPool(MachineBasicBlock &MBB, 38254721Semaste MachineBasicBlock::iterator &MBBI, 39254721Semaste unsigned DestReg, int Val, 40254721Semaste unsigned Pred, unsigned PredReg, 41254721Semaste const TargetInstrInfo *TII, bool isThumb, 42254721Semaste DebugLoc dl) const; 43254721Semaste 44254721Semaste /// getRegisterNumbering - Given the enum value for some register, e.g. 45254721Semaste /// ARM::LR, return the number that it corresponds to (e.g. 14). 46254721Semaste static unsigned getRegisterNumbering(unsigned RegEnum); 47254721Semaste 48254721Semaste /// Same as previous getRegisterNumbering except it returns true in isSPVFP 49254721Semaste /// if the register is a single precision VFP register. 50254721Semaste static unsigned getRegisterNumbering(unsigned RegEnum, bool &isSPVFP); 51254721Semaste 52254721Semaste /// getPointerRegClass - Return the register class to use to hold pointers. 53254721Semaste /// This is used for addressing modes. 54254721Semaste const TargetRegisterClass *getPointerRegClass() const; 55254721Semaste 56254721Semaste /// Code Generation virtual methods... 57254721Semaste const TargetRegisterClass * 58254721Semaste getPhysicalRegisterRegClass(unsigned Reg, MVT VT = MVT::Other) const; 59254721Semaste const unsigned *getCalleeSavedRegs(const MachineFunction *MF = 0) const; 60254721Semaste 61254721Semaste const TargetRegisterClass* const* 62254721Semaste getCalleeSavedRegClasses(const MachineFunction *MF = 0) const; 63254721Semaste 64254721Semaste BitVector getReservedRegs(const MachineFunction &MF) const; 65254721Semaste 66254721Semaste bool isReservedReg(const MachineFunction &MF, unsigned Reg) const; 67254721Semaste 68254721Semaste bool requiresRegisterScavenging(const MachineFunction &MF) const; 69254721Semaste 70254721Semaste bool hasFP(const MachineFunction &MF) const; 71254721Semaste 72254721Semaste bool hasReservedCallFrame(MachineFunction &MF) const; 73254721Semaste 74254721Semaste void eliminateCallFramePseudoInstr(MachineFunction &MF, 75254721Semaste MachineBasicBlock &MBB, 76254721Semaste MachineBasicBlock::iterator I) const; 77254721Semaste 78254721Semaste void eliminateFrameIndex(MachineBasicBlock::iterator II, 79254721Semaste int SPAdj, RegScavenger *RS = NULL) const; 80254721Semaste 81254721Semaste void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, 82254721Semaste RegScavenger *RS = NULL) const; 83254721Semaste 84254721Semaste void emitPrologue(MachineFunction &MF) const; 85254721Semaste void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; 86254721Semaste 87254721Semaste // Debug information queries. 88254721Semaste unsigned getRARegister() const; 89254721Semaste unsigned getFrameRegister(MachineFunction &MF) const; 90254721Semaste 91254721Semaste // Exception handling queries. 92254721Semaste unsigned getEHExceptionRegister() const; 93254721Semaste unsigned getEHHandlerRegister() const; 94254721Semaste 95254721Semaste int getDwarfRegNum(unsigned RegNum, bool isEH) const; 96254721Semaste 97254721Semaste bool isLowRegister(unsigned Reg) const; 98254721Semaste}; 99254721Semaste 100254721Semaste} // end namespace llvm 101254721Semaste 102254721Semaste#endif 103254721Semaste