ARMRegisterInfo.cpp revision 195340 
1//===- ARMRegisterInfo.cpp - ARM Register Information -----------*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the ARM implementation of the TargetRegisterInfo class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "ARM.h"
15#include "ARMAddressingModes.h"
16#include "ARMInstrInfo.h"
17#include "ARMMachineFunctionInfo.h"
18#include "ARMRegisterInfo.h"
19#include "ARMSubtarget.h"
20#include "llvm/Constants.h"
21#include "llvm/DerivedTypes.h"
22#include "llvm/CodeGen/MachineConstantPool.h"
23#include "llvm/CodeGen/MachineFrameInfo.h"
24#include "llvm/CodeGen/MachineFunction.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineLocation.h"
27#include "llvm/CodeGen/MachineRegisterInfo.h"
28#include "llvm/CodeGen/RegisterScavenging.h"
29#include "llvm/Target/TargetFrameInfo.h"
30#include "llvm/Target/TargetMachine.h"
31#include "llvm/Target/TargetOptions.h"
32#include "llvm/ADT/BitVector.h"
33#include "llvm/ADT/SmallVector.h"
34using namespace llvm;
35
36unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum) {
37  using namespace ARM;
38  switch (RegEnum) {
39  case R0:  case S0:  case D0:  return 0;
40  case R1:  case S1:  case D1:  return 1;
41  case R2:  case S2:  case D2:  return 2;
42  case R3:  case S3:  case D3:  return 3;
43  case R4:  case S4:  case D4:  return 4;
44  case R5:  case S5:  case D5:  return 5;
45  case R6:  case S6:  case D6:  return 6;
46  case R7:  case S7:  case D7:  return 7;
47  case R8:  case S8:  case D8:  return 8;
48  case R9:  case S9:  case D9:  return 9;
49  case R10: case S10: case D10: return 10;
50  case R11: case S11: case D11: return 11;
51  case R12: case S12: case D12: return 12;
52  case SP:  case S13: case D13: return 13;
53  case LR:  case S14: case D14: return 14;
54  case PC:  case S15: case D15: return 15;
55  case S16: return 16;
56  case S17: return 17;
57  case S18: return 18;
58  case S19: return 19;
59  case S20: return 20;
60  case S21: return 21;
61  case S22: return 22;
62  case S23: return 23;
63  case S24: return 24;
64  case S25: return 25;
65  case S26: return 26;
66  case S27: return 27;
67  case S28: return 28;
68  case S29: return 29;
69  case S30: return 30;
70  case S31: return 31;
71  default:
72    assert(0 && "Unknown ARM register!");
73    abort();
74  }
75}
76
77unsigned ARMBaseRegisterInfo::getRegisterNumbering(unsigned RegEnum,
78                                                   bool &isSPVFP) {
79  isSPVFP = false;
80
81  using namespace ARM;
82  switch (RegEnum) {
83  default:
84    assert(0 && "Unknown ARM register!");
85    abort();
86  case R0:  case D0:  return 0;
87  case R1:  case D1:  return 1;
88  case R2:  case D2:  return 2;
89  case R3:  case D3:  return 3;
90  case R4:  case D4:  return 4;
91  case R5:  case D5:  return 5;
92  case R6:  case D6:  return 6;
93  case R7:  case D7:  return 7;
94  case R8:  case D8:  return 8;
95  case R9:  case D9:  return 9;
96  case R10: case D10: return 10;
97  case R11: case D11: return 11;
98  case R12: case D12: return 12;
99  case SP:  case D13: return 13;
100  case LR:  case D14: return 14;
101  case PC:  case D15: return 15;
102
103  case S0: case S1: case S2: case S3:
104  case S4: case S5: case S6: case S7:
105  case S8: case S9: case S10: case S11:
106  case S12: case S13: case S14: case S15:
107  case S16: case S17: case S18: case S19:
108  case S20: case S21: case S22: case S23:
109  case S24: case S25: case S26: case S27:
110  case S28: case S29: case S30: case S31:  {
111    isSPVFP = true;
112    switch (RegEnum) {
113    default: return 0; // Avoid compile time warning.
114    case S0: return 0;
115    case S1: return 1;
116    case S2: return 2;
117    case S3: return 3;
118    case S4: return 4;
119    case S5: return 5;
120    case S6: return 6;
121    case S7: return 7;
122    case S8: return 8;
123    case S9: return 9;
124    case S10: return 10;
125    case S11: return 11;
126    case S12: return 12;
127    case S13: return 13;
128    case S14: return 14;
129    case S15: return 15;
130    case S16: return 16;
131    case S17: return 17;
132    case S18: return 18;
133    case S19: return 19;
134    case S20: return 20;
135    case S21: return 21;
136    case S22: return 22;
137    case S23: return 23;
138    case S24: return 24;
139    case S25: return 25;
140    case S26: return 26;
141    case S27: return 27;
142    case S28: return 28;
143    case S29: return 29;
144    case S30: return 30;
145    case S31: return 31;
146    }
147  }
148  }
149}
150
151ARMBaseRegisterInfo::ARMBaseRegisterInfo(const TargetInstrInfo &tii,
152                                         const ARMSubtarget &sti)
153  : ARMGenRegisterInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
154    TII(tii), STI(sti),
155    FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11) {
156}
157
158ARMRegisterInfo::ARMRegisterInfo(const TargetInstrInfo &tii,
159                                 const ARMSubtarget &sti)
160  : ARMBaseRegisterInfo(tii, sti) {
161}
162
163static inline
164const MachineInstrBuilder &AddDefaultPred(const MachineInstrBuilder &MIB) {
165  return MIB.addImm((int64_t)ARMCC::AL).addReg(0);
166}
167
168static inline
169const MachineInstrBuilder &AddDefaultCC(const MachineInstrBuilder &MIB) {
170  return MIB.addReg(0);
171}
172
173/// emitLoadConstPool - Emits a load from constpool to materialize the
174/// specified immediate.
175void ARMRegisterInfo::emitLoadConstPool(MachineBasicBlock &MBB,
176                                        MachineBasicBlock::iterator &MBBI,
177                                        const TargetInstrInfo *TII, DebugLoc dl,
178                                        unsigned DestReg, int Val,
179                                        ARMCC::CondCodes Pred,
180                                        unsigned PredReg) const {
181  MachineFunction &MF = *MBB.getParent();
182  MachineConstantPool *ConstantPool = MF.getConstantPool();
183  Constant *C = ConstantInt::get(Type::Int32Ty, Val);
184  unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
185
186  BuildMI(MBB, MBBI, dl, TII->get(ARM::LDRcp), DestReg)
187    .addConstantPoolIndex(Idx)
188    .addReg(0).addImm(0).addImm(Pred).addReg(PredReg);
189}
190
191const unsigned*
192ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
193  static const unsigned CalleeSavedRegs[] = {
194    ARM::LR, ARM::R11, ARM::R10, ARM::R9, ARM::R8,
195    ARM::R7, ARM::R6,  ARM::R5,  ARM::R4,
196
197    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
198    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
199    0
200  };
201
202  static const unsigned DarwinCalleeSavedRegs[] = {
203    // Darwin ABI deviates from ARM standard ABI. R9 is not a callee-saved
204    // register.
205    ARM::LR,  ARM::R7,  ARM::R6, ARM::R5, ARM::R4,
206    ARM::R11, ARM::R10, ARM::R8,
207
208    ARM::D15, ARM::D14, ARM::D13, ARM::D12,
209    ARM::D11, ARM::D10, ARM::D9,  ARM::D8,
210    0
211  };
212  return STI.isTargetDarwin() ? DarwinCalleeSavedRegs : CalleeSavedRegs;
213}
214
215const TargetRegisterClass* const *
216ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
217  static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
218    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
219    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
220    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
221
222    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
223    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
224    0
225  };
226
227  static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
228    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
229    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
230    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
231
232    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
233    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
234    0
235  };
236
237  static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
238    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
239    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
240    &ARM::GPRRegClass, &ARM::GPRRegClass,
241
242    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
243    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
244    0
245  };
246
247  static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
248    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
249    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
250    &ARM::GPRRegClass,  &ARM::GPRRegClass,
251
252    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
253    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
254    0
255  };
256
257  if (STI.isThumb()) {
258    return STI.isTargetDarwin()
259      ? DarwinThumbCalleeSavedRegClasses : ThumbCalleeSavedRegClasses;
260  }
261  return STI.isTargetDarwin()
262    ? DarwinCalleeSavedRegClasses : CalleeSavedRegClasses;
263}
264
265BitVector ARMBaseRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
266  // FIXME: avoid re-calculating this everytime.
267  BitVector Reserved(getNumRegs());
268  Reserved.set(ARM::SP);
269  Reserved.set(ARM::PC);
270  if (STI.isTargetDarwin() || hasFP(MF))
271    Reserved.set(FramePtr);
272  // Some targets reserve R9.
273  if (STI.isR9Reserved())
274    Reserved.set(ARM::R9);
275  return Reserved;
276}
277
278bool
279ARMBaseRegisterInfo::isReservedReg(const MachineFunction &MF, unsigned Reg) const {
280  switch (Reg) {
281  default: break;
282  case ARM::SP:
283  case ARM::PC:
284    return true;
285  case ARM::R7:
286  case ARM::R11:
287    if (FramePtr == Reg && (STI.isTargetDarwin() || hasFP(MF)))
288      return true;
289    break;
290  case ARM::R9:
291    return STI.isR9Reserved();
292  }
293
294  return false;
295}
296
297const TargetRegisterClass *ARMBaseRegisterInfo::getPointerRegClass() const {
298  return &ARM::GPRRegClass;
299}
300
301/// getAllocationOrder - Returns the register allocation order for a specified
302/// register class in the form of a pair of TargetRegisterClass iterators.
303std::pair<TargetRegisterClass::iterator,TargetRegisterClass::iterator>
304ARMBaseRegisterInfo::getAllocationOrder(const TargetRegisterClass *RC,
305                                        unsigned HintType, unsigned HintReg,
306                                        const MachineFunction &MF) const {
307  // Alternative register allocation orders when favoring even / odd registers
308  // of register pairs.
309
310  // No FP, R9 is available.
311  static const unsigned GPREven1[] = {
312    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8, ARM::R10,
313    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7,
314    ARM::R9, ARM::R11
315  };
316  static const unsigned GPROdd1[] = {
317    ARM::R1, ARM::R3, ARM::R5, ARM::R7, ARM::R9, ARM::R11,
318    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
319    ARM::R8, ARM::R10
320  };
321
322  // FP is R7, R9 is available.
323  static const unsigned GPREven2[] = {
324    ARM::R0, ARM::R2, ARM::R4,          ARM::R8, ARM::R10,
325    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6,
326    ARM::R9, ARM::R11
327  };
328  static const unsigned GPROdd2[] = {
329    ARM::R1, ARM::R3, ARM::R5,          ARM::R9, ARM::R11,
330    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6,
331    ARM::R8, ARM::R10
332  };
333
334  // FP is R11, R9 is available.
335  static const unsigned GPREven3[] = {
336    ARM::R0, ARM::R2, ARM::R4, ARM::R6, ARM::R8,
337    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7,
338    ARM::R9
339  };
340  static const unsigned GPROdd3[] = {
341    ARM::R1, ARM::R3, ARM::R5, ARM::R6, ARM::R9,
342    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R7,
343    ARM::R8
344  };
345
346  // No FP, R9 is not available.
347  static const unsigned GPREven4[] = {
348    ARM::R0, ARM::R2, ARM::R4, ARM::R6,          ARM::R10,
349    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8,
350    ARM::R11
351  };
352  static const unsigned GPROdd4[] = {
353    ARM::R1, ARM::R3, ARM::R5, ARM::R7,          ARM::R11,
354    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
355    ARM::R10
356  };
357
358  // FP is R7, R9 is not available.
359  static const unsigned GPREven5[] = {
360    ARM::R0, ARM::R2, ARM::R4,                   ARM::R10,
361    ARM::R1, ARM::R3, ARM::R12,ARM::LR, ARM::R5, ARM::R6, ARM::R8,
362    ARM::R11
363  };
364  static const unsigned GPROdd5[] = {
365    ARM::R1, ARM::R3, ARM::R5,                   ARM::R11,
366    ARM::R0, ARM::R2, ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8,
367    ARM::R10
368  };
369
370  // FP is R11, R9 is not available.
371  static const unsigned GPREven6[] = {
372    ARM::R0, ARM::R2, ARM::R4, ARM::R6,
373    ARM::R1, ARM::R3, ARM::R10,ARM::R12,ARM::LR, ARM::R5, ARM::R7, ARM::R8
374  };
375  static const unsigned GPROdd6[] = {
376    ARM::R1, ARM::R3, ARM::R5, ARM::R7,
377    ARM::R0, ARM::R2, ARM::R10,ARM::R12,ARM::LR, ARM::R4, ARM::R6, ARM::R8
378  };
379
380
381  if (HintType == ARMRI::RegPairEven) {
382    if (isPhysicalRegister(HintReg) && getRegisterPairEven(HintReg, MF) == 0)
383      // It's no longer possible to fulfill this hint. Return the default
384      // allocation order.
385      return std::make_pair(RC->allocation_order_begin(MF),
386                            RC->allocation_order_end(MF));
387
388    if (!STI.isTargetDarwin() && !hasFP(MF)) {
389      if (!STI.isR9Reserved())
390        return std::make_pair(GPREven1,
391                              GPREven1 + (sizeof(GPREven1)/sizeof(unsigned)));
392      else
393        return std::make_pair(GPREven4,
394                              GPREven4 + (sizeof(GPREven4)/sizeof(unsigned)));
395    } else if (FramePtr == ARM::R7) {
396      if (!STI.isR9Reserved())
397        return std::make_pair(GPREven2,
398                              GPREven2 + (sizeof(GPREven2)/sizeof(unsigned)));
399      else
400        return std::make_pair(GPREven5,
401                              GPREven5 + (sizeof(GPREven5)/sizeof(unsigned)));
402    } else { // FramePtr == ARM::R11
403      if (!STI.isR9Reserved())
404        return std::make_pair(GPREven3,
405                              GPREven3 + (sizeof(GPREven3)/sizeof(unsigned)));
406      else
407        return std::make_pair(GPREven6,
408                              GPREven6 + (sizeof(GPREven6)/sizeof(unsigned)));
409    }
410  } else if (HintType == ARMRI::RegPairOdd) {
411    if (isPhysicalRegister(HintReg) && getRegisterPairOdd(HintReg, MF) == 0)
412      // It's no longer possible to fulfill this hint. Return the default
413      // allocation order.
414      return std::make_pair(RC->allocation_order_begin(MF),
415                            RC->allocation_order_end(MF));
416
417    if (!STI.isTargetDarwin() && !hasFP(MF)) {
418      if (!STI.isR9Reserved())
419        return std::make_pair(GPROdd1,
420                              GPROdd1 + (sizeof(GPROdd1)/sizeof(unsigned)));
421      else
422        return std::make_pair(GPROdd4,
423                              GPROdd4 + (sizeof(GPROdd4)/sizeof(unsigned)));
424    } else if (FramePtr == ARM::R7) {
425      if (!STI.isR9Reserved())
426        return std::make_pair(GPROdd2,
427                              GPROdd2 + (sizeof(GPROdd2)/sizeof(unsigned)));
428      else
429        return std::make_pair(GPROdd5,
430                              GPROdd5 + (sizeof(GPROdd5)/sizeof(unsigned)));
431    } else { // FramePtr == ARM::R11
432      if (!STI.isR9Reserved())
433        return std::make_pair(GPROdd3,
434                              GPROdd3 + (sizeof(GPROdd3)/sizeof(unsigned)));
435      else
436        return std::make_pair(GPROdd6,
437                              GPROdd6 + (sizeof(GPROdd6)/sizeof(unsigned)));
438    }
439  }
440  return std::make_pair(RC->allocation_order_begin(MF),
441                        RC->allocation_order_end(MF));
442}
443
444/// ResolveRegAllocHint - Resolves the specified register allocation hint
445/// to a physical register. Returns the physical register if it is successful.
446unsigned
447ARMBaseRegisterInfo::ResolveRegAllocHint(unsigned Type, unsigned Reg,
448                                         const MachineFunction &MF) const {
449  if (Reg == 0 || !isPhysicalRegister(Reg))
450    return 0;
451  if (Type == 0)
452    return Reg;
453  else if (Type == (unsigned)ARMRI::RegPairOdd)
454    // Odd register.
455    return getRegisterPairOdd(Reg, MF);
456  else if (Type == (unsigned)ARMRI::RegPairEven)
457    // Even register.
458    return getRegisterPairEven(Reg, MF);
459  return 0;
460}
461
462void
463ARMBaseRegisterInfo::UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
464                                        MachineFunction &MF) const {
465  MachineRegisterInfo *MRI = &MF.getRegInfo();
466  std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
467  if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
468       Hint.first == (unsigned)ARMRI::RegPairEven) &&
469      Hint.second && TargetRegisterInfo::isVirtualRegister(Hint.second)) {
470    // If 'Reg' is one of the even / odd register pair and it's now changed
471    // (e.g. coalesced) into a different register. The other register of the
472    // pair allocation hint must be updated to reflect the relationship
473    // change.
474    unsigned OtherReg = Hint.second;
475    Hint = MRI->getRegAllocationHint(OtherReg);
476    if (Hint.second == Reg)
477      // Make sure the pair has not already divorced.
478      MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
479  }
480}
481
482bool
483ARMRegisterInfo::requiresRegisterScavenging(const MachineFunction &MF) const {
484  return true;
485}
486
487/// hasFP - Return true if the specified function should have a dedicated frame
488/// pointer register.  This is true if the function has variable sized allocas
489/// or if frame pointer elimination is disabled.
490///
491bool ARMBaseRegisterInfo::hasFP(const MachineFunction &MF) const {
492  const MachineFrameInfo *MFI = MF.getFrameInfo();
493  return (NoFramePointerElim ||
494          MFI->hasVarSizedObjects() ||
495          MFI->isFrameAddressTaken());
496}
497
498// hasReservedCallFrame - Under normal circumstances, when a frame pointer is
499// not required, we reserve argument space for call sites in the function
500// immediately on entry to the current function. This eliminates the need for
501// add/sub sp brackets around call sites. Returns true if the call frame is
502// included as part of the stack frame.
503bool ARMRegisterInfo::hasReservedCallFrame(MachineFunction &MF) const {
504  const MachineFrameInfo *FFI = MF.getFrameInfo();
505  unsigned CFSize = FFI->getMaxCallFrameSize();
506  // It's not always a good idea to include the call frame as part of the
507  // stack frame. ARM (especially Thumb) has small immediate offset to
508  // address the stack frame. So a large call frame can cause poor codegen
509  // and may even makes it impossible to scavenge a register.
510  if (CFSize >= ((1 << 12) - 1) / 2)  // Half of imm12
511    return false;
512
513  return !MF.getFrameInfo()->hasVarSizedObjects();
514}
515
516/// emitARMRegPlusImmediate - Emits a series of instructions to materialize
517/// a destreg = basereg + immediate in ARM code.
518static
519void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
520                             MachineBasicBlock::iterator &MBBI,
521                             unsigned DestReg, unsigned BaseReg, int NumBytes,
522                             ARMCC::CondCodes Pred, unsigned PredReg,
523                             const TargetInstrInfo &TII,
524                             DebugLoc dl) {
525  bool isSub = NumBytes < 0;
526  if (isSub) NumBytes = -NumBytes;
527
528  while (NumBytes) {
529    unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
530    unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
531    assert(ThisVal && "Didn't extract field correctly");
532
533    // We will handle these bits from offset, clear them.
534    NumBytes &= ~ThisVal;
535
536    // Get the properly encoded SOImmVal field.
537    int SOImmVal = ARM_AM::getSOImmVal(ThisVal);
538    assert(SOImmVal != -1 && "Bit extraction didn't work?");
539
540    // Build the new ADD / SUB.
541    BuildMI(MBB, MBBI, dl, TII.get(isSub ? ARM::SUBri : ARM::ADDri), DestReg)
542      .addReg(BaseReg, RegState::Kill).addImm(SOImmVal)
543      .addImm((unsigned)Pred).addReg(PredReg).addReg(0);
544    BaseReg = DestReg;
545  }
546}
547
548static void
549emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
550             const TargetInstrInfo &TII, DebugLoc dl,
551             int NumBytes,
552             ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) {
553  emitARMRegPlusImmediate(MBB, MBBI, ARM::SP, ARM::SP, NumBytes,
554                          Pred, PredReg, TII, dl);
555}
556
557void ARMRegisterInfo::
558eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
559                              MachineBasicBlock::iterator I) const {
560  if (!hasReservedCallFrame(MF)) {
561    // If we have alloca, convert as follows:
562    // ADJCALLSTACKDOWN -> sub, sp, sp, amount
563    // ADJCALLSTACKUP   -> add, sp, sp, amount
564    MachineInstr *Old = I;
565    DebugLoc dl = Old->getDebugLoc();
566    unsigned Amount = Old->getOperand(0).getImm();
567    if (Amount != 0) {
568      // We need to keep the stack aligned properly.  To do this, we round the
569      // amount of space needed for the outgoing arguments up to the next
570      // alignment boundary.
571      unsigned Align = MF.getTarget().getFrameInfo()->getStackAlignment();
572      Amount = (Amount+Align-1)/Align*Align;
573
574      // Replace the pseudo instruction with a new instruction...
575      unsigned Opc = Old->getOpcode();
576      ARMCC::CondCodes Pred = (ARMCC::CondCodes)Old->getOperand(1).getImm();
577      if (Opc == ARM::ADJCALLSTACKDOWN || Opc == ARM::tADJCALLSTACKDOWN) {
578        // Note: PredReg is operand 2 for ADJCALLSTACKDOWN.
579        unsigned PredReg = Old->getOperand(2).getReg();
580        emitSPUpdate(MBB, I, TII, dl, -Amount, Pred, PredReg);
581      } else {
582        // Note: PredReg is operand 3 for ADJCALLSTACKUP.
583        unsigned PredReg = Old->getOperand(3).getReg();
584        assert(Opc == ARM::ADJCALLSTACKUP || Opc == ARM::tADJCALLSTACKUP);
585        emitSPUpdate(MBB, I, TII, dl, Amount, Pred, PredReg);
586      }
587    }
588  }
589  MBB.erase(I);
590}
591
592/// findScratchRegister - Find a 'free' ARM register. If register scavenger
593/// is not being used, R12 is available. Otherwise, try for a call-clobbered
594/// register first and then a spilled callee-saved register if that fails.
595static
596unsigned findScratchRegister(RegScavenger *RS, const TargetRegisterClass *RC,
597                             ARMFunctionInfo *AFI) {
598  unsigned Reg = RS ? RS->FindUnusedReg(RC, true) : (unsigned) ARM::R12;
599  assert (!AFI->isThumbFunction());
600  if (Reg == 0)
601    // Try a already spilled CS register.
602    Reg = RS->FindUnusedReg(RC, AFI->getSpilledCSRegisters());
603
604  return Reg;
605}
606
607void ARMRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
608                                          int SPAdj, RegScavenger *RS) const{
609  unsigned i = 0;
610  MachineInstr &MI = *II;
611  MachineBasicBlock &MBB = *MI.getParent();
612  MachineFunction &MF = *MBB.getParent();
613  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
614  DebugLoc dl = MI.getDebugLoc();
615
616  while (!MI.getOperand(i).isFI()) {
617    ++i;
618    assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
619  }
620
621  unsigned FrameReg = ARM::SP;
622  int FrameIndex = MI.getOperand(i).getIndex();
623  int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
624               MF.getFrameInfo()->getStackSize() + SPAdj;
625
626  if (AFI->isGPRCalleeSavedArea1Frame(FrameIndex))
627    Offset -= AFI->getGPRCalleeSavedArea1Offset();
628  else if (AFI->isGPRCalleeSavedArea2Frame(FrameIndex))
629    Offset -= AFI->getGPRCalleeSavedArea2Offset();
630  else if (AFI->isDPRCalleeSavedAreaFrame(FrameIndex))
631    Offset -= AFI->getDPRCalleeSavedAreaOffset();
632  else if (hasFP(MF)) {
633    assert(SPAdj == 0 && "Unexpected");
634    // There is alloca()'s in this function, must reference off the frame
635    // pointer instead.
636    FrameReg = getFrameRegister(MF);
637    Offset -= AFI->getFramePtrSpillOffset();
638  }
639
640  unsigned Opcode = MI.getOpcode();
641  const TargetInstrDesc &Desc = MI.getDesc();
642  unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
643  bool isSub = false;
644
645  // Memory operands in inline assembly always use AddrMode2.
646  if (Opcode == ARM::INLINEASM)
647    AddrMode = ARMII::AddrMode2;
648
649  if (Opcode == ARM::ADDri) {
650    Offset += MI.getOperand(i+1).getImm();
651    if (Offset == 0) {
652      // Turn it into a move.
653      MI.setDesc(TII.get(ARM::MOVr));
654      MI.getOperand(i).ChangeToRegister(FrameReg, false);
655      MI.RemoveOperand(i+1);
656      return;
657    } else if (Offset < 0) {
658      Offset = -Offset;
659      isSub = true;
660      MI.setDesc(TII.get(ARM::SUBri));
661    }
662
663    // Common case: small offset, fits into instruction.
664    int ImmedOffset = ARM_AM::getSOImmVal(Offset);
665    if (ImmedOffset != -1) {
666      // Replace the FrameIndex with sp / fp
667      MI.getOperand(i).ChangeToRegister(FrameReg, false);
668      MI.getOperand(i+1).ChangeToImmediate(ImmedOffset);
669      return;
670    }
671
672    // Otherwise, we fallback to common code below to form the imm offset with
673    // a sequence of ADDri instructions.  First though, pull as much of the imm
674    // into this ADDri as possible.
675    unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
676    unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
677
678    // We will handle these bits from offset, clear them.
679    Offset &= ~ThisImmVal;
680
681    // Get the properly encoded SOImmVal field.
682    int ThisSOImmVal = ARM_AM::getSOImmVal(ThisImmVal);
683    assert(ThisSOImmVal != -1 && "Bit extraction didn't work?");
684    MI.getOperand(i+1).ChangeToImmediate(ThisSOImmVal);
685  } else {
686    unsigned ImmIdx = 0;
687    int InstrOffs = 0;
688    unsigned NumBits = 0;
689    unsigned Scale = 1;
690    switch (AddrMode) {
691    case ARMII::AddrMode2: {
692      ImmIdx = i+2;
693      InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
694      if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
695        InstrOffs *= -1;
696      NumBits = 12;
697      break;
698    }
699    case ARMII::AddrMode3: {
700      ImmIdx = i+2;
701      InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
702      if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
703        InstrOffs *= -1;
704      NumBits = 8;
705      break;
706    }
707    case ARMII::AddrMode5: {
708      ImmIdx = i+1;
709      InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
710      if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
711        InstrOffs *= -1;
712      NumBits = 8;
713      Scale = 4;
714      break;
715    }
716    default:
717      assert(0 && "Unsupported addressing mode!");
718      abort();
719      break;
720    }
721
722    Offset += InstrOffs * Scale;
723    assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
724    if (Offset < 0) {
725      Offset = -Offset;
726      isSub = true;
727    }
728
729    // Common case: small offset, fits into instruction.
730    MachineOperand &ImmOp = MI.getOperand(ImmIdx);
731    int ImmedOffset = Offset / Scale;
732    unsigned Mask = (1 << NumBits) - 1;
733    if ((unsigned)Offset <= Mask * Scale) {
734      // Replace the FrameIndex with sp
735      MI.getOperand(i).ChangeToRegister(FrameReg, false);
736      if (isSub)
737        ImmedOffset |= 1 << NumBits;
738      ImmOp.ChangeToImmediate(ImmedOffset);
739      return;
740    }
741
742    // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
743    ImmedOffset = ImmedOffset & Mask;
744    if (isSub)
745      ImmedOffset |= 1 << NumBits;
746    ImmOp.ChangeToImmediate(ImmedOffset);
747    Offset &= ~(Mask*Scale);
748  }
749
750  // If we get here, the immediate doesn't fit into the instruction.  We folded
751  // as much as possible above, handle the rest, providing a register that is
752  // SP+LargeImm.
753  assert(Offset && "This code isn't needed if offset already handled!");
754
755  // Insert a set of r12 with the full address: r12 = sp + offset
756  // If the offset we have is too large to fit into the instruction, we need
757  // to form it with a series of ADDri's.  Do this by taking 8-bit chunks
758  // out of 'Offset'.
759  unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
760  if (ScratchReg == 0)
761    // No register is "free". Scavenge a register.
762    ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
763  int PIdx = MI.findFirstPredOperandIdx();
764  ARMCC::CondCodes Pred = (PIdx == -1)
765    ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
766  unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
767  emitARMRegPlusImmediate(MBB, II, ScratchReg, FrameReg,
768                          isSub ? -Offset : Offset, Pred, PredReg, TII, dl);
769  MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
770}
771
772static unsigned estimateStackSize(MachineFunction &MF, MachineFrameInfo *MFI) {
773  const MachineFrameInfo *FFI = MF.getFrameInfo();
774  int Offset = 0;
775  for (int i = FFI->getObjectIndexBegin(); i != 0; ++i) {
776    int FixedOff = -FFI->getObjectOffset(i);
777    if (FixedOff > Offset) Offset = FixedOff;
778  }
779  for (unsigned i = 0, e = FFI->getObjectIndexEnd(); i != e; ++i) {
780    if (FFI->isDeadObjectIndex(i))
781      continue;
782    Offset += FFI->getObjectSize(i);
783    unsigned Align = FFI->getObjectAlignment(i);
784    // Adjust to alignment boundary
785    Offset = (Offset+Align-1)/Align*Align;
786  }
787  return (unsigned)Offset;
788}
789
790void
791ARMBaseRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
792                                                          RegScavenger *RS) const {
793  // This tells PEI to spill the FP as if it is any other callee-save register
794  // to take advantage the eliminateFrameIndex machinery. This also ensures it
795  // is spilled in the order specified by getCalleeSavedRegs() to make it easier
796  // to combine multiple loads / stores.
797  bool CanEliminateFrame = true;
798  bool CS1Spilled = false;
799  bool LRSpilled = false;
800  unsigned NumGPRSpills = 0;
801  SmallVector<unsigned, 4> UnspilledCS1GPRs;
802  SmallVector<unsigned, 4> UnspilledCS2GPRs;
803  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
804
805  // Don't spill FP if the frame can be eliminated. This is determined
806  // by scanning the callee-save registers to see if any is used.
807  const unsigned *CSRegs = getCalleeSavedRegs();
808  const TargetRegisterClass* const *CSRegClasses = getCalleeSavedRegClasses();
809  for (unsigned i = 0; CSRegs[i]; ++i) {
810    unsigned Reg = CSRegs[i];
811    bool Spilled = false;
812    if (MF.getRegInfo().isPhysRegUsed(Reg)) {
813      AFI->setCSRegisterIsSpilled(Reg);
814      Spilled = true;
815      CanEliminateFrame = false;
816    } else {
817      // Check alias registers too.
818      for (const unsigned *Aliases = getAliasSet(Reg); *Aliases; ++Aliases) {
819        if (MF.getRegInfo().isPhysRegUsed(*Aliases)) {
820          Spilled = true;
821          CanEliminateFrame = false;
822        }
823      }
824    }
825
826    if (CSRegClasses[i] == &ARM::GPRRegClass) {
827      if (Spilled) {
828        NumGPRSpills++;
829
830        if (!STI.isTargetDarwin()) {
831          if (Reg == ARM::LR)
832            LRSpilled = true;
833          CS1Spilled = true;
834          continue;
835        }
836
837        // Keep track if LR and any of R4, R5, R6, and R7 is spilled.
838        switch (Reg) {
839        case ARM::LR:
840          LRSpilled = true;
841          // Fallthrough
842        case ARM::R4:
843        case ARM::R5:
844        case ARM::R6:
845        case ARM::R7:
846          CS1Spilled = true;
847          break;
848        default:
849          break;
850        }
851      } else {
852        if (!STI.isTargetDarwin()) {
853          UnspilledCS1GPRs.push_back(Reg);
854          continue;
855        }
856
857        switch (Reg) {
858        case ARM::R4:
859        case ARM::R5:
860        case ARM::R6:
861        case ARM::R7:
862        case ARM::LR:
863          UnspilledCS1GPRs.push_back(Reg);
864          break;
865        default:
866          UnspilledCS2GPRs.push_back(Reg);
867          break;
868        }
869      }
870    }
871  }
872
873  bool ForceLRSpill = false;
874  if (!LRSpilled && AFI->isThumbFunction()) {
875    unsigned FnSize = TII.GetFunctionSizeInBytes(MF);
876    // Force LR to be spilled if the Thumb function size is > 2048. This enables
877    // use of BL to implement far jump. If it turns out that it's not needed
878    // then the branch fix up path will undo it.
879    if (FnSize >= (1 << 11)) {
880      CanEliminateFrame = false;
881      ForceLRSpill = true;
882    }
883  }
884
885  bool ExtraCSSpill = false;
886  if (!CanEliminateFrame || hasFP(MF)) {
887    AFI->setHasStackFrame(true);
888
889    // If LR is not spilled, but at least one of R4, R5, R6, and R7 is spilled.
890    // Spill LR as well so we can fold BX_RET to the registers restore (LDM).
891    if (!LRSpilled && CS1Spilled) {
892      MF.getRegInfo().setPhysRegUsed(ARM::LR);
893      AFI->setCSRegisterIsSpilled(ARM::LR);
894      NumGPRSpills++;
895      UnspilledCS1GPRs.erase(std::find(UnspilledCS1GPRs.begin(),
896                                    UnspilledCS1GPRs.end(), (unsigned)ARM::LR));
897      ForceLRSpill = false;
898      ExtraCSSpill = true;
899    }
900
901    // Darwin ABI requires FP to point to the stack slot that contains the
902    // previous FP.
903    if (STI.isTargetDarwin() || hasFP(MF)) {
904      MF.getRegInfo().setPhysRegUsed(FramePtr);
905      NumGPRSpills++;
906    }
907
908    // If stack and double are 8-byte aligned and we are spilling an odd number
909    // of GPRs. Spill one extra callee save GPR so we won't have to pad between
910    // the integer and double callee save areas.
911    unsigned TargetAlign = MF.getTarget().getFrameInfo()->getStackAlignment();
912    if (TargetAlign == 8 && (NumGPRSpills & 1)) {
913      if (CS1Spilled && !UnspilledCS1GPRs.empty()) {
914        for (unsigned i = 0, e = UnspilledCS1GPRs.size(); i != e; ++i) {
915          unsigned Reg = UnspilledCS1GPRs[i];
916          // Don't spiil high register if the function is thumb
917          if (!AFI->isThumbFunction() ||
918              isARMLowRegister(Reg) || Reg == ARM::LR) {
919            MF.getRegInfo().setPhysRegUsed(Reg);
920            AFI->setCSRegisterIsSpilled(Reg);
921            if (!isReservedReg(MF, Reg))
922              ExtraCSSpill = true;
923            break;
924          }
925        }
926      } else if (!UnspilledCS2GPRs.empty() &&
927                 !AFI->isThumbFunction()) {
928        unsigned Reg = UnspilledCS2GPRs.front();
929        MF.getRegInfo().setPhysRegUsed(Reg);
930        AFI->setCSRegisterIsSpilled(Reg);
931        if (!isReservedReg(MF, Reg))
932          ExtraCSSpill = true;
933      }
934    }
935
936    // Estimate if we might need to scavenge a register at some point in order
937    // to materialize a stack offset. If so, either spill one additional
938    // callee-saved register or reserve a special spill slot to facilitate
939    // register scavenging.
940    if (RS && !ExtraCSSpill && !AFI->isThumbFunction()) {
941      MachineFrameInfo  *MFI = MF.getFrameInfo();
942      unsigned Size = estimateStackSize(MF, MFI);
943      unsigned Limit = (1 << 12) - 1;
944      for (MachineFunction::iterator BB = MF.begin(),E = MF.end();BB != E; ++BB)
945        for (MachineBasicBlock::iterator I= BB->begin(); I != BB->end(); ++I) {
946          for (unsigned i = 0, e = I->getNumOperands(); i != e; ++i)
947            if (I->getOperand(i).isFI()) {
948              unsigned Opcode = I->getOpcode();
949              const TargetInstrDesc &Desc = TII.get(Opcode);
950              unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
951              if (AddrMode == ARMII::AddrMode3) {
952                Limit = (1 << 8) - 1;
953                goto DoneEstimating;
954              } else if (AddrMode == ARMII::AddrMode5) {
955                unsigned ThisLimit = ((1 << 8) - 1) * 4;
956                if (ThisLimit < Limit)
957                  Limit = ThisLimit;
958              }
959            }
960        }
961    DoneEstimating:
962      if (Size >= Limit) {
963        // If any non-reserved CS register isn't spilled, just spill one or two
964        // extra. That should take care of it!
965        unsigned NumExtras = TargetAlign / 4;
966        SmallVector<unsigned, 2> Extras;
967        while (NumExtras && !UnspilledCS1GPRs.empty()) {
968          unsigned Reg = UnspilledCS1GPRs.back();
969          UnspilledCS1GPRs.pop_back();
970          if (!isReservedReg(MF, Reg)) {
971            Extras.push_back(Reg);
972            NumExtras--;
973          }
974        }
975        while (NumExtras && !UnspilledCS2GPRs.empty()) {
976          unsigned Reg = UnspilledCS2GPRs.back();
977          UnspilledCS2GPRs.pop_back();
978          if (!isReservedReg(MF, Reg)) {
979            Extras.push_back(Reg);
980            NumExtras--;
981          }
982        }
983        if (Extras.size() && NumExtras == 0) {
984          for (unsigned i = 0, e = Extras.size(); i != e; ++i) {
985            MF.getRegInfo().setPhysRegUsed(Extras[i]);
986            AFI->setCSRegisterIsSpilled(Extras[i]);
987          }
988        } else {
989          // Reserve a slot closest to SP or frame pointer.
990          const TargetRegisterClass *RC = &ARM::GPRRegClass;
991          RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
992                                                           RC->getAlignment()));
993        }
994      }
995    }
996  }
997
998  if (ForceLRSpill) {
999    MF.getRegInfo().setPhysRegUsed(ARM::LR);
1000    AFI->setCSRegisterIsSpilled(ARM::LR);
1001    AFI->setLRIsSpilledForFarJump(true);
1002  }
1003}
1004
1005/// Move iterator pass the next bunch of callee save load / store ops for
1006/// the particular spill area (1: integer area 1, 2: integer area 2,
1007/// 3: fp area, 0: don't care).
1008static void movePastCSLoadStoreOps(MachineBasicBlock &MBB,
1009                                   MachineBasicBlock::iterator &MBBI,
1010                                   int Opc, unsigned Area,
1011                                   const ARMSubtarget &STI) {
1012  while (MBBI != MBB.end() &&
1013         MBBI->getOpcode() == Opc && MBBI->getOperand(1).isFI()) {
1014    if (Area != 0) {
1015      bool Done = false;
1016      unsigned Category = 0;
1017      switch (MBBI->getOperand(0).getReg()) {
1018      case ARM::R4:  case ARM::R5:  case ARM::R6: case ARM::R7:
1019      case ARM::LR:
1020        Category = 1;
1021        break;
1022      case ARM::R8:  case ARM::R9:  case ARM::R10: case ARM::R11:
1023        Category = STI.isTargetDarwin() ? 2 : 1;
1024        break;
1025      case ARM::D8:  case ARM::D9:  case ARM::D10: case ARM::D11:
1026      case ARM::D12: case ARM::D13: case ARM::D14: case ARM::D15:
1027        Category = 3;
1028        break;
1029      default:
1030        Done = true;
1031        break;
1032      }
1033      if (Done || Category != Area)
1034        break;
1035    }
1036
1037    ++MBBI;
1038  }
1039}
1040
1041void ARMRegisterInfo::emitPrologue(MachineFunction &MF) const {
1042  MachineBasicBlock &MBB = MF.front();
1043  MachineBasicBlock::iterator MBBI = MBB.begin();
1044  MachineFrameInfo  *MFI = MF.getFrameInfo();
1045  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1046  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1047  unsigned NumBytes = MFI->getStackSize();
1048  const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
1049  DebugLoc dl = (MBBI != MBB.end() ?
1050                 MBBI->getDebugLoc() : DebugLoc::getUnknownLoc());
1051
1052  // Determine the sizes of each callee-save spill areas and record which frame
1053  // belongs to which callee-save spill areas.
1054  unsigned GPRCS1Size = 0, GPRCS2Size = 0, DPRCSSize = 0;
1055  int FramePtrSpillFI = 0;
1056
1057  if (VARegSaveSize)
1058    emitSPUpdate(MBB, MBBI, TII, dl, -VARegSaveSize);
1059
1060  if (!AFI->hasStackFrame()) {
1061    if (NumBytes != 0)
1062      emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
1063    return;
1064  }
1065
1066  for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1067    unsigned Reg = CSI[i].getReg();
1068    int FI = CSI[i].getFrameIdx();
1069    switch (Reg) {
1070    case ARM::R4:
1071    case ARM::R5:
1072    case ARM::R6:
1073    case ARM::R7:
1074    case ARM::LR:
1075      if (Reg == FramePtr)
1076        FramePtrSpillFI = FI;
1077      AFI->addGPRCalleeSavedArea1Frame(FI);
1078      GPRCS1Size += 4;
1079      break;
1080    case ARM::R8:
1081    case ARM::R9:
1082    case ARM::R10:
1083    case ARM::R11:
1084      if (Reg == FramePtr)
1085        FramePtrSpillFI = FI;
1086      if (STI.isTargetDarwin()) {
1087        AFI->addGPRCalleeSavedArea2Frame(FI);
1088        GPRCS2Size += 4;
1089      } else {
1090        AFI->addGPRCalleeSavedArea1Frame(FI);
1091        GPRCS1Size += 4;
1092      }
1093      break;
1094    default:
1095      AFI->addDPRCalleeSavedAreaFrame(FI);
1096      DPRCSSize += 8;
1097    }
1098  }
1099
1100  // Build the new SUBri to adjust SP for integer callee-save spill area 1.
1101  emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS1Size);
1102  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 1, STI);
1103
1104  // Darwin ABI requires FP to point to the stack slot that contains the
1105  // previous FP.
1106  if (STI.isTargetDarwin() || hasFP(MF)) {
1107    MachineInstrBuilder MIB =
1108      BuildMI(MBB, MBBI, dl, TII.get(ARM::ADDri), FramePtr)
1109      .addFrameIndex(FramePtrSpillFI).addImm(0);
1110    AddDefaultCC(AddDefaultPred(MIB));
1111  }
1112
1113  // Build the new SUBri to adjust SP for integer callee-save spill area 2.
1114  emitSPUpdate(MBB, MBBI, TII, dl, -GPRCS2Size);
1115
1116  // Build the new SUBri to adjust SP for FP callee-save spill area.
1117  movePastCSLoadStoreOps(MBB, MBBI, ARM::STR, 2, STI);
1118  emitSPUpdate(MBB, MBBI, TII, dl, -DPRCSSize);
1119
1120  // Determine starting offsets of spill areas.
1121  unsigned DPRCSOffset  = NumBytes - (GPRCS1Size + GPRCS2Size + DPRCSSize);
1122  unsigned GPRCS2Offset = DPRCSOffset + DPRCSSize;
1123  unsigned GPRCS1Offset = GPRCS2Offset + GPRCS2Size;
1124  AFI->setFramePtrSpillOffset(MFI->getObjectOffset(FramePtrSpillFI) + NumBytes);
1125  AFI->setGPRCalleeSavedArea1Offset(GPRCS1Offset);
1126  AFI->setGPRCalleeSavedArea2Offset(GPRCS2Offset);
1127  AFI->setDPRCalleeSavedAreaOffset(DPRCSOffset);
1128
1129  NumBytes = DPRCSOffset;
1130  if (NumBytes) {
1131    // Insert it after all the callee-save spills.
1132    movePastCSLoadStoreOps(MBB, MBBI, ARM::FSTD, 3, STI);
1133    emitSPUpdate(MBB, MBBI, TII, dl, -NumBytes);
1134  }
1135
1136  if (STI.isTargetELF() && hasFP(MF)) {
1137    MFI->setOffsetAdjustment(MFI->getOffsetAdjustment() -
1138                             AFI->getFramePtrSpillOffset());
1139  }
1140
1141  AFI->setGPRCalleeSavedArea1Size(GPRCS1Size);
1142  AFI->setGPRCalleeSavedArea2Size(GPRCS2Size);
1143  AFI->setDPRCalleeSavedAreaSize(DPRCSSize);
1144}
1145
1146static bool isCalleeSavedRegister(unsigned Reg, const unsigned *CSRegs) {
1147  for (unsigned i = 0; CSRegs[i]; ++i)
1148    if (Reg == CSRegs[i])
1149      return true;
1150  return false;
1151}
1152
1153static bool isCSRestore(MachineInstr *MI, const unsigned *CSRegs) {
1154  return ((MI->getOpcode() == ARM::FLDD ||
1155           MI->getOpcode() == ARM::LDR) &&
1156          MI->getOperand(1).isFI() &&
1157          isCalleeSavedRegister(MI->getOperand(0).getReg(), CSRegs));
1158}
1159
1160void ARMRegisterInfo::emitEpilogue(MachineFunction &MF,
1161                                   MachineBasicBlock &MBB) const {
1162  MachineBasicBlock::iterator MBBI = prior(MBB.end());
1163  assert(MBBI->getOpcode() == ARM::BX_RET &&
1164         "Can only insert epilog into returning blocks");
1165  DebugLoc dl = MBBI->getDebugLoc();
1166  MachineFrameInfo *MFI = MF.getFrameInfo();
1167  ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1168  unsigned VARegSaveSize = AFI->getVarArgsRegSaveSize();
1169  int NumBytes = (int)MFI->getStackSize();
1170
1171  if (!AFI->hasStackFrame()) {
1172    if (NumBytes != 0)
1173      emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
1174  } else {
1175    // Unwind MBBI to point to first LDR / FLDD.
1176    const unsigned *CSRegs = getCalleeSavedRegs();
1177    if (MBBI != MBB.begin()) {
1178      do
1179        --MBBI;
1180      while (MBBI != MBB.begin() && isCSRestore(MBBI, CSRegs));
1181      if (!isCSRestore(MBBI, CSRegs))
1182        ++MBBI;
1183    }
1184
1185    // Move SP to start of FP callee save spill area.
1186    NumBytes -= (AFI->getGPRCalleeSavedArea1Size() +
1187                 AFI->getGPRCalleeSavedArea2Size() +
1188                 AFI->getDPRCalleeSavedAreaSize());
1189
1190    // Darwin ABI requires FP to point to the stack slot that contains the
1191    // previous FP.
1192    if ((STI.isTargetDarwin() && NumBytes) || hasFP(MF)) {
1193      NumBytes = AFI->getFramePtrSpillOffset() - NumBytes;
1194      // Reset SP based on frame pointer only if the stack frame extends beyond
1195      // frame pointer stack slot or target is ELF and the function has FP.
1196      if (AFI->getGPRCalleeSavedArea2Size() ||
1197          AFI->getDPRCalleeSavedAreaSize()  ||
1198          AFI->getDPRCalleeSavedAreaOffset()||
1199          hasFP(MF)) {
1200        if (NumBytes)
1201          BuildMI(MBB, MBBI, dl, TII.get(ARM::SUBri), ARM::SP).addReg(FramePtr)
1202            .addImm(NumBytes)
1203            .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1204        else
1205          BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP).addReg(FramePtr)
1206            .addImm((unsigned)ARMCC::AL).addReg(0).addReg(0);
1207      }
1208    } else if (NumBytes) {
1209      emitSPUpdate(MBB, MBBI, TII, dl, NumBytes);
1210    }
1211
1212    // Move SP to start of integer callee save spill area 2.
1213    movePastCSLoadStoreOps(MBB, MBBI, ARM::FLDD, 3, STI);
1214    emitSPUpdate(MBB, MBBI, TII, dl, AFI->getDPRCalleeSavedAreaSize());
1215
1216    // Move SP to start of integer callee save spill area 1.
1217    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 2, STI);
1218    emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea2Size());
1219
1220    // Move SP to SP upon entry to the function.
1221    movePastCSLoadStoreOps(MBB, MBBI, ARM::LDR, 1, STI);
1222    emitSPUpdate(MBB, MBBI, TII, dl, AFI->getGPRCalleeSavedArea1Size());
1223  }
1224
1225  if (VARegSaveSize)
1226    emitSPUpdate(MBB, MBBI, TII, dl, VARegSaveSize);
1227
1228}
1229
1230unsigned ARMBaseRegisterInfo::getRARegister() const {
1231  return ARM::LR;
1232}
1233
1234unsigned ARMBaseRegisterInfo::getFrameRegister(MachineFunction &MF) const {
1235  if (STI.isTargetDarwin() || hasFP(MF))
1236    return FramePtr;
1237  return ARM::SP;
1238}
1239
1240unsigned ARMBaseRegisterInfo::getEHExceptionRegister() const {
1241  assert(0 && "What is the exception register");
1242  return 0;
1243}
1244
1245unsigned ARMBaseRegisterInfo::getEHHandlerRegister() const {
1246  assert(0 && "What is the exception handler register");
1247  return 0;
1248}
1249
1250int ARMBaseRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
1251  return ARMGenRegisterInfo::getDwarfRegNumFull(RegNum, 0);
1252}
1253
1254unsigned ARMBaseRegisterInfo::getRegisterPairEven(unsigned Reg,
1255                                               const MachineFunction &MF) const {
1256  switch (Reg) {
1257  default: break;
1258  // Return 0 if either register of the pair is a special register.
1259  // So no R12, etc.
1260  case ARM::R1:
1261    return ARM::R0;
1262  case ARM::R3:
1263    // FIXME!
1264    return STI.isThumb() ? 0 : ARM::R2;
1265  case ARM::R5:
1266    return ARM::R4;
1267  case ARM::R7:
1268    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R6;
1269  case ARM::R9:
1270    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R8;
1271  case ARM::R11:
1272    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R10;
1273
1274  case ARM::S1:
1275    return ARM::S0;
1276  case ARM::S3:
1277    return ARM::S2;
1278  case ARM::S5:
1279    return ARM::S4;
1280  case ARM::S7:
1281    return ARM::S6;
1282  case ARM::S9:
1283    return ARM::S8;
1284  case ARM::S11:
1285    return ARM::S10;
1286  case ARM::S13:
1287    return ARM::S12;
1288  case ARM::S15:
1289    return ARM::S14;
1290  case ARM::S17:
1291    return ARM::S16;
1292  case ARM::S19:
1293    return ARM::S18;
1294  case ARM::S21:
1295    return ARM::S20;
1296  case ARM::S23:
1297    return ARM::S22;
1298  case ARM::S25:
1299    return ARM::S24;
1300  case ARM::S27:
1301    return ARM::S26;
1302  case ARM::S29:
1303    return ARM::S28;
1304  case ARM::S31:
1305    return ARM::S30;
1306
1307  case ARM::D1:
1308    return ARM::D0;
1309  case ARM::D3:
1310    return ARM::D2;
1311  case ARM::D5:
1312    return ARM::D4;
1313  case ARM::D7:
1314    return ARM::D6;
1315  case ARM::D9:
1316    return ARM::D8;
1317  case ARM::D11:
1318    return ARM::D10;
1319  case ARM::D13:
1320    return ARM::D12;
1321  case ARM::D15:
1322    return ARM::D14;
1323  }
1324
1325  return 0;
1326}
1327
1328unsigned ARMBaseRegisterInfo::getRegisterPairOdd(unsigned Reg,
1329                                             const MachineFunction &MF) const {
1330  switch (Reg) {
1331  default: break;
1332  // Return 0 if either register of the pair is a special register.
1333  // So no R12, etc.
1334  case ARM::R0:
1335    return ARM::R1;
1336  case ARM::R2:
1337    // FIXME!
1338    return STI.isThumb() ? 0 : ARM::R3;
1339  case ARM::R4:
1340    return ARM::R5;
1341  case ARM::R6:
1342    return isReservedReg(MF, ARM::R7)  ? 0 : ARM::R7;
1343  case ARM::R8:
1344    return isReservedReg(MF, ARM::R9)  ? 0 :ARM::R9;
1345  case ARM::R10:
1346    return isReservedReg(MF, ARM::R11) ? 0 : ARM::R11;
1347
1348  case ARM::S0:
1349    return ARM::S1;
1350  case ARM::S2:
1351    return ARM::S3;
1352  case ARM::S4:
1353    return ARM::S5;
1354  case ARM::S6:
1355    return ARM::S7;
1356  case ARM::S8:
1357    return ARM::S9;
1358  case ARM::S10:
1359    return ARM::S11;
1360  case ARM::S12:
1361    return ARM::S13;
1362  case ARM::S14:
1363    return ARM::S15;
1364  case ARM::S16:
1365    return ARM::S17;
1366  case ARM::S18:
1367    return ARM::S19;
1368  case ARM::S20:
1369    return ARM::S21;
1370  case ARM::S22:
1371    return ARM::S23;
1372  case ARM::S24:
1373    return ARM::S25;
1374  case ARM::S26:
1375    return ARM::S27;
1376  case ARM::S28:
1377    return ARM::S29;
1378  case ARM::S30:
1379    return ARM::S31;
1380
1381  case ARM::D0:
1382    return ARM::D1;
1383  case ARM::D2:
1384    return ARM::D3;
1385  case ARM::D4:
1386    return ARM::D5;
1387  case ARM::D6:
1388    return ARM::D7;
1389  case ARM::D8:
1390    return ARM::D9;
1391  case ARM::D10:
1392    return ARM::D11;
1393  case ARM::D12:
1394    return ARM::D13;
1395  case ARM::D14:
1396    return ARM::D15;
1397  }
1398
1399  return 0;
1400}
1401
1402#include "ARMGenRegisterInfo.inc"
1403