ARMInstrThumb.td revision 285830
1//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22def imm_sr_XFORM: SDNodeXForm<imm, [{ 23 unsigned Imm = N->getZExtValue(); 24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32); 25}]>; 26def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 27def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 28 uint64_t Imm = N->getZExtValue(); 29 return Imm > 0 && Imm <= 32; 30}], imm_sr_XFORM> { 31 let PrintMethod = "printThumbSRImm"; 32 let ParserMatchClass = ThumbSRImmAsmOperand; 33} 34 35def imm_comp_XFORM : SDNodeXForm<imm, [{ 36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 37}]>; 38 39def imm0_7_neg : PatLeaf<(i32 imm), [{ 40 return (uint32_t)-N->getZExtValue() < 8; 41}], imm_neg_XFORM>; 42 43def imm0_255_comp : PatLeaf<(i32 imm), [{ 44 return ~((uint32_t)N->getZExtValue()) < 256; 45}]>; 46 47def imm8_255 : ImmLeaf<i32, [{ 48 return Imm >= 8 && Imm < 256; 49}]>; 50def imm8_255_neg : PatLeaf<(i32 imm), [{ 51 unsigned Val = -N->getZExtValue(); 52 return Val >= 8 && Val < 256; 53}], imm_neg_XFORM>; 54 55// Break imm's up into two pieces: an immediate + a left shift. This uses 56// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 57// to get the val/shift pieces. 58def thumb_immshifted : PatLeaf<(imm), [{ 59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 60}]>; 61 62def thumb_immshifted_val : SDNodeXForm<imm, [{ 63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 64 return CurDAG->getTargetConstant(V, MVT::i32); 65}]>; 66 67def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 69 return CurDAG->getTargetConstant(V, MVT::i32); 70}]>; 71 72// Scaled 4 immediate. 73def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 74def t_imm0_1020s4 : Operand<i32> { 75 let PrintMethod = "printThumbS4ImmOperand"; 76 let ParserMatchClass = t_imm0_1020s4_asmoperand; 77 let OperandType = "OPERAND_IMMEDIATE"; 78} 79 80def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 81def t_imm0_508s4 : Operand<i32> { 82 let PrintMethod = "printThumbS4ImmOperand"; 83 let ParserMatchClass = t_imm0_508s4_asmoperand; 84 let OperandType = "OPERAND_IMMEDIATE"; 85} 86// Alias use only, so no printer is necessary. 87def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 88def t_imm0_508s4_neg : Operand<i32> { 89 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 90 let OperandType = "OPERAND_IMMEDIATE"; 91} 92 93// Define Thumb specific addressing modes. 94 95// unsigned 8-bit, 2-scaled memory offset 96class OperandUnsignedOffset_b8s2 : AsmOperandClass { 97 let Name = "UnsignedOffset_b8s2"; 98 let PredicateMethod = "isUnsignedOffset<8, 2>"; 99} 100 101def UnsignedOffset_b8s2 : OperandUnsignedOffset_b8s2; 102 103// thumb style PC relative operand. signed, 8 bits magnitude, 104// two bits shift. can be represented as either [pc, #imm], #imm, 105// or relocatable expression... 106def ThumbMemPC : AsmOperandClass { 107 let Name = "ThumbMemPC"; 108} 109 110let OperandType = "OPERAND_PCREL" in { 111def t_brtarget : Operand<OtherVT> { 112 let EncoderMethod = "getThumbBRTargetOpValue"; 113 let DecoderMethod = "DecodeThumbBROperand"; 114} 115 116// ADR instruction labels. 117def t_adrlabel : Operand<i32> { 118 let EncoderMethod = "getThumbAdrLabelOpValue"; 119 let PrintMethod = "printAdrLabelOperand<2>"; 120 let ParserMatchClass = UnsignedOffset_b8s2; 121} 122 123def t_bcctarget : Operand<i32> { 124 let EncoderMethod = "getThumbBCCTargetOpValue"; 125 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 126} 127 128def t_cbtarget : Operand<i32> { 129 let EncoderMethod = "getThumbCBTargetOpValue"; 130 let DecoderMethod = "DecodeThumbCmpBROperand"; 131} 132 133def t_bltarget : Operand<i32> { 134 let EncoderMethod = "getThumbBLTargetOpValue"; 135 let DecoderMethod = "DecodeThumbBLTargetOperand"; 136} 137 138def t_blxtarget : Operand<i32> { 139 let EncoderMethod = "getThumbBLXTargetOpValue"; 140 let DecoderMethod = "DecodeThumbBLXOffset"; 141} 142 143// t_addrmode_pc := <label> => pc + imm8 * 4 144// 145def t_addrmode_pc : Operand<i32> { 146 let EncoderMethod = "getAddrModePCOpValue"; 147 let DecoderMethod = "DecodeThumbAddrModePC"; 148 let PrintMethod = "printThumbLdrLabelOperand"; 149 let ParserMatchClass = ThumbMemPC; 150} 151} 152 153// t_addrmode_rr := reg + reg 154// 155def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 156def t_addrmode_rr : Operand<i32>, 157 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 158 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 159 let PrintMethod = "printThumbAddrModeRROperand"; 160 let DecoderMethod = "DecodeThumbAddrModeRR"; 161 let ParserMatchClass = t_addrmode_rr_asm_operand; 162 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 163} 164 165// t_addrmode_rrs := reg + reg 166// 167// We use separate scaled versions because the Select* functions need 168// to explicitly check for a matching constant and return false here so that 169// the reg+imm forms will match instead. This is a horrible way to do that, 170// as it forces tight coupling between the methods, but it's how selectiondag 171// currently works. 172def t_addrmode_rrs1 : Operand<i32>, 173 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 174 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 175 let PrintMethod = "printThumbAddrModeRROperand"; 176 let DecoderMethod = "DecodeThumbAddrModeRR"; 177 let ParserMatchClass = t_addrmode_rr_asm_operand; 178 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 179} 180def t_addrmode_rrs2 : Operand<i32>, 181 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 182 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 183 let DecoderMethod = "DecodeThumbAddrModeRR"; 184 let PrintMethod = "printThumbAddrModeRROperand"; 185 let ParserMatchClass = t_addrmode_rr_asm_operand; 186 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 187} 188def t_addrmode_rrs4 : Operand<i32>, 189 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 190 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 191 let DecoderMethod = "DecodeThumbAddrModeRR"; 192 let PrintMethod = "printThumbAddrModeRROperand"; 193 let ParserMatchClass = t_addrmode_rr_asm_operand; 194 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 195} 196 197// t_addrmode_is4 := reg + imm5 * 4 198// 199def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 200def t_addrmode_is4 : Operand<i32>, 201 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 202 let EncoderMethod = "getAddrModeISOpValue"; 203 let DecoderMethod = "DecodeThumbAddrModeIS"; 204 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 205 let ParserMatchClass = t_addrmode_is4_asm_operand; 206 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 207} 208 209// t_addrmode_is2 := reg + imm5 * 2 210// 211def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 212def t_addrmode_is2 : Operand<i32>, 213 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 214 let EncoderMethod = "getAddrModeISOpValue"; 215 let DecoderMethod = "DecodeThumbAddrModeIS"; 216 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 217 let ParserMatchClass = t_addrmode_is2_asm_operand; 218 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 219} 220 221// t_addrmode_is1 := reg + imm5 222// 223def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 224def t_addrmode_is1 : Operand<i32>, 225 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 226 let EncoderMethod = "getAddrModeISOpValue"; 227 let DecoderMethod = "DecodeThumbAddrModeIS"; 228 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 229 let ParserMatchClass = t_addrmode_is1_asm_operand; 230 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 231} 232 233// t_addrmode_sp := sp + imm8 * 4 234// 235// FIXME: This really shouldn't have an explicit SP operand at all. It should 236// be implicit, just like in the instruction encoding itself. 237def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 238def t_addrmode_sp : Operand<i32>, 239 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 240 let EncoderMethod = "getAddrModeThumbSPOpValue"; 241 let DecoderMethod = "DecodeThumbAddrModeSP"; 242 let PrintMethod = "printThumbAddrModeSPOperand"; 243 let ParserMatchClass = t_addrmode_sp_asm_operand; 244 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 245} 246 247//===----------------------------------------------------------------------===// 248// Miscellaneous Instructions. 249// 250 251// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 252// from removing one half of the matched pairs. That breaks PEI, which assumes 253// these will always be in pairs, and asserts if it finds otherwise. Better way? 254let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 255def tADJCALLSTACKUP : 256 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 257 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 258 Requires<[IsThumb, IsThumb1Only]>; 259 260def tADJCALLSTACKDOWN : 261 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 262 [(ARMcallseq_start imm:$amt)]>, 263 Requires<[IsThumb, IsThumb1Only]>; 264} 265 266class T1SystemEncoding<bits<8> opc> 267 : T1Encoding<0b101111> { 268 let Inst{9-8} = 0b11; 269 let Inst{7-0} = opc; 270} 271 272def tHINT : T1pI<(outs), (ins imm0_15:$imm), NoItinerary, "hint", "\t$imm", []>, 273 T1SystemEncoding<0x00>, 274 Requires<[IsThumb, HasV6M]> { 275 bits<4> imm; 276 let Inst{7-4} = imm; 277} 278 279class tHintAlias<string Asm, dag Result> : tInstAlias<Asm, Result> { 280 let Predicates = [IsThumb, HasV6M]; 281} 282 283def : tHintAlias<"nop$p", (tHINT 0, pred:$p)>; // A8.6.110 284def : tHintAlias<"yield$p", (tHINT 1, pred:$p)>; // A8.6.410 285def : tHintAlias<"wfe$p", (tHINT 2, pred:$p)>; // A8.6.408 286def : tHintAlias<"wfi$p", (tHINT 3, pred:$p)>; // A8.6.409 287def : tHintAlias<"sev$p", (tHINT 4, pred:$p)>; // A8.6.157 288def : tInstAlias<"sevl$p", (tHINT 5, pred:$p)> { 289 let Predicates = [IsThumb2, HasV8]; 290} 291def : T2Pat<(int_arm_sevl), (tHINT 5)>; 292 293// The imm operand $val can be used by a debugger to store more information 294// about the breakpoint. 295def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 296 []>, 297 T1Encoding<0b101111> { 298 let Inst{9-8} = 0b10; 299 // A8.6.22 300 bits<8> val; 301 let Inst{7-0} = val; 302} 303 304def tHLT : T1I<(outs), (ins imm0_63:$val), NoItinerary, "hlt\t$val", 305 []>, T1Encoding<0b101110>, Requires<[IsThumb, HasV8]> { 306 let Inst{9-6} = 0b1010; 307 bits<6> val; 308 let Inst{5-0} = val; 309} 310 311def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 312 []>, T1Encoding<0b101101>, Deprecated<HasV8Ops> { 313 bits<1> end; 314 // A8.6.156 315 let Inst{9-5} = 0b10010; 316 let Inst{4} = 1; 317 let Inst{3} = end; 318 let Inst{2-0} = 0b000; 319} 320 321// Change Processor State is a system instruction -- for disassembly only. 322def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 323 NoItinerary, "cps$imod $iflags", []>, 324 T1Misc<0b0110011> { 325 // A8.6.38 & B6.1.1 326 bit imod; 327 bits<3> iflags; 328 329 let Inst{4} = imod; 330 let Inst{3} = 0; 331 let Inst{2-0} = iflags; 332 let DecoderMethod = "DecodeThumbCPS"; 333} 334 335// For both thumb1 and thumb2. 336let isNotDuplicable = 1, isCodeGenOnly = 1 in 337def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 338 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 339 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 340 // A8.6.6 341 bits<3> dst; 342 let Inst{6-3} = 0b1111; // Rm = pc 343 let Inst{2-0} = dst; 344} 345 346// ADD <Rd>, sp, #<imm8> 347// FIXME: This should not be marked as having side effects, and it should be 348// rematerializable. Clearing the side effect bit causes miscompilations, 349// probably because the instruction can be moved around. 350def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 351 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 352 T1Encoding<{1,0,1,0,1,?}>, Sched<[WriteALU]> { 353 // A6.2 & A8.6.8 354 bits<3> dst; 355 bits<8> imm; 356 let Inst{10-8} = dst; 357 let Inst{7-0} = imm; 358 let DecoderMethod = "DecodeThumbAddSpecialReg"; 359} 360 361// ADD sp, sp, #<imm7> 362def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 363 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 364 T1Misc<{0,0,0,0,0,?,?}>, Sched<[WriteALU]> { 365 // A6.2.5 & A8.6.8 366 bits<7> imm; 367 let Inst{6-0} = imm; 368 let DecoderMethod = "DecodeThumbAddSPImm"; 369} 370 371// SUB sp, sp, #<imm7> 372// FIXME: The encoding and the ASM string don't match up. 373def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 374 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 375 T1Misc<{0,0,0,0,1,?,?}>, Sched<[WriteALU]> { 376 // A6.2.5 & A8.6.214 377 bits<7> imm; 378 let Inst{6-0} = imm; 379 let DecoderMethod = "DecodeThumbAddSPImm"; 380} 381 382def : tInstAlias<"add${p} sp, $imm", 383 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 384def : tInstAlias<"add${p} sp, sp, $imm", 385 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 386 387// Can optionally specify SP as a three operand instruction. 388def : tInstAlias<"add${p} sp, sp, $imm", 389 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 390def : tInstAlias<"sub${p} sp, sp, $imm", 391 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 392 393// ADD <Rm>, sp 394def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 395 "add", "\t$Rdn, $sp, $Rn", []>, 396 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 397 // A8.6.9 Encoding T1 398 bits<4> Rdn; 399 let Inst{7} = Rdn{3}; 400 let Inst{6-3} = 0b1101; 401 let Inst{2-0} = Rdn{2-0}; 402 let DecoderMethod = "DecodeThumbAddSPReg"; 403} 404 405// ADD sp, <Rm> 406def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 407 "add", "\t$Rdn, $Rm", []>, 408 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 409 // A8.6.9 Encoding T2 410 bits<4> Rm; 411 let Inst{7} = 1; 412 let Inst{6-3} = Rm; 413 let Inst{2-0} = 0b101; 414 let DecoderMethod = "DecodeThumbAddSPReg"; 415} 416 417//===----------------------------------------------------------------------===// 418// Control Flow Instructions. 419// 420 421// Indirect branches 422let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 423 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 424 T1Special<{1,1,0,?}>, Sched<[WriteBr]> { 425 // A6.2.3 & A8.6.25 426 bits<4> Rm; 427 let Inst{6-3} = Rm; 428 let Inst{2-0} = 0b000; 429 let Unpredictable{2-0} = 0b111; 430 } 431} 432 433let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 434 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 435 [(ARMretflag)], (tBX LR, pred:$p)>, Sched<[WriteBr]>; 436 437 // Alternative return instruction used by vararg functions. 438 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 439 2, IIC_Br, [], 440 (tBX GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 441} 442 443// All calls clobber the non-callee saved registers. SP is marked as a use to 444// prevent stack-pointer assignments that appear immediately before calls from 445// potentially appearing dead. 446let isCall = 1, 447 Defs = [LR], Uses = [SP] in { 448 // Also used for Thumb2 449 def tBL : TIx2<0b11110, 0b11, 1, 450 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br, 451 "bl${p}\t$func", 452 [(ARMtcall tglobaladdr:$func)]>, 453 Requires<[IsThumb]>, Sched<[WriteBrL]> { 454 bits<24> func; 455 let Inst{26} = func{23}; 456 let Inst{25-16} = func{20-11}; 457 let Inst{13} = func{22}; 458 let Inst{11} = func{21}; 459 let Inst{10-0} = func{10-0}; 460 } 461 462 // ARMv5T and above, also used for Thumb2 463 def tBLXi : TIx2<0b11110, 0b11, 0, 464 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br, 465 "blx${p}\t$func", 466 [(ARMcall tglobaladdr:$func)]>, 467 Requires<[IsThumb, HasV5T]>, Sched<[WriteBrL]> { 468 bits<24> func; 469 let Inst{26} = func{23}; 470 let Inst{25-16} = func{20-11}; 471 let Inst{13} = func{22}; 472 let Inst{11} = func{21}; 473 let Inst{10-1} = func{10-1}; 474 let Inst{0} = 0; // func{0} is assumed zero 475 } 476 477 // Also used for Thumb2 478 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 479 "blx${p}\t$func", 480 [(ARMtcall GPR:$func)]>, 481 Requires<[IsThumb, HasV5T]>, 482 T1Special<{1,1,1,?}>, Sched<[WriteBrL]> { // A6.2.3 & A8.6.24; 483 bits<4> func; 484 let Inst{6-3} = func; 485 let Inst{2-0} = 0b000; 486 } 487 488 // ARMv4T 489 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 490 4, IIC_Br, 491 [(ARMcall_nolink tGPR:$func)]>, 492 Requires<[IsThumb, IsThumb1Only]>, Sched<[WriteBr]>; 493} 494 495let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 496 let isPredicable = 1 in 497 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 498 "b", "\t$target", [(br bb:$target)]>, 499 T1Encoding<{1,1,1,0,0,?}>, Sched<[WriteBr]> { 500 bits<11> target; 501 let Inst{10-0} = target; 502 let AsmMatchConverter = "cvtThumbBranches"; 503 } 504 505 // Far jump 506 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 507 // the clobber of LR. 508 let Defs = [LR] in 509 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 510 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>, 511 Sched<[WriteBrTbl]>; 512 513 def tBR_JTr : tPseudoInst<(outs), 514 (ins tGPR:$target, i32imm:$jt, i32imm:$id), 515 0, IIC_Br, 516 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>, 517 Sched<[WriteBrTbl]> { 518 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 519 } 520} 521 522// FIXME: should be able to write a pattern for ARMBrcond, but can't use 523// a two-value operand where a dag node expects two operands. :( 524let isBranch = 1, isTerminator = 1 in 525 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 526 "b${p}\t$target", 527 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 528 T1BranchCond<{1,1,0,1}>, Sched<[WriteBr]> { 529 bits<4> p; 530 bits<8> target; 531 let Inst{11-8} = p; 532 let Inst{7-0} = target; 533 let AsmMatchConverter = "cvtThumbBranches"; 534} 535 536 537// Tail calls 538let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 539 // IOS versions. 540 let Uses = [SP] in { 541 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 542 4, IIC_Br, [], 543 (tBX GPR:$dst, (ops 14, zero_reg))>, 544 Requires<[IsThumb]>, Sched<[WriteBr]>; 545 } 546 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls 547 // on IOS), so it's in ARMInstrThumb2.td. 548 // Non-IOS version: 549 let Uses = [SP] in { 550 def tTAILJMPdND : tPseudoExpand<(outs), 551 (ins t_brtarget:$dst, pred:$p), 552 4, IIC_Br, [], 553 (tB t_brtarget:$dst, pred:$p)>, 554 Requires<[IsThumb, IsNotIOS]>, Sched<[WriteBr]>; 555 } 556} 557 558 559// A8.6.218 Supervisor Call (Software Interrupt) 560// A8.6.16 B: Encoding T1 561// If Inst{11-8} == 0b1111 then SEE SVC 562let isCall = 1, Uses = [SP] in 563def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 564 "svc", "\t$imm", []>, Encoding16, Sched<[WriteBr]> { 565 bits<8> imm; 566 let Inst{15-12} = 0b1101; 567 let Inst{11-8} = 0b1111; 568 let Inst{7-0} = imm; 569} 570 571// The assembler uses 0xDEFE for a trap instruction. 572let isBarrier = 1, isTerminator = 1 in 573def tTRAP : TI<(outs), (ins), IIC_Br, 574 "trap", [(trap)]>, Encoding16, Sched<[WriteBr]> { 575 let Inst = 0xdefe; 576} 577 578//===----------------------------------------------------------------------===// 579// Load Store Instructions. 580// 581 582// Loads: reg/reg and reg/imm5 583let canFoldAsLoad = 1, isReMaterializable = 1 in 584multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 585 Operand AddrMode_r, Operand AddrMode_i, 586 AddrMode am, InstrItinClass itin_r, 587 InstrItinClass itin_i, string asm, 588 PatFrag opnode> { 589 def r : // reg/reg 590 T1pILdStEncode<reg_opc, 591 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 592 am, itin_r, asm, "\t$Rt, $addr", 593 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 594 def i : // reg/imm5 595 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 596 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 597 am, itin_i, asm, "\t$Rt, $addr", 598 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 599} 600// Stores: reg/reg and reg/imm5 601multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 602 Operand AddrMode_r, Operand AddrMode_i, 603 AddrMode am, InstrItinClass itin_r, 604 InstrItinClass itin_i, string asm, 605 PatFrag opnode> { 606 def r : // reg/reg 607 T1pILdStEncode<reg_opc, 608 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 609 am, itin_r, asm, "\t$Rt, $addr", 610 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 611 def i : // reg/imm5 612 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 613 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 614 am, itin_i, asm, "\t$Rt, $addr", 615 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 616} 617 618// A8.6.57 & A8.6.60 619defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, 620 t_addrmode_is4, AddrModeT1_4, 621 IIC_iLoad_r, IIC_iLoad_i, "ldr", 622 UnOpFrag<(load node:$Src)>>; 623 624// A8.6.64 & A8.6.61 625defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1, 626 t_addrmode_is1, AddrModeT1_1, 627 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 628 UnOpFrag<(zextloadi8 node:$Src)>>; 629 630// A8.6.76 & A8.6.73 631defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2, 632 t_addrmode_is2, AddrModeT1_2, 633 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 634 UnOpFrag<(zextloadi16 node:$Src)>>; 635 636let AddedComplexity = 10 in 637def tLDRSB : // A8.6.80 638 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 639 AddrModeT1_1, IIC_iLoad_bh_r, 640 "ldrsb", "\t$Rt, $addr", 641 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 642 643let AddedComplexity = 10 in 644def tLDRSH : // A8.6.84 645 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 646 AddrModeT1_2, IIC_iLoad_bh_r, 647 "ldrsh", "\t$Rt, $addr", 648 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 649 650let canFoldAsLoad = 1 in 651def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 652 "ldr", "\t$Rt, $addr", 653 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 654 T1LdStSP<{1,?,?}> { 655 bits<3> Rt; 656 bits<8> addr; 657 let Inst{10-8} = Rt; 658 let Inst{7-0} = addr; 659} 660 661let canFoldAsLoad = 1, isReMaterializable = 1 in 662def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 663 "ldr", "\t$Rt, $addr", 664 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 665 T1Encoding<{0,1,0,0,1,?}> { 666 // A6.2 & A8.6.59 667 bits<3> Rt; 668 bits<8> addr; 669 let Inst{10-8} = Rt; 670 let Inst{7-0} = addr; 671} 672 673// A8.6.194 & A8.6.192 674defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, 675 t_addrmode_is4, AddrModeT1_4, 676 IIC_iStore_r, IIC_iStore_i, "str", 677 BinOpFrag<(store node:$LHS, node:$RHS)>>; 678 679// A8.6.197 & A8.6.195 680defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1, 681 t_addrmode_is1, AddrModeT1_1, 682 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 683 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 684 685// A8.6.207 & A8.6.205 686defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, 687 t_addrmode_is2, AddrModeT1_2, 688 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 689 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 690 691 692def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 693 "str", "\t$Rt, $addr", 694 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 695 T1LdStSP<{0,?,?}> { 696 bits<3> Rt; 697 bits<8> addr; 698 let Inst{10-8} = Rt; 699 let Inst{7-0} = addr; 700} 701 702//===----------------------------------------------------------------------===// 703// Load / store multiple Instructions. 704// 705 706// These require base address to be written back or one of the loaded regs. 707let neverHasSideEffects = 1 in { 708 709let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 710def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 711 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 712 bits<3> Rn; 713 bits<8> regs; 714 let Inst{10-8} = Rn; 715 let Inst{7-0} = regs; 716} 717 718// Writeback version is just a pseudo, as there's no encoding difference. 719// Writeback happens iff the base register is not in the destination register 720// list. 721def tLDMIA_UPD : 722 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 723 "$Rn = $wb", IIC_iLoad_mu>, 724 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 725 let Size = 2; 726 let OutOperandList = (outs GPR:$wb); 727 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 728 let Pattern = []; 729 let isCodeGenOnly = 1; 730 let isPseudo = 1; 731 list<Predicate> Predicates = [IsThumb]; 732} 733 734// There is no non-writeback version of STM for Thumb. 735let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 736def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 737 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 738 AddrModeNone, 2, IIC_iStore_mu, 739 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 740 T1Encoding<{1,1,0,0,0,?}> { 741 bits<3> Rn; 742 bits<8> regs; 743 let Inst{10-8} = Rn; 744 let Inst{7-0} = regs; 745} 746 747} // neverHasSideEffects 748 749def : InstAlias<"ldm${p} $Rn!, $regs", 750 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, 751 Requires<[IsThumb, IsThumb1Only]>; 752 753let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 754def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 755 IIC_iPop, 756 "pop${p}\t$regs", []>, 757 T1Misc<{1,1,0,?,?,?,?}> { 758 bits<16> regs; 759 let Inst{8} = regs{15}; 760 let Inst{7-0} = regs{7-0}; 761} 762 763let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 764def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 765 IIC_iStore_m, 766 "push${p}\t$regs", []>, 767 T1Misc<{0,1,0,?,?,?,?}> { 768 bits<16> regs; 769 let Inst{8} = regs{14}; 770 let Inst{7-0} = regs{7-0}; 771} 772 773//===----------------------------------------------------------------------===// 774// Arithmetic Instructions. 775// 776 777// Helper classes for encoding T1pI patterns: 778class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 779 string opc, string asm, list<dag> pattern> 780 : T1pI<oops, iops, itin, opc, asm, pattern>, 781 T1DataProcessing<opA> { 782 bits<3> Rm; 783 bits<3> Rn; 784 let Inst{5-3} = Rm; 785 let Inst{2-0} = Rn; 786} 787class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 788 string opc, string asm, list<dag> pattern> 789 : T1pI<oops, iops, itin, opc, asm, pattern>, 790 T1Misc<opA> { 791 bits<3> Rm; 792 bits<3> Rd; 793 let Inst{5-3} = Rm; 794 let Inst{2-0} = Rd; 795} 796 797// Helper classes for encoding T1sI patterns: 798class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 799 string opc, string asm, list<dag> pattern> 800 : T1sI<oops, iops, itin, opc, asm, pattern>, 801 T1DataProcessing<opA> { 802 bits<3> Rd; 803 bits<3> Rn; 804 let Inst{5-3} = Rn; 805 let Inst{2-0} = Rd; 806} 807class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 808 string opc, string asm, list<dag> pattern> 809 : T1sI<oops, iops, itin, opc, asm, pattern>, 810 T1General<opA> { 811 bits<3> Rm; 812 bits<3> Rn; 813 bits<3> Rd; 814 let Inst{8-6} = Rm; 815 let Inst{5-3} = Rn; 816 let Inst{2-0} = Rd; 817} 818class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 819 string opc, string asm, list<dag> pattern> 820 : T1sI<oops, iops, itin, opc, asm, pattern>, 821 T1General<opA> { 822 bits<3> Rd; 823 bits<3> Rm; 824 let Inst{5-3} = Rm; 825 let Inst{2-0} = Rd; 826} 827 828// Helper classes for encoding T1sIt patterns: 829class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 830 string opc, string asm, list<dag> pattern> 831 : T1sIt<oops, iops, itin, opc, asm, pattern>, 832 T1DataProcessing<opA> { 833 bits<3> Rdn; 834 bits<3> Rm; 835 let Inst{5-3} = Rm; 836 let Inst{2-0} = Rdn; 837} 838class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 839 string opc, string asm, list<dag> pattern> 840 : T1sIt<oops, iops, itin, opc, asm, pattern>, 841 T1General<opA> { 842 bits<3> Rdn; 843 bits<8> imm8; 844 let Inst{10-8} = Rdn; 845 let Inst{7-0} = imm8; 846} 847 848// Add with carry register 849let isCommutable = 1, Uses = [CPSR] in 850def tADC : // A8.6.2 851 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 852 "adc", "\t$Rdn, $Rm", 853 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 854 855// Add immediate 856def tADDi3 : // A8.6.4 T1 857 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 858 IIC_iALUi, 859 "add", "\t$Rd, $Rm, $imm3", 860 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]>, 861 Sched<[WriteALU]> { 862 bits<3> imm3; 863 let Inst{8-6} = imm3; 864} 865 866def tADDi8 : // A8.6.4 T2 867 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 868 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 869 "add", "\t$Rdn, $imm8", 870 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>, 871 Sched<[WriteALU]>; 872 873// Add register 874let isCommutable = 1 in 875def tADDrr : // A8.6.6 T1 876 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 877 IIC_iALUr, 878 "add", "\t$Rd, $Rn, $Rm", 879 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 880 881let neverHasSideEffects = 1 in 882def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 883 "add", "\t$Rdn, $Rm", []>, 884 T1Special<{0,0,?,?}>, Sched<[WriteALU]> { 885 // A8.6.6 T2 886 bits<4> Rdn; 887 bits<4> Rm; 888 let Inst{7} = Rdn{3}; 889 let Inst{6-3} = Rm; 890 let Inst{2-0} = Rdn{2-0}; 891} 892 893// AND register 894let isCommutable = 1 in 895def tAND : // A8.6.12 896 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 897 IIC_iBITr, 898 "and", "\t$Rdn, $Rm", 899 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 900 901// ASR immediate 902def tASRri : // A8.6.14 903 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 904 IIC_iMOVsi, 905 "asr", "\t$Rd, $Rm, $imm5", 906 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 907 Sched<[WriteALU]> { 908 bits<5> imm5; 909 let Inst{10-6} = imm5; 910} 911 912// ASR register 913def tASRrr : // A8.6.15 914 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 915 IIC_iMOVsr, 916 "asr", "\t$Rdn, $Rm", 917 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 918 919// BIC register 920def tBIC : // A8.6.20 921 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 922 IIC_iBITr, 923 "bic", "\t$Rdn, $Rm", 924 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>, 925 Sched<[WriteALU]>; 926 927// CMN register 928let isCompare = 1, Defs = [CPSR] in { 929//FIXME: Disable CMN, as CCodes are backwards from compare expectations 930// Compare-to-zero still works out, just not the relationals 931//def tCMN : // A8.6.33 932// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 933// IIC_iCMPr, 934// "cmn", "\t$lhs, $rhs", 935// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 936 937def tCMNz : // A8.6.33 938 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 939 IIC_iCMPr, 940 "cmn", "\t$Rn, $Rm", 941 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>, Sched<[WriteCMP]>; 942 943} // isCompare = 1, Defs = [CPSR] 944 945// CMP immediate 946let isCompare = 1, Defs = [CPSR] in { 947def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 948 "cmp", "\t$Rn, $imm8", 949 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 950 T1General<{1,0,1,?,?}>, Sched<[WriteCMP]> { 951 // A8.6.35 952 bits<3> Rn; 953 bits<8> imm8; 954 let Inst{10-8} = Rn; 955 let Inst{7-0} = imm8; 956} 957 958// CMP register 959def tCMPr : // A8.6.36 T1 960 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 961 IIC_iCMPr, 962 "cmp", "\t$Rn, $Rm", 963 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>, Sched<[WriteCMP]>; 964 965def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 966 "cmp", "\t$Rn, $Rm", []>, 967 T1Special<{0,1,?,?}>, Sched<[WriteCMP]> { 968 // A8.6.36 T2 969 bits<4> Rm; 970 bits<4> Rn; 971 let Inst{7} = Rn{3}; 972 let Inst{6-3} = Rm; 973 let Inst{2-0} = Rn{2-0}; 974} 975} // isCompare = 1, Defs = [CPSR] 976 977 978// XOR register 979let isCommutable = 1 in 980def tEOR : // A8.6.45 981 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 982 IIC_iBITr, 983 "eor", "\t$Rdn, $Rm", 984 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 985 986// LSL immediate 987def tLSLri : // A8.6.88 988 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 989 IIC_iMOVsi, 990 "lsl", "\t$Rd, $Rm, $imm5", 991 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]>, 992 Sched<[WriteALU]> { 993 bits<5> imm5; 994 let Inst{10-6} = imm5; 995} 996 997// LSL register 998def tLSLrr : // A8.6.89 999 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1000 IIC_iMOVsr, 1001 "lsl", "\t$Rdn, $Rm", 1002 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1003 1004// LSR immediate 1005def tLSRri : // A8.6.90 1006 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 1007 IIC_iMOVsi, 1008 "lsr", "\t$Rd, $Rm, $imm5", 1009 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]>, 1010 Sched<[WriteALU]> { 1011 bits<5> imm5; 1012 let Inst{10-6} = imm5; 1013} 1014 1015// LSR register 1016def tLSRrr : // A8.6.91 1017 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1018 IIC_iMOVsr, 1019 "lsr", "\t$Rdn, $Rm", 1020 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1021 1022// Move register 1023let isMoveImm = 1 in 1024def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1025 "mov", "\t$Rd, $imm8", 1026 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1027 T1General<{1,0,0,?,?}>, Sched<[WriteALU]> { 1028 // A8.6.96 1029 bits<3> Rd; 1030 bits<8> imm8; 1031 let Inst{10-8} = Rd; 1032 let Inst{7-0} = imm8; 1033} 1034// Because we have an explicit tMOVSr below, we need an alias to handle 1035// the immediate "movs" form here. Blech. 1036def : tInstAlias <"movs $Rdn, $imm", 1037 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1038 1039// A7-73: MOV(2) - mov setting flag. 1040 1041let neverHasSideEffects = 1 in { 1042def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1043 2, IIC_iMOVr, 1044 "mov", "\t$Rd, $Rm", "", []>, 1045 T1Special<{1,0,?,?}>, Sched<[WriteALU]> { 1046 // A8.6.97 1047 bits<4> Rd; 1048 bits<4> Rm; 1049 let Inst{7} = Rd{3}; 1050 let Inst{6-3} = Rm; 1051 let Inst{2-0} = Rd{2-0}; 1052} 1053let Defs = [CPSR] in 1054def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1055 "movs\t$Rd, $Rm", []>, Encoding16, Sched<[WriteALU]> { 1056 // A8.6.97 1057 bits<3> Rd; 1058 bits<3> Rm; 1059 let Inst{15-6} = 0b0000000000; 1060 let Inst{5-3} = Rm; 1061 let Inst{2-0} = Rd; 1062} 1063} // neverHasSideEffects 1064 1065// Multiply register 1066let isCommutable = 1 in 1067def tMUL : // A8.6.105 T1 1068 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1069 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1070 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1071 T1DataProcessing<0b1101> { 1072 bits<3> Rd; 1073 bits<3> Rn; 1074 let Inst{5-3} = Rn; 1075 let Inst{2-0} = Rd; 1076 let AsmMatchConverter = "cvtThumbMultiply"; 1077} 1078 1079def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1080 pred:$p)>; 1081 1082// Move inverse register 1083def tMVN : // A8.6.107 1084 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1085 "mvn", "\t$Rd, $Rn", 1086 [(set tGPR:$Rd, (not tGPR:$Rn))]>, Sched<[WriteALU]>; 1087 1088// Bitwise or register 1089let isCommutable = 1 in 1090def tORR : // A8.6.114 1091 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1092 IIC_iBITr, 1093 "orr", "\t$Rdn, $Rm", 1094 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>, Sched<[WriteALU]>; 1095 1096// Swaps 1097def tREV : // A8.6.134 1098 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1099 IIC_iUNAr, 1100 "rev", "\t$Rd, $Rm", 1101 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1102 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1103 1104def tREV16 : // A8.6.135 1105 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1106 IIC_iUNAr, 1107 "rev16", "\t$Rd, $Rm", 1108 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1109 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1110 1111def tREVSH : // A8.6.136 1112 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1113 IIC_iUNAr, 1114 "revsh", "\t$Rd, $Rm", 1115 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1116 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1117 1118// Rotate right register 1119def tROR : // A8.6.139 1120 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1121 IIC_iMOVsr, 1122 "ror", "\t$Rdn, $Rm", 1123 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>, 1124 Sched<[WriteALU]>; 1125 1126// Negate register 1127def tRSB : // A8.6.141 1128 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1129 IIC_iALUi, 1130 "rsb", "\t$Rd, $Rn, #0", 1131 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>, Sched<[WriteALU]>; 1132 1133// Subtract with carry register 1134let Uses = [CPSR] in 1135def tSBC : // A8.6.151 1136 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1137 IIC_iALUr, 1138 "sbc", "\t$Rdn, $Rm", 1139 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>, 1140 Sched<[WriteALU]>; 1141 1142// Subtract immediate 1143def tSUBi3 : // A8.6.210 T1 1144 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1145 IIC_iALUi, 1146 "sub", "\t$Rd, $Rm, $imm3", 1147 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]>, 1148 Sched<[WriteALU]> { 1149 bits<3> imm3; 1150 let Inst{8-6} = imm3; 1151} 1152 1153def tSUBi8 : // A8.6.210 T2 1154 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1155 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1156 "sub", "\t$Rdn, $imm8", 1157 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>, 1158 Sched<[WriteALU]>; 1159 1160// Subtract register 1161def tSUBrr : // A8.6.212 1162 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1163 IIC_iALUr, 1164 "sub", "\t$Rd, $Rn, $Rm", 1165 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>, 1166 Sched<[WriteALU]>; 1167 1168// Sign-extend byte 1169def tSXTB : // A8.6.222 1170 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1171 IIC_iUNAr, 1172 "sxtb", "\t$Rd, $Rm", 1173 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1174 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1175 Sched<[WriteALU]>; 1176 1177// Sign-extend short 1178def tSXTH : // A8.6.224 1179 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1180 IIC_iUNAr, 1181 "sxth", "\t$Rd, $Rm", 1182 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1183 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1184 Sched<[WriteALU]>; 1185 1186// Test 1187let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1188def tTST : // A8.6.230 1189 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1190 "tst", "\t$Rn, $Rm", 1191 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>, 1192 Sched<[WriteALU]>; 1193 1194// Zero-extend byte 1195def tUXTB : // A8.6.262 1196 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1197 IIC_iUNAr, 1198 "uxtb", "\t$Rd, $Rm", 1199 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1200 Requires<[IsThumb, IsThumb1Only, HasV6]>, 1201 Sched<[WriteALU]>; 1202 1203// Zero-extend short 1204def tUXTH : // A8.6.264 1205 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1206 IIC_iUNAr, 1207 "uxth", "\t$Rd, $Rm", 1208 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1209 Requires<[IsThumb, IsThumb1Only, HasV6]>, Sched<[WriteALU]>; 1210 1211// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1212// Expanded after instruction selection into a branch sequence. 1213let usesCustomInserter = 1 in // Expanded after instruction selection. 1214 def tMOVCCr_pseudo : 1215 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, cmovpred:$p), 1216 NoItinerary, 1217 [(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, cmovpred:$p))]>; 1218 1219// tLEApcrel - Load a pc-relative address into a register without offending the 1220// assembler. 1221 1222def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1223 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1224 T1Encoding<{1,0,1,0,0,?}>, Sched<[WriteALU]> { 1225 bits<3> Rd; 1226 bits<8> addr; 1227 let Inst{10-8} = Rd; 1228 let Inst{7-0} = addr; 1229 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1230} 1231 1232let neverHasSideEffects = 1, isReMaterializable = 1 in 1233def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1234 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1235 1236let hasSideEffects = 1 in 1237def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1238 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1239 2, IIC_iALUi, []>, Sched<[WriteALU]>; 1240 1241//===----------------------------------------------------------------------===// 1242// TLS Instructions 1243// 1244 1245// __aeabi_read_tp preserves the registers r1-r3. 1246// This is a pseudo inst so that we can get the encoding right, 1247// complete with fixup for the aeabi_read_tp function. 1248let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1249def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1250 [(set R0, ARMthread_pointer)]>, 1251 Sched<[WriteBr]>; 1252 1253//===----------------------------------------------------------------------===// 1254// SJLJ Exception handling intrinsics 1255// 1256 1257// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1258// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1259// from some other function to get here, and we're using the stack frame for the 1260// containing function to save/restore registers, we can't keep anything live in 1261// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1262// tromped upon when we get here from a longjmp(). We force everything out of 1263// registers except for our own input by listing the relevant registers in 1264// Defs. By doing so, we also cause the prologue/epilogue code to actively 1265// preserve all of the callee-saved resgisters, which is exactly what we want. 1266// $val is a scratch register for our use. 1267let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1268 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1269 usesCustomInserter = 1 in 1270def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1271 AddrModeNone, 0, NoItinerary, "","", 1272 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1273 1274// FIXME: Non-IOS version(s) 1275let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1276 Defs = [ R7, LR, SP ] in 1277def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1278 AddrModeNone, 0, IndexModeNone, 1279 Pseudo, NoItinerary, "", "", 1280 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1281 Requires<[IsThumb, IsIOS]>; 1282 1283//===----------------------------------------------------------------------===// 1284// Non-Instruction Patterns 1285// 1286 1287// Comparisons 1288def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1289 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1290def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1291 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1292 1293// Add with carry 1294def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1295 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1296def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1297 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1298def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1299 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1300 1301// Subtract with carry 1302def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1303 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1304def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1305 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1306def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1307 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1308 1309// ConstantPool, GlobalAddress 1310def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 1311def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1312 1313// JumpTable 1314def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1315 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 1316 1317// Direct calls 1318def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1319 Requires<[IsThumb]>; 1320 1321def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1322 Requires<[IsThumb, HasV5T]>; 1323 1324// Indirect calls to ARM routines 1325def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1326 Requires<[IsThumb, HasV5T]>; 1327 1328// zextload i1 -> zextload i8 1329def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), 1330 (tLDRBr t_addrmode_rrs1:$addr)>; 1331def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1332 (tLDRBi t_addrmode_is1:$addr)>; 1333 1334// extload -> zextload 1335def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1336def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1337def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1338def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1339def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>; 1340def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1341 1342// If it's impossible to use [r,r] address mode for sextload, select to 1343// ldr{b|h} + sxt{b|h} instead. 1344def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1345 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1346 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1347def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1348 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, 1349 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1350def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1351 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1352 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1353def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1354 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, 1355 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1356 1357def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1358 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; 1359def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1360 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1361def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1362 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; 1363def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1364 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1365 1366def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1367 (tLDRBi t_addrmode_is1:$src)>; 1368def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src), 1369 (tLDRBr t_addrmode_rrs1:$src)>; 1370def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1371 (tLDRHi t_addrmode_is2:$src)>; 1372def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src), 1373 (tLDRHr t_addrmode_rrs2:$src)>; 1374def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1375 (tLDRi t_addrmode_is4:$src)>; 1376def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src), 1377 (tLDRr t_addrmode_rrs4:$src)>; 1378def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1379 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1380def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val), 1381 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>; 1382def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1383 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1384def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val), 1385 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>; 1386def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1387 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1388def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val), 1389 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>; 1390 1391// Large immediate handling. 1392 1393// Two piece imms. 1394def : T1Pat<(i32 thumb_immshifted:$src), 1395 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1396 (thumb_immshifted_shamt imm:$src))>; 1397 1398def : T1Pat<(i32 imm0_255_comp:$src), 1399 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1400 1401// Pseudo instruction that combines ldr from constpool and add pc. This should 1402// be expanded into two instructions late to allow if-conversion and 1403// scheduling. 1404let isReMaterializable = 1 in 1405def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1406 NoItinerary, 1407 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1408 imm:$cp))]>, 1409 Requires<[IsThumb, IsThumb1Only]>; 1410 1411// Pseudo-instruction for merged POP and return. 1412// FIXME: remove when we have a way to marking a MI with these properties. 1413let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1414 hasExtraDefRegAllocReq = 1 in 1415def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1416 2, IIC_iPop_Br, [], 1417 (tPOP pred:$p, reglist:$regs)>, Sched<[WriteBrL]>; 1418 1419// Indirect branch using "mov pc, $Rm" 1420let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1421 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1422 2, IIC_Br, [(brind GPR:$Rm)], 1423 (tMOVr PC, GPR:$Rm, pred:$p)>, Sched<[WriteBr]>; 1424} 1425 1426 1427// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1428// encoding is available on ARMv6K, but we don't differentiate that finely. 1429def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>; 1430 1431 1432// For round-trip assembly/disassembly, we have to handle a CPS instruction 1433// without any iflags. That's not, strictly speaking, valid syntax, but it's 1434// a useful extension and assembles to defined behaviour (the insn does 1435// nothing). 1436def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1437def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1438 1439// "neg" is and alias for "rsb rd, rn, #0" 1440def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1441 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1442 1443 1444// Implied destination operand forms for shifts. 1445def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1446 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1447def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1448 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1449def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1450 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1451