ARMInstrThumb.td revision 239462
1//===-- ARMInstrThumb.td - Thumb support for ARM -----------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22def imm_sr_XFORM: SDNodeXForm<imm, [{ 23 unsigned Imm = N->getZExtValue(); 24 return CurDAG->getTargetConstant((Imm == 32 ? 0 : Imm), MVT::i32); 25}]>; 26def ThumbSRImmAsmOperand: AsmOperandClass { let Name = "ImmThumbSR"; } 27def imm_sr : Operand<i32>, PatLeaf<(imm), [{ 28 uint64_t Imm = N->getZExtValue(); 29 return Imm > 0 && Imm <= 32; 30}], imm_sr_XFORM> { 31 let PrintMethod = "printThumbSRImm"; 32 let ParserMatchClass = ThumbSRImmAsmOperand; 33} 34 35def imm_comp_XFORM : SDNodeXForm<imm, [{ 36 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 37}]>; 38 39def imm0_7_neg : PatLeaf<(i32 imm), [{ 40 return (uint32_t)-N->getZExtValue() < 8; 41}], imm_neg_XFORM>; 42 43def imm0_255_comp : PatLeaf<(i32 imm), [{ 44 return ~((uint32_t)N->getZExtValue()) < 256; 45}]>; 46 47def imm8_255 : ImmLeaf<i32, [{ 48 return Imm >= 8 && Imm < 256; 49}]>; 50def imm8_255_neg : PatLeaf<(i32 imm), [{ 51 unsigned Val = -N->getZExtValue(); 52 return Val >= 8 && Val < 256; 53}], imm_neg_XFORM>; 54 55// Break imm's up into two pieces: an immediate + a left shift. This uses 56// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 57// to get the val/shift pieces. 58def thumb_immshifted : PatLeaf<(imm), [{ 59 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 60}]>; 61 62def thumb_immshifted_val : SDNodeXForm<imm, [{ 63 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 64 return CurDAG->getTargetConstant(V, MVT::i32); 65}]>; 66 67def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 68 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 69 return CurDAG->getTargetConstant(V, MVT::i32); 70}]>; 71 72// ADR instruction labels. 73def t_adrlabel : Operand<i32> { 74 let EncoderMethod = "getThumbAdrLabelOpValue"; 75} 76 77// Scaled 4 immediate. 78def t_imm0_1020s4_asmoperand: AsmOperandClass { let Name = "Imm0_1020s4"; } 79def t_imm0_1020s4 : Operand<i32> { 80 let PrintMethod = "printThumbS4ImmOperand"; 81 let ParserMatchClass = t_imm0_1020s4_asmoperand; 82 let OperandType = "OPERAND_IMMEDIATE"; 83} 84 85def t_imm0_508s4_asmoperand: AsmOperandClass { let Name = "Imm0_508s4"; } 86def t_imm0_508s4 : Operand<i32> { 87 let PrintMethod = "printThumbS4ImmOperand"; 88 let ParserMatchClass = t_imm0_508s4_asmoperand; 89 let OperandType = "OPERAND_IMMEDIATE"; 90} 91// Alias use only, so no printer is necessary. 92def t_imm0_508s4_neg_asmoperand: AsmOperandClass { let Name = "Imm0_508s4Neg"; } 93def t_imm0_508s4_neg : Operand<i32> { 94 let ParserMatchClass = t_imm0_508s4_neg_asmoperand; 95 let OperandType = "OPERAND_IMMEDIATE"; 96} 97 98// Define Thumb specific addressing modes. 99 100let OperandType = "OPERAND_PCREL" in { 101def t_brtarget : Operand<OtherVT> { 102 let EncoderMethod = "getThumbBRTargetOpValue"; 103 let DecoderMethod = "DecodeThumbBROperand"; 104} 105 106def t_bcctarget : Operand<i32> { 107 let EncoderMethod = "getThumbBCCTargetOpValue"; 108 let DecoderMethod = "DecodeThumbBCCTargetOperand"; 109} 110 111def t_cbtarget : Operand<i32> { 112 let EncoderMethod = "getThumbCBTargetOpValue"; 113 let DecoderMethod = "DecodeThumbCmpBROperand"; 114} 115 116def t_bltarget : Operand<i32> { 117 let EncoderMethod = "getThumbBLTargetOpValue"; 118 let DecoderMethod = "DecodeThumbBLTargetOperand"; 119} 120 121def t_blxtarget : Operand<i32> { 122 let EncoderMethod = "getThumbBLXTargetOpValue"; 123 let DecoderMethod = "DecodeThumbBLXOffset"; 124} 125} 126 127// t_addrmode_rr := reg + reg 128// 129def t_addrmode_rr_asm_operand : AsmOperandClass { let Name = "MemThumbRR"; } 130def t_addrmode_rr : Operand<i32>, 131 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 132 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 133 let PrintMethod = "printThumbAddrModeRROperand"; 134 let DecoderMethod = "DecodeThumbAddrModeRR"; 135 let ParserMatchClass = t_addrmode_rr_asm_operand; 136 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 137} 138 139// t_addrmode_rrs := reg + reg 140// 141// We use separate scaled versions because the Select* functions need 142// to explicitly check for a matching constant and return false here so that 143// the reg+imm forms will match instead. This is a horrible way to do that, 144// as it forces tight coupling between the methods, but it's how selectiondag 145// currently works. 146def t_addrmode_rrs1 : Operand<i32>, 147 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 148 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 149 let PrintMethod = "printThumbAddrModeRROperand"; 150 let DecoderMethod = "DecodeThumbAddrModeRR"; 151 let ParserMatchClass = t_addrmode_rr_asm_operand; 152 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 153} 154def t_addrmode_rrs2 : Operand<i32>, 155 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 156 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 157 let DecoderMethod = "DecodeThumbAddrModeRR"; 158 let PrintMethod = "printThumbAddrModeRROperand"; 159 let ParserMatchClass = t_addrmode_rr_asm_operand; 160 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 161} 162def t_addrmode_rrs4 : Operand<i32>, 163 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 164 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 165 let DecoderMethod = "DecodeThumbAddrModeRR"; 166 let PrintMethod = "printThumbAddrModeRROperand"; 167 let ParserMatchClass = t_addrmode_rr_asm_operand; 168 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 169} 170 171// t_addrmode_is4 := reg + imm5 * 4 172// 173def t_addrmode_is4_asm_operand : AsmOperandClass { let Name = "MemThumbRIs4"; } 174def t_addrmode_is4 : Operand<i32>, 175 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 176 let EncoderMethod = "getAddrModeISOpValue"; 177 let DecoderMethod = "DecodeThumbAddrModeIS"; 178 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 179 let ParserMatchClass = t_addrmode_is4_asm_operand; 180 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 181} 182 183// t_addrmode_is2 := reg + imm5 * 2 184// 185def t_addrmode_is2_asm_operand : AsmOperandClass { let Name = "MemThumbRIs2"; } 186def t_addrmode_is2 : Operand<i32>, 187 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 188 let EncoderMethod = "getAddrModeISOpValue"; 189 let DecoderMethod = "DecodeThumbAddrModeIS"; 190 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 191 let ParserMatchClass = t_addrmode_is2_asm_operand; 192 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 193} 194 195// t_addrmode_is1 := reg + imm5 196// 197def t_addrmode_is1_asm_operand : AsmOperandClass { let Name = "MemThumbRIs1"; } 198def t_addrmode_is1 : Operand<i32>, 199 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 200 let EncoderMethod = "getAddrModeISOpValue"; 201 let DecoderMethod = "DecodeThumbAddrModeIS"; 202 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 203 let ParserMatchClass = t_addrmode_is1_asm_operand; 204 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 205} 206 207// t_addrmode_sp := sp + imm8 * 4 208// 209// FIXME: This really shouldn't have an explicit SP operand at all. It should 210// be implicit, just like in the instruction encoding itself. 211def t_addrmode_sp_asm_operand : AsmOperandClass { let Name = "MemThumbSPI"; } 212def t_addrmode_sp : Operand<i32>, 213 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 214 let EncoderMethod = "getAddrModeThumbSPOpValue"; 215 let DecoderMethod = "DecodeThumbAddrModeSP"; 216 let PrintMethod = "printThumbAddrModeSPOperand"; 217 let ParserMatchClass = t_addrmode_sp_asm_operand; 218 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 219} 220 221// t_addrmode_pc := <label> => pc + imm8 * 4 222// 223def t_addrmode_pc : Operand<i32> { 224 let EncoderMethod = "getAddrModePCOpValue"; 225 let DecoderMethod = "DecodeThumbAddrModePC"; 226} 227 228//===----------------------------------------------------------------------===// 229// Miscellaneous Instructions. 230// 231 232// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 233// from removing one half of the matched pairs. That breaks PEI, which assumes 234// these will always be in pairs, and asserts if it finds otherwise. Better way? 235let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 236def tADJCALLSTACKUP : 237 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 238 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 239 Requires<[IsThumb, IsThumb1Only]>; 240 241def tADJCALLSTACKDOWN : 242 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 243 [(ARMcallseq_start imm:$amt)]>, 244 Requires<[IsThumb, IsThumb1Only]>; 245} 246 247class T1SystemEncoding<bits<8> opc> 248 : T1Encoding<0b101111> { 249 let Inst{9-8} = 0b11; 250 let Inst{7-0} = opc; 251} 252 253def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", []>, 254 T1SystemEncoding<0x00>, // A8.6.110 255 Requires<[IsThumb2]>; 256 257def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", []>, 258 T1SystemEncoding<0x10>, // A8.6.410 259 Requires<[IsThumb2]>; 260 261def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", []>, 262 T1SystemEncoding<0x20>, // A8.6.408 263 Requires<[IsThumb2]>; 264 265def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", []>, 266 T1SystemEncoding<0x30>, // A8.6.409 267 Requires<[IsThumb2]>; 268 269def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", []>, 270 T1SystemEncoding<0x40>, // A8.6.157 271 Requires<[IsThumb2]>; 272 273// The imm operand $val can be used by a debugger to store more information 274// about the breakpoint. 275def tBKPT : T1I<(outs), (ins imm0_255:$val), NoItinerary, "bkpt\t$val", 276 []>, 277 T1Encoding<0b101111> { 278 let Inst{9-8} = 0b10; 279 // A8.6.22 280 bits<8> val; 281 let Inst{7-0} = val; 282} 283 284def tSETEND : T1I<(outs), (ins setend_op:$end), NoItinerary, "setend\t$end", 285 []>, T1Encoding<0b101101> { 286 bits<1> end; 287 // A8.6.156 288 let Inst{9-5} = 0b10010; 289 let Inst{4} = 1; 290 let Inst{3} = end; 291 let Inst{2-0} = 0b000; 292} 293 294// Change Processor State is a system instruction -- for disassembly only. 295def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 296 NoItinerary, "cps$imod $iflags", []>, 297 T1Misc<0b0110011> { 298 // A8.6.38 & B6.1.1 299 bit imod; 300 bits<3> iflags; 301 302 let Inst{4} = imod; 303 let Inst{3} = 0; 304 let Inst{2-0} = iflags; 305 let DecoderMethod = "DecodeThumbCPS"; 306} 307 308// For both thumb1 and thumb2. 309let isNotDuplicable = 1, isCodeGenOnly = 1 in 310def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 311 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 312 T1Special<{0,0,?,?}> { 313 // A8.6.6 314 bits<3> dst; 315 let Inst{6-3} = 0b1111; // Rm = pc 316 let Inst{2-0} = dst; 317} 318 319// ADD <Rd>, sp, #<imm8> 320// FIXME: This should not be marked as having side effects, and it should be 321// rematerializable. Clearing the side effect bit causes miscompilations, 322// probably because the instruction can be moved around. 323def tADDrSPi : T1pI<(outs tGPR:$dst), (ins GPRsp:$sp, t_imm0_1020s4:$imm), 324 IIC_iALUi, "add", "\t$dst, $sp, $imm", []>, 325 T1Encoding<{1,0,1,0,1,?}> { 326 // A6.2 & A8.6.8 327 bits<3> dst; 328 bits<8> imm; 329 let Inst{10-8} = dst; 330 let Inst{7-0} = imm; 331 let DecoderMethod = "DecodeThumbAddSpecialReg"; 332} 333 334// ADD sp, sp, #<imm7> 335def tADDspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 336 IIC_iALUi, "add", "\t$Rdn, $imm", []>, 337 T1Misc<{0,0,0,0,0,?,?}> { 338 // A6.2.5 & A8.6.8 339 bits<7> imm; 340 let Inst{6-0} = imm; 341 let DecoderMethod = "DecodeThumbAddSPImm"; 342} 343 344// SUB sp, sp, #<imm7> 345// FIXME: The encoding and the ASM string don't match up. 346def tSUBspi : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, t_imm0_508s4:$imm), 347 IIC_iALUi, "sub", "\t$Rdn, $imm", []>, 348 T1Misc<{0,0,0,0,1,?,?}> { 349 // A6.2.5 & A8.6.214 350 bits<7> imm; 351 let Inst{6-0} = imm; 352 let DecoderMethod = "DecodeThumbAddSPImm"; 353} 354 355def : tInstAlias<"add${p} sp, $imm", 356 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 357def : tInstAlias<"add${p} sp, sp, $imm", 358 (tSUBspi SP, t_imm0_508s4_neg:$imm, pred:$p)>; 359 360// Can optionally specify SP as a three operand instruction. 361def : tInstAlias<"add${p} sp, sp, $imm", 362 (tADDspi SP, t_imm0_508s4:$imm, pred:$p)>; 363def : tInstAlias<"sub${p} sp, sp, $imm", 364 (tSUBspi SP, t_imm0_508s4:$imm, pred:$p)>; 365 366// ADD <Rm>, sp 367def tADDrSP : T1pI<(outs GPR:$Rdn), (ins GPRsp:$sp, GPR:$Rn), IIC_iALUr, 368 "add", "\t$Rdn, $sp, $Rn", []>, 369 T1Special<{0,0,?,?}> { 370 // A8.6.9 Encoding T1 371 bits<4> Rdn; 372 let Inst{7} = Rdn{3}; 373 let Inst{6-3} = 0b1101; 374 let Inst{2-0} = Rdn{2-0}; 375 let DecoderMethod = "DecodeThumbAddSPReg"; 376} 377 378// ADD sp, <Rm> 379def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr, 380 "add", "\t$Rdn, $Rm", []>, 381 T1Special<{0,0,?,?}> { 382 // A8.6.9 Encoding T2 383 bits<4> Rm; 384 let Inst{7} = 1; 385 let Inst{6-3} = Rm; 386 let Inst{2-0} = 0b101; 387 let DecoderMethod = "DecodeThumbAddSPReg"; 388} 389 390//===----------------------------------------------------------------------===// 391// Control Flow Instructions. 392// 393 394// Indirect branches 395let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 396 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>, 397 T1Special<{1,1,0,?}> { 398 // A6.2.3 & A8.6.25 399 bits<4> Rm; 400 let Inst{6-3} = Rm; 401 let Inst{2-0} = 0b000; 402 let Unpredictable{2-0} = 0b111; 403 } 404} 405 406let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 407 def tBX_RET : tPseudoExpand<(outs), (ins pred:$p), 2, IIC_Br, 408 [(ARMretflag)], (tBX LR, pred:$p)>; 409 410 // Alternative return instruction used by vararg functions. 411 def tBX_RET_vararg : tPseudoExpand<(outs), (ins tGPR:$Rm, pred:$p), 412 2, IIC_Br, [], 413 (tBX GPR:$Rm, pred:$p)>; 414} 415 416// All calls clobber the non-callee saved registers. SP is marked as a use to 417// prevent stack-pointer assignments that appear immediately before calls from 418// potentially appearing dead. 419let isCall = 1, 420 Defs = [LR], Uses = [SP] in { 421 // Also used for Thumb2 422 def tBL : TIx2<0b11110, 0b11, 1, 423 (outs), (ins pred:$p, t_bltarget:$func), IIC_Br, 424 "bl${p}\t$func", 425 [(ARMtcall tglobaladdr:$func)]>, 426 Requires<[IsThumb]> { 427 bits<24> func; 428 let Inst{26} = func{23}; 429 let Inst{25-16} = func{20-11}; 430 let Inst{13} = func{22}; 431 let Inst{11} = func{21}; 432 let Inst{10-0} = func{10-0}; 433 } 434 435 // ARMv5T and above, also used for Thumb2 436 def tBLXi : TIx2<0b11110, 0b11, 0, 437 (outs), (ins pred:$p, t_blxtarget:$func), IIC_Br, 438 "blx${p}\t$func", 439 [(ARMcall tglobaladdr:$func)]>, 440 Requires<[IsThumb, HasV5T]> { 441 bits<24> func; 442 let Inst{26} = func{23}; 443 let Inst{25-16} = func{20-11}; 444 let Inst{13} = func{22}; 445 let Inst{11} = func{21}; 446 let Inst{10-1} = func{10-1}; 447 let Inst{0} = 0; // func{0} is assumed zero 448 } 449 450 // Also used for Thumb2 451 def tBLXr : TI<(outs), (ins pred:$p, GPR:$func), IIC_Br, 452 "blx${p}\t$func", 453 [(ARMtcall GPR:$func)]>, 454 Requires<[IsThumb, HasV5T]>, 455 T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24; 456 bits<4> func; 457 let Inst{6-3} = func; 458 let Inst{2-0} = 0b000; 459 } 460 461 // ARMv4T 462 def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func), 463 4, IIC_Br, 464 [(ARMcall_nolink tGPR:$func)]>, 465 Requires<[IsThumb, IsThumb1Only]>; 466} 467 468let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 469 let isPredicable = 1 in 470 def tB : T1pI<(outs), (ins t_brtarget:$target), IIC_Br, 471 "b", "\t$target", [(br bb:$target)]>, 472 T1Encoding<{1,1,1,0,0,?}> { 473 bits<11> target; 474 let Inst{10-0} = target; 475 } 476 477 // Far jump 478 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 479 // the clobber of LR. 480 let Defs = [LR] in 481 def tBfar : tPseudoExpand<(outs), (ins t_bltarget:$target, pred:$p), 482 4, IIC_Br, [], (tBL pred:$p, t_bltarget:$target)>; 483 484 def tBR_JTr : tPseudoInst<(outs), 485 (ins tGPR:$target, i32imm:$jt, i32imm:$id), 486 0, IIC_Br, 487 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> { 488 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 489 } 490} 491 492// FIXME: should be able to write a pattern for ARMBrcond, but can't use 493// a two-value operand where a dag node expects two operands. :( 494let isBranch = 1, isTerminator = 1 in 495 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 496 "b${p}\t$target", 497 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 498 T1BranchCond<{1,1,0,1}> { 499 bits<4> p; 500 bits<8> target; 501 let Inst{11-8} = p; 502 let Inst{7-0} = target; 503} 504 505// Tail calls 506let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in { 507 // IOS versions. 508 let Uses = [SP] in { 509 def tTAILJMPr : tPseudoExpand<(outs), (ins tcGPR:$dst), 510 4, IIC_Br, [], 511 (tBX GPR:$dst, (ops 14, zero_reg))>, 512 Requires<[IsThumb]>; 513 } 514 // tTAILJMPd: IOS version uses a Thumb2 branch (no Thumb1 tail calls 515 // on IOS), so it's in ARMInstrThumb2.td. 516 // Non-IOS version: 517 let Uses = [SP] in { 518 def tTAILJMPdND : tPseudoExpand<(outs), 519 (ins t_brtarget:$dst, pred:$p), 520 4, IIC_Br, [], 521 (tB t_brtarget:$dst, pred:$p)>, 522 Requires<[IsThumb, IsNotIOS]>; 523 } 524} 525 526 527// A8.6.218 Supervisor Call (Software Interrupt) 528// A8.6.16 B: Encoding T1 529// If Inst{11-8} == 0b1111 then SEE SVC 530let isCall = 1, Uses = [SP] in 531def tSVC : T1pI<(outs), (ins imm0_255:$imm), IIC_Br, 532 "svc", "\t$imm", []>, Encoding16 { 533 bits<8> imm; 534 let Inst{15-12} = 0b1101; 535 let Inst{11-8} = 0b1111; 536 let Inst{7-0} = imm; 537} 538 539// The assembler uses 0xDEFE for a trap instruction. 540let isBarrier = 1, isTerminator = 1 in 541def tTRAP : TI<(outs), (ins), IIC_Br, 542 "trap", [(trap)]>, Encoding16 { 543 let Inst = 0xdefe; 544} 545 546//===----------------------------------------------------------------------===// 547// Load Store Instructions. 548// 549 550// Loads: reg/reg and reg/imm5 551let canFoldAsLoad = 1, isReMaterializable = 1 in 552multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 553 Operand AddrMode_r, Operand AddrMode_i, 554 AddrMode am, InstrItinClass itin_r, 555 InstrItinClass itin_i, string asm, 556 PatFrag opnode> { 557 def r : // reg/reg 558 T1pILdStEncode<reg_opc, 559 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 560 am, itin_r, asm, "\t$Rt, $addr", 561 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 562 def i : // reg/imm5 563 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 564 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 565 am, itin_i, asm, "\t$Rt, $addr", 566 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 567} 568// Stores: reg/reg and reg/imm5 569multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 570 Operand AddrMode_r, Operand AddrMode_i, 571 AddrMode am, InstrItinClass itin_r, 572 InstrItinClass itin_i, string asm, 573 PatFrag opnode> { 574 def r : // reg/reg 575 T1pILdStEncode<reg_opc, 576 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 577 am, itin_r, asm, "\t$Rt, $addr", 578 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 579 def i : // reg/imm5 580 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 581 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 582 am, itin_i, asm, "\t$Rt, $addr", 583 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 584} 585 586// A8.6.57 & A8.6.60 587defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, 588 t_addrmode_is4, AddrModeT1_4, 589 IIC_iLoad_r, IIC_iLoad_i, "ldr", 590 UnOpFrag<(load node:$Src)>>; 591 592// A8.6.64 & A8.6.61 593defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1, 594 t_addrmode_is1, AddrModeT1_1, 595 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 596 UnOpFrag<(zextloadi8 node:$Src)>>; 597 598// A8.6.76 & A8.6.73 599defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2, 600 t_addrmode_is2, AddrModeT1_2, 601 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 602 UnOpFrag<(zextloadi16 node:$Src)>>; 603 604let AddedComplexity = 10 in 605def tLDRSB : // A8.6.80 606 T1pILdStEncode<0b011, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 607 AddrModeT1_1, IIC_iLoad_bh_r, 608 "ldrsb", "\t$Rt, $addr", 609 [(set tGPR:$Rt, (sextloadi8 t_addrmode_rr:$addr))]>; 610 611let AddedComplexity = 10 in 612def tLDRSH : // A8.6.84 613 T1pILdStEncode<0b111, (outs tGPR:$Rt), (ins t_addrmode_rr:$addr), 614 AddrModeT1_2, IIC_iLoad_bh_r, 615 "ldrsh", "\t$Rt, $addr", 616 [(set tGPR:$Rt, (sextloadi16 t_addrmode_rr:$addr))]>; 617 618let canFoldAsLoad = 1 in 619def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 620 "ldr", "\t$Rt, $addr", 621 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 622 T1LdStSP<{1,?,?}> { 623 bits<3> Rt; 624 bits<8> addr; 625 let Inst{10-8} = Rt; 626 let Inst{7-0} = addr; 627} 628 629// Load tconstpool 630// FIXME: Use ldr.n to work around a darwin assembler bug. 631let canFoldAsLoad = 1, isReMaterializable = 1, isCodeGenOnly = 1 in 632def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 633 "ldr", ".n\t$Rt, $addr", 634 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 635 T1Encoding<{0,1,0,0,1,?}> { 636 // A6.2 & A8.6.59 637 bits<3> Rt; 638 bits<8> addr; 639 let Inst{10-8} = Rt; 640 let Inst{7-0} = addr; 641} 642 643// FIXME: Remove this entry when the above ldr.n workaround is fixed. 644// For assembly/disassembly use only. 645def tLDRpciASM : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 646 "ldr", "\t$Rt, $addr", []>, 647 T1Encoding<{0,1,0,0,1,?}> { 648 // A6.2 & A8.6.59 649 bits<3> Rt; 650 bits<8> addr; 651 let Inst{10-8} = Rt; 652 let Inst{7-0} = addr; 653} 654 655// A8.6.194 & A8.6.192 656defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, 657 t_addrmode_is4, AddrModeT1_4, 658 IIC_iStore_r, IIC_iStore_i, "str", 659 BinOpFrag<(store node:$LHS, node:$RHS)>>; 660 661// A8.6.197 & A8.6.195 662defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1, 663 t_addrmode_is1, AddrModeT1_1, 664 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 665 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 666 667// A8.6.207 & A8.6.205 668defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, 669 t_addrmode_is2, AddrModeT1_2, 670 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 671 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 672 673 674def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 675 "str", "\t$Rt, $addr", 676 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 677 T1LdStSP<{0,?,?}> { 678 bits<3> Rt; 679 bits<8> addr; 680 let Inst{10-8} = Rt; 681 let Inst{7-0} = addr; 682} 683 684//===----------------------------------------------------------------------===// 685// Load / store multiple Instructions. 686// 687 688// These require base address to be written back or one of the loaded regs. 689let neverHasSideEffects = 1 in { 690 691let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 692def tLDMIA : T1I<(outs), (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 693 IIC_iLoad_m, "ldm${p}\t$Rn, $regs", []>, T1Encoding<{1,1,0,0,1,?}> { 694 bits<3> Rn; 695 bits<8> regs; 696 let Inst{10-8} = Rn; 697 let Inst{7-0} = regs; 698} 699 700// Writeback version is just a pseudo, as there's no encoding difference. 701// Writeback happens iff the base register is not in the destination register 702// list. 703def tLDMIA_UPD : 704 InstTemplate<AddrModeNone, 0, IndexModeNone, Pseudo, GenericDomain, 705 "$Rn = $wb", IIC_iLoad_mu>, 706 PseudoInstExpansion<(tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)> { 707 let Size = 2; 708 let OutOperandList = (outs GPR:$wb); 709 let InOperandList = (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops); 710 let Pattern = []; 711 let isCodeGenOnly = 1; 712 let isPseudo = 1; 713 list<Predicate> Predicates = [IsThumb]; 714} 715 716// There is no non-writeback version of STM for Thumb. 717let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 718def tSTMIA_UPD : Thumb1I<(outs GPR:$wb), 719 (ins tGPR:$Rn, pred:$p, reglist:$regs, variable_ops), 720 AddrModeNone, 2, IIC_iStore_mu, 721 "stm${p}\t$Rn!, $regs", "$Rn = $wb", []>, 722 T1Encoding<{1,1,0,0,0,?}> { 723 bits<3> Rn; 724 bits<8> regs; 725 let Inst{10-8} = Rn; 726 let Inst{7-0} = regs; 727} 728 729} // neverHasSideEffects 730 731def : InstAlias<"ldm${p} $Rn!, $regs", 732 (tLDMIA tGPR:$Rn, pred:$p, reglist:$regs)>, 733 Requires<[IsThumb, IsThumb1Only]>; 734 735let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 736def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 737 IIC_iPop, 738 "pop${p}\t$regs", []>, 739 T1Misc<{1,1,0,?,?,?,?}> { 740 bits<16> regs; 741 let Inst{8} = regs{15}; 742 let Inst{7-0} = regs{7-0}; 743} 744 745let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 746def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 747 IIC_iStore_m, 748 "push${p}\t$regs", []>, 749 T1Misc<{0,1,0,?,?,?,?}> { 750 bits<16> regs; 751 let Inst{8} = regs{14}; 752 let Inst{7-0} = regs{7-0}; 753} 754 755//===----------------------------------------------------------------------===// 756// Arithmetic Instructions. 757// 758 759// Helper classes for encoding T1pI patterns: 760class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 761 string opc, string asm, list<dag> pattern> 762 : T1pI<oops, iops, itin, opc, asm, pattern>, 763 T1DataProcessing<opA> { 764 bits<3> Rm; 765 bits<3> Rn; 766 let Inst{5-3} = Rm; 767 let Inst{2-0} = Rn; 768} 769class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 770 string opc, string asm, list<dag> pattern> 771 : T1pI<oops, iops, itin, opc, asm, pattern>, 772 T1Misc<opA> { 773 bits<3> Rm; 774 bits<3> Rd; 775 let Inst{5-3} = Rm; 776 let Inst{2-0} = Rd; 777} 778 779// Helper classes for encoding T1sI patterns: 780class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 781 string opc, string asm, list<dag> pattern> 782 : T1sI<oops, iops, itin, opc, asm, pattern>, 783 T1DataProcessing<opA> { 784 bits<3> Rd; 785 bits<3> Rn; 786 let Inst{5-3} = Rn; 787 let Inst{2-0} = Rd; 788} 789class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 790 string opc, string asm, list<dag> pattern> 791 : T1sI<oops, iops, itin, opc, asm, pattern>, 792 T1General<opA> { 793 bits<3> Rm; 794 bits<3> Rn; 795 bits<3> Rd; 796 let Inst{8-6} = Rm; 797 let Inst{5-3} = Rn; 798 let Inst{2-0} = Rd; 799} 800class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 801 string opc, string asm, list<dag> pattern> 802 : T1sI<oops, iops, itin, opc, asm, pattern>, 803 T1General<opA> { 804 bits<3> Rd; 805 bits<3> Rm; 806 let Inst{5-3} = Rm; 807 let Inst{2-0} = Rd; 808} 809 810// Helper classes for encoding T1sIt patterns: 811class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 812 string opc, string asm, list<dag> pattern> 813 : T1sIt<oops, iops, itin, opc, asm, pattern>, 814 T1DataProcessing<opA> { 815 bits<3> Rdn; 816 bits<3> Rm; 817 let Inst{5-3} = Rm; 818 let Inst{2-0} = Rdn; 819} 820class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 821 string opc, string asm, list<dag> pattern> 822 : T1sIt<oops, iops, itin, opc, asm, pattern>, 823 T1General<opA> { 824 bits<3> Rdn; 825 bits<8> imm8; 826 let Inst{10-8} = Rdn; 827 let Inst{7-0} = imm8; 828} 829 830// Add with carry register 831let isCommutable = 1, Uses = [CPSR] in 832def tADC : // A8.6.2 833 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 834 "adc", "\t$Rdn, $Rm", 835 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>; 836 837// Add immediate 838def tADDi3 : // A8.6.4 T1 839 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 840 IIC_iALUi, 841 "add", "\t$Rd, $Rm, $imm3", 842 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> { 843 bits<3> imm3; 844 let Inst{8-6} = imm3; 845} 846 847def tADDi8 : // A8.6.4 T2 848 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), 849 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 850 "add", "\t$Rdn, $imm8", 851 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>; 852 853// Add register 854let isCommutable = 1 in 855def tADDrr : // A8.6.6 T1 856 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 857 IIC_iALUr, 858 "add", "\t$Rd, $Rn, $Rm", 859 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>; 860 861let neverHasSideEffects = 1 in 862def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 863 "add", "\t$Rdn, $Rm", []>, 864 T1Special<{0,0,?,?}> { 865 // A8.6.6 T2 866 bits<4> Rdn; 867 bits<4> Rm; 868 let Inst{7} = Rdn{3}; 869 let Inst{6-3} = Rm; 870 let Inst{2-0} = Rdn{2-0}; 871} 872 873// AND register 874let isCommutable = 1 in 875def tAND : // A8.6.12 876 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 877 IIC_iBITr, 878 "and", "\t$Rdn, $Rm", 879 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>; 880 881// ASR immediate 882def tASRri : // A8.6.14 883 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 884 IIC_iMOVsi, 885 "asr", "\t$Rd, $Rm, $imm5", 886 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm_sr:$imm5)))]> { 887 bits<5> imm5; 888 let Inst{10-6} = imm5; 889} 890 891// ASR register 892def tASRrr : // A8.6.15 893 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 894 IIC_iMOVsr, 895 "asr", "\t$Rdn, $Rm", 896 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>; 897 898// BIC register 899def tBIC : // A8.6.20 900 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 901 IIC_iBITr, 902 "bic", "\t$Rdn, $Rm", 903 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>; 904 905// CMN register 906let isCompare = 1, Defs = [CPSR] in { 907//FIXME: Disable CMN, as CCodes are backwards from compare expectations 908// Compare-to-zero still works out, just not the relationals 909//def tCMN : // A8.6.33 910// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 911// IIC_iCMPr, 912// "cmn", "\t$lhs, $rhs", 913// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 914 915def tCMNz : // A8.6.33 916 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 917 IIC_iCMPr, 918 "cmn", "\t$Rn, $Rm", 919 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>; 920 921} // isCompare = 1, Defs = [CPSR] 922 923// CMP immediate 924let isCompare = 1, Defs = [CPSR] in { 925def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, imm0_255:$imm8), IIC_iCMPi, 926 "cmp", "\t$Rn, $imm8", 927 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 928 T1General<{1,0,1,?,?}> { 929 // A8.6.35 930 bits<3> Rn; 931 bits<8> imm8; 932 let Inst{10-8} = Rn; 933 let Inst{7-0} = imm8; 934} 935 936// CMP register 937def tCMPr : // A8.6.36 T1 938 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 939 IIC_iCMPr, 940 "cmp", "\t$Rn, $Rm", 941 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>; 942 943def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 944 "cmp", "\t$Rn, $Rm", []>, 945 T1Special<{0,1,?,?}> { 946 // A8.6.36 T2 947 bits<4> Rm; 948 bits<4> Rn; 949 let Inst{7} = Rn{3}; 950 let Inst{6-3} = Rm; 951 let Inst{2-0} = Rn{2-0}; 952} 953} // isCompare = 1, Defs = [CPSR] 954 955 956// XOR register 957let isCommutable = 1 in 958def tEOR : // A8.6.45 959 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 960 IIC_iBITr, 961 "eor", "\t$Rdn, $Rm", 962 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>; 963 964// LSL immediate 965def tLSLri : // A8.6.88 966 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_31:$imm5), 967 IIC_iMOVsi, 968 "lsl", "\t$Rd, $Rm, $imm5", 969 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> { 970 bits<5> imm5; 971 let Inst{10-6} = imm5; 972} 973 974// LSL register 975def tLSLrr : // A8.6.89 976 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 977 IIC_iMOVsr, 978 "lsl", "\t$Rdn, $Rm", 979 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>; 980 981// LSR immediate 982def tLSRri : // A8.6.90 983 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, imm_sr:$imm5), 984 IIC_iMOVsi, 985 "lsr", "\t$Rd, $Rm, $imm5", 986 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm_sr:$imm5)))]> { 987 bits<5> imm5; 988 let Inst{10-6} = imm5; 989} 990 991// LSR register 992def tLSRrr : // A8.6.91 993 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 994 IIC_iMOVsr, 995 "lsr", "\t$Rdn, $Rm", 996 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>; 997 998// Move register 999let isMoveImm = 1 in 1000def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins imm0_255:$imm8), IIC_iMOVi, 1001 "mov", "\t$Rd, $imm8", 1002 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1003 T1General<{1,0,0,?,?}> { 1004 // A8.6.96 1005 bits<3> Rd; 1006 bits<8> imm8; 1007 let Inst{10-8} = Rd; 1008 let Inst{7-0} = imm8; 1009} 1010// Because we have an explicit tMOVSr below, we need an alias to handle 1011// the immediate "movs" form here. Blech. 1012def : tInstAlias <"movs $Rdn, $imm", 1013 (tMOVi8 tGPR:$Rdn, CPSR, imm0_255:$imm, 14, 0)>; 1014 1015// A7-73: MOV(2) - mov setting flag. 1016 1017let neverHasSideEffects = 1 in { 1018def tMOVr : Thumb1pI<(outs GPR:$Rd), (ins GPR:$Rm), AddrModeNone, 1019 2, IIC_iMOVr, 1020 "mov", "\t$Rd, $Rm", "", []>, 1021 T1Special<{1,0,?,?}> { 1022 // A8.6.97 1023 bits<4> Rd; 1024 bits<4> Rm; 1025 let Inst{7} = Rd{3}; 1026 let Inst{6-3} = Rm; 1027 let Inst{2-0} = Rd{2-0}; 1028} 1029let Defs = [CPSR] in 1030def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1031 "movs\t$Rd, $Rm", []>, Encoding16 { 1032 // A8.6.97 1033 bits<3> Rd; 1034 bits<3> Rm; 1035 let Inst{15-6} = 0b0000000000; 1036 let Inst{5-3} = Rm; 1037 let Inst{2-0} = Rd; 1038} 1039} // neverHasSideEffects 1040 1041// Multiply register 1042let isCommutable = 1 in 1043def tMUL : // A8.6.105 T1 1044 Thumb1sI<(outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), AddrModeNone, 2, 1045 IIC_iMUL32, "mul", "\t$Rd, $Rn, $Rm", "$Rm = $Rd", 1046 [(set tGPR:$Rd, (mul tGPR:$Rn, tGPR:$Rm))]>, 1047 T1DataProcessing<0b1101> { 1048 bits<3> Rd; 1049 bits<3> Rn; 1050 let Inst{5-3} = Rn; 1051 let Inst{2-0} = Rd; 1052 let AsmMatchConverter = "cvtThumbMultiply"; 1053} 1054 1055def :tInstAlias<"mul${s}${p} $Rdm, $Rn", (tMUL tGPR:$Rdm, s_cc_out:$s, tGPR:$Rn, 1056 pred:$p)>; 1057 1058// Move inverse register 1059def tMVN : // A8.6.107 1060 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1061 "mvn", "\t$Rd, $Rn", 1062 [(set tGPR:$Rd, (not tGPR:$Rn))]>; 1063 1064// Bitwise or register 1065let isCommutable = 1 in 1066def tORR : // A8.6.114 1067 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1068 IIC_iBITr, 1069 "orr", "\t$Rdn, $Rm", 1070 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>; 1071 1072// Swaps 1073def tREV : // A8.6.134 1074 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1075 IIC_iUNAr, 1076 "rev", "\t$Rd, $Rm", 1077 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1078 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1079 1080def tREV16 : // A8.6.135 1081 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1082 IIC_iUNAr, 1083 "rev16", "\t$Rd, $Rm", 1084 [(set tGPR:$Rd, (rotr (bswap tGPR:$Rm), (i32 16)))]>, 1085 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1086 1087def tREVSH : // A8.6.136 1088 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1089 IIC_iUNAr, 1090 "revsh", "\t$Rd, $Rm", 1091 [(set tGPR:$Rd, (sra (bswap tGPR:$Rm), (i32 16)))]>, 1092 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1093 1094// Rotate right register 1095def tROR : // A8.6.139 1096 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1097 IIC_iMOVsr, 1098 "ror", "\t$Rdn, $Rm", 1099 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>; 1100 1101// Negate register 1102def tRSB : // A8.6.141 1103 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1104 IIC_iALUi, 1105 "rsb", "\t$Rd, $Rn, #0", 1106 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>; 1107 1108// Subtract with carry register 1109let Uses = [CPSR] in 1110def tSBC : // A8.6.151 1111 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1112 IIC_iALUr, 1113 "sbc", "\t$Rdn, $Rm", 1114 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>; 1115 1116// Subtract immediate 1117def tSUBi3 : // A8.6.210 T1 1118 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, imm0_7:$imm3), 1119 IIC_iALUi, 1120 "sub", "\t$Rd, $Rm, $imm3", 1121 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> { 1122 bits<3> imm3; 1123 let Inst{8-6} = imm3; 1124} 1125 1126def tSUBi8 : // A8.6.210 T2 1127 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), 1128 (ins tGPR:$Rn, imm0_255:$imm8), IIC_iALUi, 1129 "sub", "\t$Rdn, $imm8", 1130 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>; 1131 1132// Subtract register 1133def tSUBrr : // A8.6.212 1134 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1135 IIC_iALUr, 1136 "sub", "\t$Rd, $Rn, $Rm", 1137 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>; 1138 1139// Sign-extend byte 1140def tSXTB : // A8.6.222 1141 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1142 IIC_iUNAr, 1143 "sxtb", "\t$Rd, $Rm", 1144 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1145 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1146 1147// Sign-extend short 1148def tSXTH : // A8.6.224 1149 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1150 IIC_iUNAr, 1151 "sxth", "\t$Rd, $Rm", 1152 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1153 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1154 1155// Test 1156let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1157def tTST : // A8.6.230 1158 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1159 "tst", "\t$Rn, $Rm", 1160 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>; 1161 1162// Zero-extend byte 1163def tUXTB : // A8.6.262 1164 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1165 IIC_iUNAr, 1166 "uxtb", "\t$Rd, $Rm", 1167 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1168 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1169 1170// Zero-extend short 1171def tUXTH : // A8.6.264 1172 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1173 IIC_iUNAr, 1174 "uxth", "\t$Rd, $Rm", 1175 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1176 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1177 1178// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1179// Expanded after instruction selection into a branch sequence. 1180let usesCustomInserter = 1 in // Expanded after instruction selection. 1181 def tMOVCCr_pseudo : 1182 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 1183 NoItinerary, 1184 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 1185 1186// tLEApcrel - Load a pc-relative address into a register without offending the 1187// assembler. 1188 1189def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1190 IIC_iALUi, "adr{$p}\t$Rd, $addr", []>, 1191 T1Encoding<{1,0,1,0,0,?}> { 1192 bits<3> Rd; 1193 bits<8> addr; 1194 let Inst{10-8} = Rd; 1195 let Inst{7-0} = addr; 1196 let DecoderMethod = "DecodeThumbAddSpecialReg"; 1197} 1198 1199let neverHasSideEffects = 1, isReMaterializable = 1 in 1200def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1201 2, IIC_iALUi, []>; 1202 1203def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1204 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1205 2, IIC_iALUi, []>; 1206 1207//===----------------------------------------------------------------------===// 1208// TLS Instructions 1209// 1210 1211// __aeabi_read_tp preserves the registers r1-r3. 1212// This is a pseudo inst so that we can get the encoding right, 1213// complete with fixup for the aeabi_read_tp function. 1214let isCall = 1, Defs = [R0, R12, LR, CPSR], Uses = [SP] in 1215def tTPsoft : tPseudoInst<(outs), (ins), 4, IIC_Br, 1216 [(set R0, ARMthread_pointer)]>; 1217 1218//===----------------------------------------------------------------------===// 1219// SJLJ Exception handling intrinsics 1220// 1221 1222// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1223// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1224// from some other function to get here, and we're using the stack frame for the 1225// containing function to save/restore registers, we can't keep anything live in 1226// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1227// tromped upon when we get here from a longjmp(). We force everything out of 1228// registers except for our own input by listing the relevant registers in 1229// Defs. By doing so, we also cause the prologue/epilogue code to actively 1230// preserve all of the callee-saved resgisters, which is exactly what we want. 1231// $val is a scratch register for our use. 1232let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1233 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1, 1234 usesCustomInserter = 1 in 1235def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1236 AddrModeNone, 0, NoItinerary, "","", 1237 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1238 1239// FIXME: Non-IOS version(s) 1240let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1241 Defs = [ R7, LR, SP ] in 1242def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1243 AddrModeNone, 0, IndexModeNone, 1244 Pseudo, NoItinerary, "", "", 1245 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1246 Requires<[IsThumb, IsIOS]>; 1247 1248let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12, CPSR ], 1249 isBarrier = 1 in 1250def tInt_eh_sjlj_dispatchsetup : PseudoInst<(outs), (ins), NoItinerary, []>; 1251 1252//===----------------------------------------------------------------------===// 1253// Non-Instruction Patterns 1254// 1255 1256// Comparisons 1257def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1258 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1259def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1260 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1261 1262// Add with carry 1263def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1264 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1265def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1266 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1267def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1268 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1269 1270// Subtract with carry 1271def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1272 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1273def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1274 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1275def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1276 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1277 1278// ConstantPool, GlobalAddress 1279def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 1280def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1281 1282// JumpTable 1283def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1284 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 1285 1286// Direct calls 1287def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1288 Requires<[IsThumb]>; 1289 1290def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1291 Requires<[IsThumb, HasV5T]>; 1292 1293// Indirect calls to ARM routines 1294def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1295 Requires<[IsThumb, HasV5T]>; 1296 1297// zextload i1 -> zextload i8 1298def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), 1299 (tLDRBr t_addrmode_rrs1:$addr)>; 1300def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1301 (tLDRBi t_addrmode_is1:$addr)>; 1302 1303// extload -> zextload 1304def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1305def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1306def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1307def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1308def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>; 1309def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1310 1311// If it's impossible to use [r,r] address mode for sextload, select to 1312// ldr{b|h} + sxt{b|h} instead. 1313def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1314 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1315 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1316def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1317 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, 1318 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1319def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1320 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1321 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1322def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1323 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, 1324 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1325 1326def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1327 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; 1328def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1329 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1330def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1331 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; 1332def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1333 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1334 1335def : T1Pat<(atomic_load_8 t_addrmode_is1:$src), 1336 (tLDRBi t_addrmode_is1:$src)>; 1337def : T1Pat<(atomic_load_8 t_addrmode_rrs1:$src), 1338 (tLDRBr t_addrmode_rrs1:$src)>; 1339def : T1Pat<(atomic_load_16 t_addrmode_is2:$src), 1340 (tLDRHi t_addrmode_is2:$src)>; 1341def : T1Pat<(atomic_load_16 t_addrmode_rrs2:$src), 1342 (tLDRHr t_addrmode_rrs2:$src)>; 1343def : T1Pat<(atomic_load_32 t_addrmode_is4:$src), 1344 (tLDRi t_addrmode_is4:$src)>; 1345def : T1Pat<(atomic_load_32 t_addrmode_rrs4:$src), 1346 (tLDRr t_addrmode_rrs4:$src)>; 1347def : T1Pat<(atomic_store_8 t_addrmode_is1:$ptr, tGPR:$val), 1348 (tSTRBi tGPR:$val, t_addrmode_is1:$ptr)>; 1349def : T1Pat<(atomic_store_8 t_addrmode_rrs1:$ptr, tGPR:$val), 1350 (tSTRBr tGPR:$val, t_addrmode_rrs1:$ptr)>; 1351def : T1Pat<(atomic_store_16 t_addrmode_is2:$ptr, tGPR:$val), 1352 (tSTRHi tGPR:$val, t_addrmode_is2:$ptr)>; 1353def : T1Pat<(atomic_store_16 t_addrmode_rrs2:$ptr, tGPR:$val), 1354 (tSTRHr tGPR:$val, t_addrmode_rrs2:$ptr)>; 1355def : T1Pat<(atomic_store_32 t_addrmode_is4:$ptr, tGPR:$val), 1356 (tSTRi tGPR:$val, t_addrmode_is4:$ptr)>; 1357def : T1Pat<(atomic_store_32 t_addrmode_rrs4:$ptr, tGPR:$val), 1358 (tSTRr tGPR:$val, t_addrmode_rrs4:$ptr)>; 1359 1360// Large immediate handling. 1361 1362// Two piece imms. 1363def : T1Pat<(i32 thumb_immshifted:$src), 1364 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1365 (thumb_immshifted_shamt imm:$src))>; 1366 1367def : T1Pat<(i32 imm0_255_comp:$src), 1368 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1369 1370// Pseudo instruction that combines ldr from constpool and add pc. This should 1371// be expanded into two instructions late to allow if-conversion and 1372// scheduling. 1373let isReMaterializable = 1 in 1374def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1375 NoItinerary, 1376 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1377 imm:$cp))]>, 1378 Requires<[IsThumb, IsThumb1Only]>; 1379 1380// Pseudo-instruction for merged POP and return. 1381// FIXME: remove when we have a way to marking a MI with these properties. 1382let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 1383 hasExtraDefRegAllocReq = 1 in 1384def tPOP_RET : tPseudoExpand<(outs), (ins pred:$p, reglist:$regs, variable_ops), 1385 2, IIC_iPop_Br, [], 1386 (tPOP pred:$p, reglist:$regs)>; 1387 1388// Indirect branch using "mov pc, $Rm" 1389let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 1390 def tBRIND : tPseudoExpand<(outs), (ins GPR:$Rm, pred:$p), 1391 2, IIC_Br, [(brind GPR:$Rm)], 1392 (tMOVr PC, GPR:$Rm, pred:$p)>; 1393} 1394 1395 1396// In Thumb1, "nop" is encoded as a "mov r8, r8". Technically, the bf00 1397// encoding is available on ARMv6K, but we don't differentiate that finely. 1398def : InstAlias<"nop", (tMOVr R8, R8, 14, 0)>,Requires<[IsThumb, IsThumb1Only]>; 1399 1400 1401// For round-trip assembly/disassembly, we have to handle a CPS instruction 1402// without any iflags. That's not, strictly speaking, valid syntax, but it's 1403// a useful extension and assembles to defined behaviour (the insn does 1404// nothing). 1405def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1406def : tInstAlias<"cps$imod", (tCPS imod_op:$imod, 0)>; 1407 1408// "neg" is and alias for "rsb rd, rn, #0" 1409def : tInstAlias<"neg${s}${p} $Rd, $Rm", 1410 (tRSB tGPR:$Rd, s_cc_out:$s, tGPR:$Rm, pred:$p)>; 1411 1412 1413// Implied destination operand forms for shifts. 1414def : tInstAlias<"lsl${s}${p} $Rdm, $imm", 1415 (tLSLri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm0_31:$imm, pred:$p)>; 1416def : tInstAlias<"lsr${s}${p} $Rdm, $imm", 1417 (tLSRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1418def : tInstAlias<"asr${s}${p} $Rdm, $imm", 1419 (tASRri tGPR:$Rdm, cc_out:$s, tGPR:$Rdm, imm_sr:$imm, pred:$p)>; 1420