ARMInstrThumb.td revision 223017 
1//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the Thumb instruction set.
11//
12//===----------------------------------------------------------------------===//
13
14//===----------------------------------------------------------------------===//
15// Thumb specific DAG Nodes.
16//
17
18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
19                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
20                       SDNPVariadic]>;
21
22def imm_neg_XFORM : SDNodeXForm<imm, [{
23  return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
24}]>;
25def imm_comp_XFORM : SDNodeXForm<imm, [{
26  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
27}]>;
28
29/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7].
30def imm0_7 : ImmLeaf<i32, [{
31  return Imm >= 0 && Imm < 8;
32}]>;
33def imm0_7_neg : PatLeaf<(i32 imm), [{
34  return (uint32_t)-N->getZExtValue() < 8;
35}], imm_neg_XFORM>;
36
37def imm0_255 : ImmLeaf<i32, [{
38  return Imm >= 0 && Imm < 256;
39}]>;
40def imm0_255_comp : PatLeaf<(i32 imm), [{
41  return ~((uint32_t)N->getZExtValue()) < 256;
42}]>;
43
44def imm8_255 : ImmLeaf<i32, [{
45  return Imm >= 8 && Imm < 256;
46}]>;
47def imm8_255_neg : PatLeaf<(i32 imm), [{
48  unsigned Val = -N->getZExtValue();
49  return Val >= 8 && Val < 256;
50}], imm_neg_XFORM>;
51
52// Break imm's up into two pieces: an immediate + a left shift. This uses
53// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
54// to get the val/shift pieces.
55def thumb_immshifted : PatLeaf<(imm), [{
56  return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
57}]>;
58
59def thumb_immshifted_val : SDNodeXForm<imm, [{
60  unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
61  return CurDAG->getTargetConstant(V, MVT::i32);
62}]>;
63
64def thumb_immshifted_shamt : SDNodeXForm<imm, [{
65  unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
66  return CurDAG->getTargetConstant(V, MVT::i32);
67}]>;
68
69// ADR instruction labels.
70def t_adrlabel : Operand<i32> {
71  let EncoderMethod = "getThumbAdrLabelOpValue";
72}
73
74// Scaled 4 immediate.
75def t_imm_s4 : Operand<i32> {
76  let PrintMethod = "printThumbS4ImmOperand";
77}
78
79// Define Thumb specific addressing modes.
80
81def t_brtarget : Operand<OtherVT> {
82  let EncoderMethod = "getThumbBRTargetOpValue";
83}
84
85def t_bcctarget : Operand<i32> {
86  let EncoderMethod = "getThumbBCCTargetOpValue";
87}
88
89def t_cbtarget : Operand<i32> {
90  let EncoderMethod = "getThumbCBTargetOpValue";
91}
92
93def t_bltarget : Operand<i32> {
94  let EncoderMethod = "getThumbBLTargetOpValue";
95}
96
97def t_blxtarget : Operand<i32> {
98  let EncoderMethod = "getThumbBLXTargetOpValue";
99}
100
101def MemModeRegThumbAsmOperand : AsmOperandClass {
102  let Name = "MemModeRegThumb";
103  let SuperClasses = [];
104}
105
106def MemModeImmThumbAsmOperand : AsmOperandClass {
107  let Name = "MemModeImmThumb";
108  let SuperClasses = [];
109}
110
111// t_addrmode_rr := reg + reg
112//
113def t_addrmode_rr : Operand<i32>,
114                    ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
115  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
116  let PrintMethod = "printThumbAddrModeRROperand";
117  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
118}
119
120// t_addrmode_rrs := reg + reg
121//
122def t_addrmode_rrs1 : Operand<i32>,
123                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
124  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
125  let PrintMethod = "printThumbAddrModeRROperand";
126  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
127  let ParserMatchClass = MemModeRegThumbAsmOperand;
128}
129def t_addrmode_rrs2 : Operand<i32>,
130                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
131  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
132  let PrintMethod = "printThumbAddrModeRROperand";
133  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
134  let ParserMatchClass = MemModeRegThumbAsmOperand;
135}
136def t_addrmode_rrs4 : Operand<i32>,
137                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
138  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
139  let PrintMethod = "printThumbAddrModeRROperand";
140  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
141  let ParserMatchClass = MemModeRegThumbAsmOperand;
142}
143
144// t_addrmode_is4 := reg + imm5 * 4
145//
146def t_addrmode_is4 : Operand<i32>,
147                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
148  let EncoderMethod = "getAddrModeISOpValue";
149  let PrintMethod = "printThumbAddrModeImm5S4Operand";
150  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
151  let ParserMatchClass = MemModeImmThumbAsmOperand;
152}
153
154// t_addrmode_is2 := reg + imm5 * 2
155//
156def t_addrmode_is2 : Operand<i32>,
157                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
158  let EncoderMethod = "getAddrModeISOpValue";
159  let PrintMethod = "printThumbAddrModeImm5S2Operand";
160  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
161  let ParserMatchClass = MemModeImmThumbAsmOperand;
162}
163
164// t_addrmode_is1 := reg + imm5
165//
166def t_addrmode_is1 : Operand<i32>,
167                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
168  let EncoderMethod = "getAddrModeISOpValue";
169  let PrintMethod = "printThumbAddrModeImm5S1Operand";
170  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
171  let ParserMatchClass = MemModeImmThumbAsmOperand;
172}
173
174// t_addrmode_sp := sp + imm8 * 4
175//
176def t_addrmode_sp : Operand<i32>,
177                    ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
178  let EncoderMethod = "getAddrModeThumbSPOpValue";
179  let PrintMethod = "printThumbAddrModeSPOperand";
180  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
181  let ParserMatchClass = MemModeImmThumbAsmOperand;
182}
183
184// t_addrmode_pc := <label> => pc + imm8 * 4
185//
186def t_addrmode_pc : Operand<i32> {
187  let EncoderMethod = "getAddrModePCOpValue";
188  let ParserMatchClass = MemModeImmThumbAsmOperand;
189}
190
191//===----------------------------------------------------------------------===//
192//  Miscellaneous Instructions.
193//
194
195// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
196// from removing one half of the matched pairs. That breaks PEI, which assumes
197// these will always be in pairs, and asserts if it finds otherwise. Better way?
198let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
199def tADJCALLSTACKUP :
200  PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
201             [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
202            Requires<[IsThumb, IsThumb1Only]>;
203
204def tADJCALLSTACKDOWN :
205  PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
206             [(ARMcallseq_start imm:$amt)]>,
207            Requires<[IsThumb, IsThumb1Only]>;
208}
209
210// T1Disassembly - A simple class to make encoding some disassembly patterns
211// easier and less verbose.
212class T1Disassembly<bits<2> op1, bits<8> op2>
213  : T1Encoding<0b101111> {
214  let Inst{9-8} = op1;
215  let Inst{7-0} = op2;
216}
217
218def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "",
219                [/* For disassembly only; pattern left blank */]>,
220           T1Disassembly<0b11, 0x00>; // A8.6.110
221
222def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "",
223                  [/* For disassembly only; pattern left blank */]>,
224           T1Disassembly<0b11, 0x10>; // A8.6.410
225
226def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "",
227                [/* For disassembly only; pattern left blank */]>,
228           T1Disassembly<0b11, 0x20>; // A8.6.408
229
230def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "",
231                [/* For disassembly only; pattern left blank */]>,
232           T1Disassembly<0b11, 0x30>; // A8.6.409
233
234def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "",
235                [/* For disassembly only; pattern left blank */]>,
236           T1Disassembly<0b11, 0x40>; // A8.6.157
237
238// The i32imm operand $val can be used by a debugger to store more information
239// about the breakpoint.
240def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val",
241                [/* For disassembly only; pattern left blank */]>,
242           T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> {
243  // A8.6.22
244  bits<8> val;
245  let Inst{7-0} = val;
246}
247
248def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe",
249                    [/* For disassembly only; pattern left blank */]>,
250                T1Encoding<0b101101> {
251  // A8.6.156
252  let Inst{9-5} = 0b10010;
253  let Inst{4}   = 1;
254  let Inst{3}   = 1;            // Big-Endian
255  let Inst{2-0} = 0b000;
256}
257
258def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle",
259                    [/* For disassembly only; pattern left blank */]>,
260                T1Encoding<0b101101> {
261  // A8.6.156
262  let Inst{9-5} = 0b10010;
263  let Inst{4}   = 1;
264  let Inst{3}   = 0;            // Little-Endian
265  let Inst{2-0} = 0b000;
266}
267
268// Change Processor State is a system instruction -- for disassembly only.
269def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags),
270                NoItinerary, "cps$imod $iflags",
271                [/* For disassembly only; pattern left blank */]>,
272           T1Misc<0b0110011> {
273  // A8.6.38 & B6.1.1
274  bit imod;
275  bits<3> iflags;
276
277  let Inst{4}   = imod;
278  let Inst{3}   = 0;
279  let Inst{2-0} = iflags;
280}
281
282// For both thumb1 and thumb2.
283let isNotDuplicable = 1, isCodeGenOnly = 1 in
284def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "",
285                  [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>,
286              T1Special<{0,0,?,?}> {
287  // A8.6.6
288  bits<3> dst;
289  let Inst{6-3} = 0b1111; // Rm = pc
290  let Inst{2-0} = dst;
291}
292
293// PC relative add (ADR).
294def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi,
295                   "add\t$dst, pc, $rhs", []>,
296               T1Encoding<{1,0,1,0,0,?}> {
297  // A6.2 & A8.6.10
298  bits<3> dst;
299  bits<8> rhs;
300  let Inst{10-8} = dst;
301  let Inst{7-0}  = rhs;
302}
303
304// ADD <Rd>, sp, #<imm8>
305// This is rematerializable, which is particularly useful for taking the
306// address of locals.
307let isReMaterializable = 1 in
308def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi,
309                   "add\t$dst, $sp, $rhs", []>,
310               T1Encoding<{1,0,1,0,1,?}> {
311  // A6.2 & A8.6.8
312  bits<3> dst;
313  bits<8> rhs;
314  let Inst{10-8} = dst;
315  let Inst{7-0}  = rhs;
316}
317
318// ADD sp, sp, #<imm7>
319def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
320                  "add\t$dst, $rhs", []>,
321              T1Misc<{0,0,0,0,0,?,?}> {
322  // A6.2.5 & A8.6.8
323  bits<7> rhs;
324  let Inst{6-0} = rhs;
325}
326
327// SUB sp, sp, #<imm7>
328// FIXME: The encoding and the ASM string don't match up.
329def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi,
330                  "sub\t$dst, $rhs", []>,
331              T1Misc<{0,0,0,0,1,?,?}> {
332  // A6.2.5 & A8.6.214
333  bits<7> rhs;
334  let Inst{6-0} = rhs;
335}
336
337// ADD <Rm>, sp
338def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
339                  "add\t$dst, $rhs", []>,
340              T1Special<{0,0,?,?}> {
341  // A8.6.9 Encoding T1
342  bits<4> dst;
343  let Inst{7}   = dst{3};
344  let Inst{6-3} = 0b1101;
345  let Inst{2-0} = dst{2-0};
346}
347
348// ADD sp, <Rm>
349def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr,
350                  "add\t$dst, $rhs", []>,
351              T1Special<{0,0,?,?}> {
352  // A8.6.9 Encoding T2
353  bits<4> dst;
354  let Inst{7} = 1;
355  let Inst{6-3} = dst;
356  let Inst{2-0} = 0b101;
357}
358
359//===----------------------------------------------------------------------===//
360//  Control Flow Instructions.
361//
362
363let isReturn = 1, isTerminator = 1, isBarrier = 1 in {
364  def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr",
365                   [(ARMretflag)]>,
366                T1Special<{1,1,0,?}> {
367    // A6.2.3 & A8.6.25
368    let Inst{6-3} = 0b1110; // Rm = lr
369    let Inst{2-0} = 0b000;
370  }
371
372  // Alternative return instruction used by vararg functions.
373  def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm),
374                          IIC_Br, "bx\t$Rm",
375                          []>,
376                       T1Special<{1,1,0,?}> {
377    // A6.2.3 & A8.6.25
378    bits<4> Rm;
379    let Inst{6-3} = Rm;
380    let Inst{2-0} = 0b000;
381  }
382}
383
384// Indirect branches
385let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
386  def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
387            T1Special<{1,1,0,?}> {
388    // A6.2.3 & A8.6.25
389    bits<4> Rm;
390    let Inst{6-3} = Rm;
391    let Inst{2-0} = 0b000;
392  }
393
394  def tBRIND : TI<(outs), (ins GPR:$Rm),
395                  IIC_Br,
396                  "mov\tpc, $Rm",
397                  [(brind GPR:$Rm)]>,
398               T1Special<{1,0,?,?}> {
399    // A8.6.97
400    bits<4> Rm;
401    let Inst{7}   = 1;          // <Rd> = Inst{7:2-0} = pc
402    let Inst{6-3} = Rm;
403    let Inst{2-0} = 0b111;
404  }
405}
406
407// FIXME: remove when we have a way to marking a MI with these properties.
408let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1,
409    hasExtraDefRegAllocReq = 1 in
410def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
411                   IIC_iPop_Br,
412                   "pop${p}\t$regs", []>,
413               T1Misc<{1,1,0,?,?,?,?}> {
414  // A8.6.121
415  bits<16> regs;
416  let Inst{8}   = regs{15};     // registers = P:'0000000':register_list
417  let Inst{7-0} = regs{7-0};
418}
419
420// All calls clobber the non-callee saved registers. SP is marked as a use to
421// prevent stack-pointer assignments that appear immediately before calls from
422// potentially appearing dead.
423let isCall = 1,
424  // On non-Darwin platforms R9 is callee-saved.
425  Defs = [R0,  R1,  R2,  R3,  R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
426  Uses = [SP] in {
427  // Also used for Thumb2
428  def tBL  : TIx2<0b11110, 0b11, 1,
429                  (outs), (ins t_bltarget:$func, variable_ops), IIC_Br,
430                  "bl\t$func",
431                  [(ARMtcall tglobaladdr:$func)]>,
432             Requires<[IsThumb, IsNotDarwin]> {
433    bits<21> func;
434    let Inst{25-16} = func{20-11};
435    let Inst{13} = 1;
436    let Inst{11} = 1;
437    let Inst{10-0} = func{10-0};
438  }
439
440  // ARMv5T and above, also used for Thumb2
441  def tBLXi : TIx2<0b11110, 0b11, 0,
442                   (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br,
443                   "blx\t$func",
444                   [(ARMcall tglobaladdr:$func)]>,
445              Requires<[IsThumb, HasV5T, IsNotDarwin]> {
446    bits<21> func;
447    let Inst{25-16} = func{20-11};
448    let Inst{13} = 1;
449    let Inst{11} = 1;
450    let Inst{10-1} = func{10-1};
451    let Inst{0} = 0; // func{0} is assumed zero
452  }
453
454  // Also used for Thumb2
455  def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br,
456                  "blx\t$func",
457                  [(ARMtcall GPR:$func)]>,
458              Requires<[IsThumb, HasV5T, IsNotDarwin]>,
459              T1Special<{1,1,1,?}> { // A6.2.3 & A8.6.24;
460    bits<4> func;
461    let Inst{6-3} = func;
462    let Inst{2-0} = 0b000;
463  }
464
465  // ARMv4T
466  def tBX_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
467                  Size4Bytes, IIC_Br,
468                  [(ARMcall_nolink tGPR:$func)]>,
469            Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>;
470}
471
472let isCall = 1,
473  // On Darwin R9 is call-clobbered.
474  // R7 is marked as a use to prevent frame-pointer assignments from being
475  // moved above / below calls.
476  Defs = [R0,  R1,  R2,  R3,  R9,  R12, LR, QQQQ0, QQQQ2, QQQQ3, CPSR, FPSCR],
477  Uses = [R7, SP] in {
478  // Also used for Thumb2
479  def tBLr9 : TIx2<0b11110, 0b11, 1,
480                   (outs), (ins pred:$p, t_bltarget:$func, variable_ops),
481                   IIC_Br, "bl${p}\t$func",
482                   [(ARMtcall tglobaladdr:$func)]>,
483              Requires<[IsThumb, IsDarwin]> {
484    bits<21> func;
485    let Inst{25-16} = func{20-11};
486    let Inst{13} = 1;
487    let Inst{11} = 1;
488    let Inst{10-0} = func{10-0};
489  }
490
491  // ARMv5T and above, also used for Thumb2
492  def tBLXi_r9 : TIx2<0b11110, 0b11, 0,
493                      (outs), (ins pred:$p, t_blxtarget:$func, variable_ops),
494                      IIC_Br, "blx${p}\t$func",
495                      [(ARMcall tglobaladdr:$func)]>,
496                 Requires<[IsThumb, HasV5T, IsDarwin]> {
497    bits<21> func;
498    let Inst{25-16} = func{20-11};
499    let Inst{13} = 1;
500    let Inst{11} = 1;
501    let Inst{10-1} = func{10-1};
502    let Inst{0} = 0; // func{0} is assumed zero
503  }
504
505  // Also used for Thumb2
506  def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br,
507                    "blx${p}\t$func",
508                    [(ARMtcall GPR:$func)]>,
509                 Requires<[IsThumb, HasV5T, IsDarwin]>,
510                 T1Special<{1,1,1,?}> {
511    // A6.2.3 & A8.6.24
512    bits<4> func;
513    let Inst{6-3} = func;
514    let Inst{2-0} = 0b000;
515  }
516
517  // ARMv4T
518  def tBXr9_CALL : tPseudoInst<(outs), (ins tGPR:$func, variable_ops),
519                   Size4Bytes, IIC_Br,
520                   [(ARMcall_nolink tGPR:$func)]>,
521              Requires<[IsThumb, IsThumb1Only, IsDarwin]>;
522}
523
524let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
525  let isPredicable = 1 in
526  def tB   : T1I<(outs), (ins t_brtarget:$target), IIC_Br,
527                 "b\t$target", [(br bb:$target)]>,
528             T1Encoding<{1,1,1,0,0,?}> {
529    bits<11> target;
530    let Inst{10-0} = target;
531  }
532
533  // Far jump
534  // Just a pseudo for a tBL instruction. Needed to let regalloc know about
535  // the clobber of LR.
536  let Defs = [LR] in
537  def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target),
538                          Size4Bytes, IIC_Br, []>;
539
540  def tBR_JTr : tPseudoInst<(outs),
541                      (ins tGPR:$target, i32imm:$jt, i32imm:$id),
542                      SizeSpecial, IIC_Br,
543                      [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> {
544    list<Predicate> Predicates = [IsThumb, IsThumb1Only];
545  }
546}
547
548// FIXME: should be able to write a pattern for ARMBrcond, but can't use
549// a two-value operand where a dag node expects two operands. :(
550let isBranch = 1, isTerminator = 1 in
551  def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br,
552                 "b${p}\t$target",
553                 [/*(ARMbrcond bb:$target, imm:$cc)*/]>,
554             T1BranchCond<{1,1,0,1}> {
555  bits<4> p;
556  bits<8> target;
557  let Inst{11-8} = p;
558  let Inst{7-0} = target;
559}
560
561// Compare and branch on zero / non-zero
562let isBranch = 1, isTerminator = 1 in {
563  def tCBZ  : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br,
564                  "cbz\t$Rn, $target", []>,
565              T1Misc<{0,0,?,1,?,?,?}> {
566    // A8.6.27
567    bits<6> target;
568    bits<3> Rn;
569    let Inst{9}   = target{5};
570    let Inst{7-3} = target{4-0};
571    let Inst{2-0} = Rn;
572  }
573
574  def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br,
575                  "cbnz\t$cmp, $target", []>,
576              T1Misc<{1,0,?,1,?,?,?}> {
577    // A8.6.27
578    bits<6> target;
579    bits<3> Rn;
580    let Inst{9}   = target{5};
581    let Inst{7-3} = target{4-0};
582    let Inst{2-0} = Rn;
583  }
584}
585
586// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only
587// A8.6.16 B: Encoding T1
588// If Inst{11-8} == 0b1111 then SEE SVC
589let isCall = 1, Uses = [SP] in
590def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br,
591                "svc", "\t$imm", []>, Encoding16 {
592  bits<8> imm;
593  let Inst{15-12} = 0b1101;
594  let Inst{11-8}  = 0b1111;
595  let Inst{7-0}   = imm;
596}
597
598// The assembler uses 0xDEFE for a trap instruction.
599let isBarrier = 1, isTerminator = 1 in
600def tTRAP : TI<(outs), (ins), IIC_Br,
601               "trap", [(trap)]>, Encoding16 {
602  let Inst = 0xdefe;
603}
604
605//===----------------------------------------------------------------------===//
606//  Load Store Instructions.
607//
608
609// Loads: reg/reg and reg/imm5
610let canFoldAsLoad = 1, isReMaterializable = 1 in
611multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
612                              Operand AddrMode_r, Operand AddrMode_i,
613                              AddrMode am, InstrItinClass itin_r,
614                              InstrItinClass itin_i, string asm,
615                              PatFrag opnode> {
616  def r : // reg/reg
617    T1pILdStEncode<reg_opc,
618                   (outs tGPR:$Rt), (ins AddrMode_r:$addr),
619                   am, itin_r, asm, "\t$Rt, $addr",
620                   [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>;
621  def i : // reg/imm5
622    T1pILdStEncodeImm<imm_opc, 1 /* Load */,
623                      (outs tGPR:$Rt), (ins AddrMode_i:$addr),
624                      am, itin_i, asm, "\t$Rt, $addr",
625                      [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>;
626}
627// Stores: reg/reg and reg/imm5
628multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc,
629                              Operand AddrMode_r, Operand AddrMode_i,
630                              AddrMode am, InstrItinClass itin_r,
631                              InstrItinClass itin_i, string asm,
632                              PatFrag opnode> {
633  def r : // reg/reg
634    T1pILdStEncode<reg_opc,
635                   (outs), (ins tGPR:$Rt, AddrMode_r:$addr),
636                   am, itin_r, asm, "\t$Rt, $addr",
637                   [(opnode tGPR:$Rt, AddrMode_r:$addr)]>;
638  def i : // reg/imm5
639    T1pILdStEncodeImm<imm_opc, 0 /* Store */,
640                      (outs), (ins tGPR:$Rt, AddrMode_i:$addr),
641                      am, itin_i, asm, "\t$Rt, $addr",
642                      [(opnode tGPR:$Rt, AddrMode_i:$addr)]>;
643}
644
645// A8.6.57 & A8.6.60
646defm tLDR  : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
647                                t_addrmode_is4, AddrModeT1_4,
648                                IIC_iLoad_r, IIC_iLoad_i, "ldr",
649                                UnOpFrag<(load node:$Src)>>;
650
651// A8.6.64 & A8.6.61
652defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1,
653                                t_addrmode_is1, AddrModeT1_1,
654                                IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb",
655                                UnOpFrag<(zextloadi8 node:$Src)>>;
656
657// A8.6.76 & A8.6.73
658defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2,
659                                t_addrmode_is2, AddrModeT1_2,
660                                IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh",
661                                UnOpFrag<(zextloadi16 node:$Src)>>;
662
663let AddedComplexity = 10 in
664def tLDRSB :                    // A8.6.80
665  T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
666                 AddrModeT1_1, IIC_iLoad_bh_r,
667                 "ldrsb", "\t$dst, $addr",
668                 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>;
669
670let AddedComplexity = 10 in
671def tLDRSH :                    // A8.6.84
672  T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr),
673                 AddrModeT1_2, IIC_iLoad_bh_r,
674                 "ldrsh", "\t$dst, $addr",
675                 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>;
676
677let canFoldAsLoad = 1 in
678def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
679                    "ldr", "\t$Rt, $addr",
680                    [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>,
681              T1LdStSP<{1,?,?}> {
682  bits<3> Rt;
683  bits<8> addr;
684  let Inst{10-8} = Rt;
685  let Inst{7-0} = addr;
686}
687
688// Special instruction for restore. It cannot clobber condition register
689// when it's expanded by eliminateCallFramePseudoInstr().
690let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in
691// FIXME: Pseudo for tLDRspi
692def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i,
693                     "ldr", "\t$dst, $addr", []>,
694               T1LdStSP<{1,?,?}> {
695  bits<3> Rt;
696  bits<8> addr;
697  let Inst{10-8} = Rt;
698  let Inst{7-0} = addr;
699}
700
701// Load tconstpool
702// FIXME: Use ldr.n to work around a Darwin assembler bug.
703let canFoldAsLoad = 1, isReMaterializable = 1 in
704def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
705                  "ldr", ".n\t$Rt, $addr",
706                  [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>,
707              T1Encoding<{0,1,0,0,1,?}> {
708  // A6.2 & A8.6.59
709  bits<3> Rt;
710  bits<8> addr;
711  let Inst{10-8} = Rt;
712  let Inst{7-0}  = addr;
713}
714
715// FIXME: Remove this entry when the above ldr.n workaround is fixed.
716// For disassembly use only.
717def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i,
718                       "ldr", "\t$Rt, $addr",
719                       [/* disassembly only */]>,
720                 T1Encoding<{0,1,0,0,1,?}> {
721  // A6.2 & A8.6.59
722  bits<3> Rt;
723  bits<8> addr;
724  let Inst{10-8} = Rt;
725  let Inst{7-0}  = addr;
726}
727
728// A8.6.194 & A8.6.192
729defm tSTR  : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4,
730                                t_addrmode_is4, AddrModeT1_4,
731                                IIC_iStore_r, IIC_iStore_i, "str",
732                                BinOpFrag<(store node:$LHS, node:$RHS)>>;
733
734// A8.6.197 & A8.6.195
735defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1,
736                                t_addrmode_is1, AddrModeT1_1,
737                                IIC_iStore_bh_r, IIC_iStore_bh_i, "strb",
738                                BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>;
739
740// A8.6.207 & A8.6.205
741defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2,
742                                t_addrmode_is2, AddrModeT1_2,
743                                IIC_iStore_bh_r, IIC_iStore_bh_i, "strh",
744                                BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>;
745
746
747def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i,
748                    "str", "\t$Rt, $addr",
749                    [(store tGPR:$Rt, t_addrmode_sp:$addr)]>,
750              T1LdStSP<{0,?,?}> {
751  bits<3> Rt;
752  bits<8> addr;
753  let Inst{10-8} = Rt;
754  let Inst{7-0} = addr;
755}
756
757let mayStore = 1, neverHasSideEffects = 1 in
758// Special instruction for spill. It cannot clobber condition register when it's
759// expanded by eliminateCallFramePseudoInstr().
760// FIXME: Pseudo for tSTRspi
761def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i,
762                  "str", "\t$src, $addr", []>,
763             T1LdStSP<{0,?,?}> {
764  bits<3> Rt;
765  bits<8> addr;
766  let Inst{10-8} = Rt;
767  let Inst{7-0} = addr;
768}
769
770//===----------------------------------------------------------------------===//
771//  Load / store multiple Instructions.
772//
773
774multiclass thumb_ldst_mult<string asm, InstrItinClass itin,
775                           InstrItinClass itin_upd, bits<6> T1Enc,
776                           bit L_bit> {
777  def IA :
778    T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
779        itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>,
780       T1Encoding<T1Enc> {
781    bits<3> Rn;
782    bits<8> regs;
783    let Inst{10-8} = Rn;
784    let Inst{7-0}  = regs;
785  }
786  def IA_UPD :
787    T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops),
788         itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>,
789        T1Encoding<T1Enc> {
790    bits<3> Rn;
791    bits<8> regs;
792    let Inst{10-8} = Rn;
793    let Inst{7-0}  = regs;
794  }
795}
796
797// These require base address to be written back or one of the loaded regs.
798let neverHasSideEffects = 1 in {
799
800let mayLoad = 1, hasExtraDefRegAllocReq = 1 in
801defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu,
802                            {1,1,0,0,1,?}, 1>;
803
804let mayStore = 1, hasExtraSrcRegAllocReq = 1 in
805defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu,
806                            {1,1,0,0,0,?}, 0>;
807
808} // neverHasSideEffects
809
810let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in
811def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
812               IIC_iPop,
813               "pop${p}\t$regs", []>,
814           T1Misc<{1,1,0,?,?,?,?}> {
815  bits<16> regs;
816  let Inst{8}   = regs{15};
817  let Inst{7-0} = regs{7-0};
818}
819
820let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in
821def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops),
822                IIC_iStore_m,
823                "push${p}\t$regs", []>,
824            T1Misc<{0,1,0,?,?,?,?}> {
825  bits<16> regs;
826  let Inst{8}   = regs{14};
827  let Inst{7-0} = regs{7-0};
828}
829
830//===----------------------------------------------------------------------===//
831//  Arithmetic Instructions.
832//
833
834// Helper classes for encoding T1pI patterns:
835class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
836                   string opc, string asm, list<dag> pattern>
837    : T1pI<oops, iops, itin, opc, asm, pattern>,
838      T1DataProcessing<opA> {
839  bits<3> Rm;
840  bits<3> Rn;
841  let Inst{5-3} = Rm;
842  let Inst{2-0} = Rn;
843}
844class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
845                     string opc, string asm, list<dag> pattern>
846    : T1pI<oops, iops, itin, opc, asm, pattern>,
847      T1Misc<opA> {
848  bits<3> Rm;
849  bits<3> Rd;
850  let Inst{5-3} = Rm;
851  let Inst{2-0} = Rd;
852}
853
854// Helper classes for encoding T1sI patterns:
855class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
856                   string opc, string asm, list<dag> pattern>
857    : T1sI<oops, iops, itin, opc, asm, pattern>,
858      T1DataProcessing<opA> {
859  bits<3> Rd;
860  bits<3> Rn;
861  let Inst{5-3} = Rn;
862  let Inst{2-0} = Rd;
863}
864class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
865                    string opc, string asm, list<dag> pattern>
866    : T1sI<oops, iops, itin, opc, asm, pattern>,
867      T1General<opA> {
868  bits<3> Rm;
869  bits<3> Rn;
870  bits<3> Rd;
871  let Inst{8-6} = Rm;
872  let Inst{5-3} = Rn;
873  let Inst{2-0} = Rd;
874}
875class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
876                       string opc, string asm, list<dag> pattern>
877    : T1sI<oops, iops, itin, opc, asm, pattern>,
878      T1General<opA> {
879  bits<3> Rd;
880  bits<3> Rm;
881  let Inst{5-3} = Rm;
882  let Inst{2-0} = Rd;
883}
884
885// Helper classes for encoding T1sIt patterns:
886class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
887                    string opc, string asm, list<dag> pattern>
888    : T1sIt<oops, iops, itin, opc, asm, pattern>,
889      T1DataProcessing<opA> {
890  bits<3> Rdn;
891  bits<3> Rm;
892  let Inst{5-3} = Rm;
893  let Inst{2-0} = Rdn;
894}
895class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
896                        string opc, string asm, list<dag> pattern>
897    : T1sIt<oops, iops, itin, opc, asm, pattern>,
898      T1General<opA> {
899  bits<3> Rdn;
900  bits<8> imm8;
901  let Inst{10-8} = Rdn;
902  let Inst{7-0}  = imm8;
903}
904
905// Add with carry register
906let isCommutable = 1, Uses = [CPSR] in
907def tADC :                      // A8.6.2
908  T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr,
909                "adc", "\t$Rdn, $Rm",
910                [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>;
911
912// Add immediate
913def tADDi3 :                    // A8.6.4 T1
914  T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi,
915                   "add", "\t$Rd, $Rm, $imm3",
916                   [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> {
917  bits<3> imm3;
918  let Inst{8-6} = imm3;
919}
920
921def tADDi8 :                    // A8.6.4 T2
922  T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
923                    IIC_iALUi,
924                    "add", "\t$Rdn, $imm8",
925                    [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>;
926
927// Add register
928let isCommutable = 1 in
929def tADDrr :                    // A8.6.6 T1
930  T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
931                IIC_iALUr,
932                "add", "\t$Rd, $Rn, $Rm",
933                [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>;
934
935let neverHasSideEffects = 1 in
936def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr,
937                     "add", "\t$Rdn, $Rm", []>,
938               T1Special<{0,0,?,?}> {
939  // A8.6.6 T2
940  bits<4> Rdn;
941  bits<4> Rm;
942  let Inst{7}   = Rdn{3};
943  let Inst{6-3} = Rm;
944  let Inst{2-0} = Rdn{2-0};
945}
946
947// AND register
948let isCommutable = 1 in
949def tAND :                      // A8.6.12
950  T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
951                IIC_iBITr,
952                "and", "\t$Rdn, $Rm",
953                [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>;
954
955// ASR immediate
956def tASRri :                    // A8.6.14
957  T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
958                   IIC_iMOVsi,
959                   "asr", "\t$Rd, $Rm, $imm5",
960                   [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> {
961  bits<5> imm5;
962  let Inst{10-6} = imm5;
963}
964
965// ASR register
966def tASRrr :                    // A8.6.15
967  T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
968                IIC_iMOVsr,
969                "asr", "\t$Rdn, $Rm",
970                [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>;
971
972// BIC register
973def tBIC :                      // A8.6.20
974  T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
975                IIC_iBITr,
976                "bic", "\t$Rdn, $Rm",
977                [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>;
978
979// CMN register
980let isCompare = 1, Defs = [CPSR] in {
981//FIXME: Disable CMN, as CCodes are backwards from compare expectations
982//       Compare-to-zero still works out, just not the relationals
983//def tCMN :                     // A8.6.33
984//  T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs),
985//               IIC_iCMPr,
986//               "cmn", "\t$lhs, $rhs",
987//               [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>;
988
989def tCMNz :                     // A8.6.33
990  T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm),
991               IIC_iCMPr,
992               "cmn", "\t$Rn, $Rm",
993               [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>;
994
995} // isCompare = 1, Defs = [CPSR]
996
997// CMP immediate
998let isCompare = 1, Defs = [CPSR] in {
999def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi,
1000                  "cmp", "\t$Rn, $imm8",
1001                  [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>,
1002             T1General<{1,0,1,?,?}> {
1003  // A8.6.35
1004  bits<3> Rn;
1005  bits<8> imm8;
1006  let Inst{10-8} = Rn;
1007  let Inst{7-0}  = imm8;
1008}
1009
1010// CMP register
1011def tCMPr :                     // A8.6.36 T1
1012  T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm),
1013               IIC_iCMPr,
1014               "cmp", "\t$Rn, $Rm",
1015               [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>;
1016
1017def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr,
1018                   "cmp", "\t$Rn, $Rm", []>,
1019              T1Special<{0,1,?,?}> {
1020  // A8.6.36 T2
1021  bits<4> Rm;
1022  bits<4> Rn;
1023  let Inst{7}   = Rn{3};
1024  let Inst{6-3} = Rm;
1025  let Inst{2-0} = Rn{2-0};
1026}
1027} // isCompare = 1, Defs = [CPSR]
1028
1029
1030// XOR register
1031let isCommutable = 1 in
1032def tEOR :                      // A8.6.45
1033  T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1034                IIC_iBITr,
1035                "eor", "\t$Rdn, $Rm",
1036                [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>;
1037
1038// LSL immediate
1039def tLSLri :                    // A8.6.88
1040  T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1041                   IIC_iMOVsi,
1042                   "lsl", "\t$Rd, $Rm, $imm5",
1043                   [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> {
1044  bits<5> imm5;
1045  let Inst{10-6} = imm5;
1046}
1047
1048// LSL register
1049def tLSLrr :                    // A8.6.89
1050  T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1051                IIC_iMOVsr,
1052                "lsl", "\t$Rdn, $Rm",
1053                [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>;
1054
1055// LSR immediate
1056def tLSRri :                    // A8.6.90
1057  T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5),
1058                   IIC_iMOVsi,
1059                   "lsr", "\t$Rd, $Rm, $imm5",
1060                   [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> {
1061  bits<5> imm5;
1062  let Inst{10-6} = imm5;
1063}
1064
1065// LSR register
1066def tLSRrr :                    // A8.6.91
1067  T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1068                IIC_iMOVsr,
1069                "lsr", "\t$Rdn, $Rm",
1070                [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>;
1071
1072// Move register
1073let isMoveImm = 1 in
1074def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi,
1075                  "mov", "\t$Rd, $imm8",
1076                  [(set tGPR:$Rd, imm0_255:$imm8)]>,
1077             T1General<{1,0,0,?,?}> {
1078  // A8.6.96
1079  bits<3> Rd;
1080  bits<8> imm8;
1081  let Inst{10-8} = Rd;
1082  let Inst{7-0}  = imm8;
1083}
1084
1085// TODO: A7-73: MOV(2) - mov setting flag.
1086
1087let neverHasSideEffects = 1 in {
1088// FIXME: Make this predicable.
1089def tMOVr       : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1090                      "mov\t$Rd, $Rm", []>,
1091                  T1Special<0b1000> {
1092  // A8.6.97
1093  bits<4> Rd;
1094  bits<4> Rm;
1095  // Bits {7-6} are encoded by the T1Special value.
1096  let Inst{5-3} = Rm{2-0};
1097  let Inst{2-0} = Rd{2-0};
1098}
1099let Defs = [CPSR] in
1100def tMOVSr      : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1101                      "movs\t$Rd, $Rm", []>, Encoding16 {
1102  // A8.6.97
1103  bits<3> Rd;
1104  bits<3> Rm;
1105  let Inst{15-6} = 0b0000000000;
1106  let Inst{5-3}  = Rm;
1107  let Inst{2-0}  = Rd;
1108}
1109
1110// FIXME: Make these predicable.
1111def tMOVgpr2tgpr : T1I<(outs tGPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1112                       "mov\t$Rd, $Rm", []>,
1113                   T1Special<{1,0,0,?}> {
1114  // A8.6.97
1115  bits<4> Rd;
1116  bits<4> Rm;
1117  // Bit {7} is encoded by the T1Special value.
1118  let Inst{6-3} = Rm;
1119  let Inst{2-0} = Rd{2-0};
1120}
1121def tMOVtgpr2gpr : T1I<(outs GPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr,
1122                       "mov\t$Rd, $Rm", []>,
1123                   T1Special<{1,0,?,0}> {
1124  // A8.6.97
1125  bits<4> Rd;
1126  bits<4> Rm;
1127  // Bit {6} is encoded by the T1Special value.
1128  let Inst{7}   = Rd{3};
1129  let Inst{5-3} = Rm{2-0};
1130  let Inst{2-0} = Rd{2-0};
1131}
1132def tMOVgpr2gpr  : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr,
1133                       "mov\t$Rd, $Rm", []>,
1134                   T1Special<{1,0,?,?}> {
1135  // A8.6.97
1136  bits<4> Rd;
1137  bits<4> Rm;
1138  let Inst{7}   = Rd{3};
1139  let Inst{6-3} = Rm;
1140  let Inst{2-0} = Rd{2-0};
1141}
1142} // neverHasSideEffects
1143
1144// Multiply register
1145let isCommutable = 1 in
1146def tMUL :                      // A8.6.105 T1
1147  T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1148                IIC_iMUL32,
1149                "mul", "\t$Rdn, $Rm, $Rdn",
1150                [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>;
1151
1152// Move inverse register
1153def tMVN :                      // A8.6.107
1154  T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr,
1155               "mvn", "\t$Rd, $Rn",
1156               [(set tGPR:$Rd, (not tGPR:$Rn))]>;
1157
1158// Bitwise or register
1159let isCommutable = 1 in
1160def tORR :                      // A8.6.114
1161  T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1162                IIC_iBITr,
1163                "orr", "\t$Rdn, $Rm",
1164                [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>;
1165
1166// Swaps
1167def tREV :                      // A8.6.134
1168  T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1169                 IIC_iUNAr,
1170                 "rev", "\t$Rd, $Rm",
1171                 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>,
1172                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1173
1174def tREV16 :                    // A8.6.135
1175  T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1176                 IIC_iUNAr,
1177                 "rev16", "\t$Rd, $Rm",
1178             [(set tGPR:$Rd,
1179                   (or (and (srl tGPR:$Rm, (i32 8)), 0xFF),
1180                       (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00),
1181                           (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000),
1182                               (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>,
1183                Requires<[IsThumb, IsThumb1Only, HasV6]>;
1184
1185def tREVSH :                    // A8.6.136
1186  T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1187                 IIC_iUNAr,
1188                 "revsh", "\t$Rd, $Rm",
1189                 [(set tGPR:$Rd,
1190                       (sext_inreg
1191                         (or (srl tGPR:$Rm, (i32 8)),
1192                             (shl tGPR:$Rm, (i32 8))), i16))]>,
1193                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1194
1195def : T1Pat<(sext_inreg (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)),
1196                            (shl tGPR:$Rm, (i32 8))), i16),
1197            (tREVSH tGPR:$Rm)>,
1198      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1199
1200def : T1Pat<(sra (bswap tGPR:$Rm), (i32 16)), (tREVSH tGPR:$Rm)>,
1201      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1202
1203// Rotate right register
1204def tROR :                      // A8.6.139
1205  T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1206                IIC_iMOVsr,
1207                "ror", "\t$Rdn, $Rm",
1208                [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>;
1209
1210// Negate register
1211def tRSB :                      // A8.6.141
1212  T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn),
1213               IIC_iALUi,
1214               "rsb", "\t$Rd, $Rn, #0",
1215               [(set tGPR:$Rd, (ineg tGPR:$Rn))]>;
1216
1217// Subtract with carry register
1218let Uses = [CPSR] in
1219def tSBC :                      // A8.6.151
1220  T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm),
1221                IIC_iALUr,
1222                "sbc", "\t$Rdn, $Rm",
1223                [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>;
1224
1225// Subtract immediate
1226def tSUBi3 :                    // A8.6.210 T1
1227  T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3),
1228                   IIC_iALUi,
1229                   "sub", "\t$Rd, $Rm, $imm3",
1230                   [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> {
1231  bits<3> imm3;
1232  let Inst{8-6} = imm3;
1233}
1234
1235def tSUBi8 :                    // A8.6.210 T2
1236  T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8),
1237                    IIC_iALUi,
1238                    "sub", "\t$Rdn, $imm8",
1239                    [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>;
1240
1241// Subtract register
1242def tSUBrr :                    // A8.6.212
1243  T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm),
1244                IIC_iALUr,
1245                "sub", "\t$Rd, $Rn, $Rm",
1246                [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>;
1247
1248// TODO: A7-96: STMIA - store multiple.
1249
1250// Sign-extend byte
1251def tSXTB :                     // A8.6.222
1252  T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1253                 IIC_iUNAr,
1254                 "sxtb", "\t$Rd, $Rm",
1255                 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>,
1256                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1257
1258// Sign-extend short
1259def tSXTH :                     // A8.6.224
1260  T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1261                 IIC_iUNAr,
1262                 "sxth", "\t$Rd, $Rm",
1263                 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>,
1264                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1265
1266// Test
1267let isCompare = 1, isCommutable = 1, Defs = [CPSR] in
1268def tTST :                      // A8.6.230
1269  T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr,
1270               "tst", "\t$Rn, $Rm",
1271               [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>;
1272
1273// Zero-extend byte
1274def tUXTB :                     // A8.6.262
1275  T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1276                 IIC_iUNAr,
1277                 "uxtb", "\t$Rd, $Rm",
1278                 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>,
1279                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1280
1281// Zero-extend short
1282def tUXTH :                     // A8.6.264
1283  T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm),
1284                 IIC_iUNAr,
1285                 "uxth", "\t$Rd, $Rm",
1286                 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>,
1287                 Requires<[IsThumb, IsThumb1Only, HasV6]>;
1288
1289// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation.
1290// Expanded after instruction selection into a branch sequence.
1291let usesCustomInserter = 1 in  // Expanded after instruction selection.
1292  def tMOVCCr_pseudo :
1293  PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc),
1294              NoItinerary,
1295             [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>;
1296
1297
1298// 16-bit movcc in IT blocks for Thumb2.
1299let neverHasSideEffects = 1 in {
1300def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr,
1301                    "mov", "\t$Rdn, $Rm", []>,
1302              T1Special<{1,0,?,?}> {
1303  bits<4> Rdn;
1304  bits<4> Rm;
1305  let Inst{7}   = Rdn{3};
1306  let Inst{6-3} = Rm;
1307  let Inst{2-0} = Rdn{2-0};
1308}
1309
1310let isMoveImm = 1 in
1311def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi,
1312                    "mov", "\t$Rdn, $Rm", []>,
1313              T1General<{1,0,0,?,?}> {
1314  bits<3> Rdn;
1315  bits<8> Rm;
1316  let Inst{10-8} = Rdn;
1317  let Inst{7-0}  = Rm;
1318}
1319
1320} // neverHasSideEffects
1321
1322// tLEApcrel - Load a pc-relative address into a register without offending the
1323// assembler.
1324
1325def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p),
1326               IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>,
1327               T1Encoding<{1,0,1,0,0,?}> {
1328  bits<3> Rd;
1329  bits<8> addr;
1330  let Inst{10-8} = Rd;
1331  let Inst{7-0} = addr;
1332}
1333
1334let neverHasSideEffects = 1, isReMaterializable = 1 in
1335def tLEApcrel   : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p),
1336                              Size2Bytes, IIC_iALUi, []>;
1337
1338def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd),
1339                              (ins i32imm:$label, nohash_imm:$id, pred:$p),
1340                              Size2Bytes, IIC_iALUi, []>;
1341
1342//===----------------------------------------------------------------------===//
1343// Move between coprocessor and ARM core register -- for disassembly only
1344//
1345
1346class tMovRCopro<string opc, bit direction, dag oops, dag iops,
1347                 list<dag> pattern>
1348  : T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
1349          pattern> {
1350  let Inst{27-24} = 0b1110;
1351  let Inst{20} = direction;
1352  let Inst{4} = 1;
1353
1354  bits<4> Rt;
1355  bits<4> cop;
1356  bits<3> opc1;
1357  bits<3> opc2;
1358  bits<4> CRm;
1359  bits<4> CRn;
1360
1361  let Inst{15-12} = Rt;
1362  let Inst{11-8}  = cop;
1363  let Inst{23-21} = opc1;
1364  let Inst{7-5}   = opc2;
1365  let Inst{3-0}   = CRm;
1366  let Inst{19-16} = CRn;
1367}
1368
1369def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */,
1370           (outs),
1371           (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn,
1372                c_imm:$CRm, i32imm:$opc2),
1373           [(int_arm_mcr imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
1374                         imm:$CRm, imm:$opc2)]>;
1375def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */,
1376           (outs GPR:$Rt),
1377           (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1378           []>;
1379
1380def : Pat<(int_arm_mrc imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2),
1381          (tMRC imm:$cop, imm:$opc1, imm:$CRn, imm:$CRm, imm:$opc2)>,
1382          Requires<[IsThumb, HasV6T2]>;
1383
1384class tMovRRCopro<string opc, bit direction,
1385                  list<dag> pattern = [/* For disassembly only */]>
1386  : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
1387          !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
1388  let Inst{27-24} = 0b1100;
1389  let Inst{23-21} = 0b010;
1390  let Inst{20} = direction;
1391
1392  bits<4> Rt;
1393  bits<4> Rt2;
1394  bits<4> cop;
1395  bits<4> opc1;
1396  bits<4> CRm;
1397
1398  let Inst{15-12} = Rt;
1399  let Inst{19-16} = Rt2;
1400  let Inst{11-8}  = cop;
1401  let Inst{7-4}   = opc1;
1402  let Inst{3-0}   = CRm;
1403}
1404
1405def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
1406                        [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
1407                                       imm:$CRm)]>;
1408def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
1409
1410//===----------------------------------------------------------------------===//
1411// Other Coprocessor Instructions.  For disassembly only.
1412//
1413def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1414                 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1415                 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
1416                 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
1417                               imm:$CRm, imm:$opc2)]> {
1418  let Inst{27-24} = 0b1110;
1419
1420  bits<4> opc1;
1421  bits<4> CRn;
1422  bits<4> CRd;
1423  bits<4> cop;
1424  bits<3> opc2;
1425  bits<4> CRm;
1426
1427  let Inst{3-0}   = CRm;
1428  let Inst{4}     = 0;
1429  let Inst{7-5}   = opc2;
1430  let Inst{11-8}  = cop;
1431  let Inst{15-12} = CRd;
1432  let Inst{19-16} = CRn;
1433  let Inst{23-20} = opc1;
1434}
1435
1436//===----------------------------------------------------------------------===//
1437// TLS Instructions
1438//
1439
1440// __aeabi_read_tp preserves the registers r1-r3.
1441let isCall = 1, Defs = [R0, LR], Uses = [SP] in
1442def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br,
1443                   "bl\t__aeabi_read_tp",
1444                   [(set R0, ARMthread_pointer)]> {
1445  // Encoding is 0xf7fffffe.
1446  let Inst = 0xf7fffffe;
1447}
1448
1449//===----------------------------------------------------------------------===//
1450// SJLJ Exception handling intrinsics
1451//
1452
1453// eh_sjlj_setjmp() is an instruction sequence to store the return address and
1454// save #0 in R0 for the non-longjmp case.  Since by its nature we may be coming
1455// from some other function to get here, and we're using the stack frame for the
1456// containing function to save/restore registers, we can't keep anything live in
1457// regs across the eh_sjlj_setjmp(), else it will almost certainly have been
1458// tromped upon when we get here from a longjmp(). We force everything out of
1459// registers except for our own input by listing the relevant registers in
1460// Defs. By doing so, we also cause the prologue/epilogue code to actively
1461// preserve all of the callee-saved resgisters, which is exactly what we want.
1462// $val is a scratch register for our use.
1463let Defs = [ R0,  R1,  R2,  R3,  R4,  R5,  R6,  R7, R12, CPSR ],
1464    hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in
1465def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val),
1466                                  AddrModeNone, SizeSpecial, NoItinerary, "","",
1467                          [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>;
1468
1469// FIXME: Non-Darwin version(s)
1470let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1,
1471    Defs = [ R7, LR, SP ] in
1472def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch),
1473                              AddrModeNone, SizeSpecial, IndexModeNone,
1474                              Pseudo, NoItinerary, "", "",
1475                              [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>,
1476                             Requires<[IsThumb, IsDarwin]>;
1477
1478//===----------------------------------------------------------------------===//
1479// Non-Instruction Patterns
1480//
1481
1482// Comparisons
1483def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8),
1484            (tCMPi8  tGPR:$Rn, imm0_255:$imm8)>;
1485def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm),
1486            (tCMPr   tGPR:$Rn, tGPR:$Rm)>;
1487
1488// Add with carry
1489def : T1Pat<(addc   tGPR:$lhs, imm0_7:$rhs),
1490            (tADDi3 tGPR:$lhs, imm0_7:$rhs)>;
1491def : T1Pat<(addc   tGPR:$lhs, imm8_255:$rhs),
1492            (tADDi8 tGPR:$lhs, imm8_255:$rhs)>;
1493def : T1Pat<(addc   tGPR:$lhs, tGPR:$rhs),
1494            (tADDrr tGPR:$lhs, tGPR:$rhs)>;
1495
1496// Subtract with carry
1497def : T1Pat<(addc   tGPR:$lhs, imm0_7_neg:$rhs),
1498            (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>;
1499def : T1Pat<(addc   tGPR:$lhs, imm8_255_neg:$rhs),
1500            (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>;
1501def : T1Pat<(subc   tGPR:$lhs, tGPR:$rhs),
1502            (tSUBrr tGPR:$lhs, tGPR:$rhs)>;
1503
1504// ConstantPool, GlobalAddress
1505def : T1Pat<(ARMWrapper  tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>;
1506def : T1Pat<(ARMWrapper  tconstpool  :$dst), (tLEApcrel tconstpool  :$dst)>;
1507
1508// JumpTable
1509def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id),
1510            (tLEApcrelJT tjumptable:$dst, imm:$id)>;
1511
1512// Direct calls
1513def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>,
1514      Requires<[IsThumb, IsNotDarwin]>;
1515def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>,
1516      Requires<[IsThumb, IsDarwin]>;
1517
1518def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>,
1519      Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1520def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>,
1521      Requires<[IsThumb, HasV5T, IsDarwin]>;
1522
1523// Indirect calls to ARM routines
1524def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>,
1525      Requires<[IsThumb, HasV5T, IsNotDarwin]>;
1526def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>,
1527      Requires<[IsThumb, HasV5T, IsDarwin]>;
1528
1529// zextload i1 -> zextload i8
1530def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr),
1531            (tLDRBr t_addrmode_rrs1:$addr)>;
1532def : T1Pat<(zextloadi1 t_addrmode_is1:$addr),
1533            (tLDRBi t_addrmode_is1:$addr)>;
1534
1535// extload -> zextload
1536def : T1Pat<(extloadi1  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1537def : T1Pat<(extloadi1  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
1538def : T1Pat<(extloadi8  t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>;
1539def : T1Pat<(extloadi8  t_addrmode_is1:$addr),  (tLDRBi t_addrmode_is1:$addr)>;
1540def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>;
1541def : T1Pat<(extloadi16 t_addrmode_is2:$addr),  (tLDRHi t_addrmode_is2:$addr)>;
1542
1543// If it's impossible to use [r,r] address mode for sextload, select to
1544// ldr{b|h} + sxt{b|h} instead.
1545def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1546            (tSXTB (tLDRBi t_addrmode_is1:$addr))>,
1547      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1548def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1549            (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>,
1550      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1551def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1552            (tSXTH (tLDRHi t_addrmode_is2:$addr))>,
1553      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1554def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1555            (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>,
1556      Requires<[IsThumb, IsThumb1Only, HasV6]>;
1557
1558def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr),
1559            (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>;
1560def : T1Pat<(sextloadi8 t_addrmode_is1:$addr),
1561            (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>;
1562def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr),
1563            (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>;
1564def : T1Pat<(sextloadi16 t_addrmode_is2:$addr),
1565            (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>;
1566
1567// Large immediate handling.
1568
1569// Two piece imms.
1570def : T1Pat<(i32 thumb_immshifted:$src),
1571            (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)),
1572                    (thumb_immshifted_shamt imm:$src))>;
1573
1574def : T1Pat<(i32 imm0_255_comp:$src),
1575            (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>;
1576
1577// Pseudo instruction that combines ldr from constpool and add pc. This should
1578// be expanded into two instructions late to allow if-conversion and
1579// scheduling.
1580let isReMaterializable = 1 in
1581def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp),
1582                             NoItinerary,
1583               [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)),
1584                                           imm:$cp))]>,
1585               Requires<[IsThumb, IsThumb1Only]>;
1586