ARMInstrThumb.td revision 221345
1//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, 20 SDNPVariadic]>; 21 22def imm_neg_XFORM : SDNodeXForm<imm, [{ 23 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 24}]>; 25def imm_comp_XFORM : SDNodeXForm<imm, [{ 26 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 27}]>; 28 29/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7]. 30def imm0_7 : ImmLeaf<i32, [{ 31 return Imm >= 0 && Imm < 8; 32}]>; 33def imm0_7_neg : PatLeaf<(i32 imm), [{ 34 return (uint32_t)-N->getZExtValue() < 8; 35}], imm_neg_XFORM>; 36 37def imm0_255 : ImmLeaf<i32, [{ 38 return Imm >= 0 && Imm < 256; 39}]>; 40def imm0_255_comp : PatLeaf<(i32 imm), [{ 41 return ~((uint32_t)N->getZExtValue()) < 256; 42}]>; 43 44def imm8_255 : ImmLeaf<i32, [{ 45 return Imm >= 8 && Imm < 256; 46}]>; 47def imm8_255_neg : PatLeaf<(i32 imm), [{ 48 unsigned Val = -N->getZExtValue(); 49 return Val >= 8 && Val < 256; 50}], imm_neg_XFORM>; 51 52// Break imm's up into two pieces: an immediate + a left shift. This uses 53// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt 54// to get the val/shift pieces. 55def thumb_immshifted : PatLeaf<(imm), [{ 56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 57}]>; 58 59def thumb_immshifted_val : SDNodeXForm<imm, [{ 60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 61 return CurDAG->getTargetConstant(V, MVT::i32); 62}]>; 63 64def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 66 return CurDAG->getTargetConstant(V, MVT::i32); 67}]>; 68 69// ADR instruction labels. 70def t_adrlabel : Operand<i32> { 71 let EncoderMethod = "getThumbAdrLabelOpValue"; 72} 73 74// Scaled 4 immediate. 75def t_imm_s4 : Operand<i32> { 76 let PrintMethod = "printThumbS4ImmOperand"; 77} 78 79// Define Thumb specific addressing modes. 80 81def t_brtarget : Operand<OtherVT> { 82 let EncoderMethod = "getThumbBRTargetOpValue"; 83} 84 85def t_bcctarget : Operand<i32> { 86 let EncoderMethod = "getThumbBCCTargetOpValue"; 87} 88 89def t_cbtarget : Operand<i32> { 90 let EncoderMethod = "getThumbCBTargetOpValue"; 91} 92 93def t_bltarget : Operand<i32> { 94 let EncoderMethod = "getThumbBLTargetOpValue"; 95} 96 97def t_blxtarget : Operand<i32> { 98 let EncoderMethod = "getThumbBLXTargetOpValue"; 99} 100 101def MemModeRegThumbAsmOperand : AsmOperandClass { 102 let Name = "MemModeRegThumb"; 103 let SuperClasses = []; 104} 105 106def MemModeImmThumbAsmOperand : AsmOperandClass { 107 let Name = "MemModeImmThumb"; 108 let SuperClasses = []; 109} 110 111// t_addrmode_rr := reg + reg 112// 113def t_addrmode_rr : Operand<i32>, 114 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 115 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 116 let PrintMethod = "printThumbAddrModeRROperand"; 117 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 118} 119 120// t_addrmode_rrs := reg + reg 121// 122def t_addrmode_rrs1 : Operand<i32>, 123 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> { 124 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 125 let PrintMethod = "printThumbAddrModeRROperand"; 126 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 127 let ParserMatchClass = MemModeRegThumbAsmOperand; 128} 129def t_addrmode_rrs2 : Operand<i32>, 130 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> { 131 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 132 let PrintMethod = "printThumbAddrModeRROperand"; 133 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 134 let ParserMatchClass = MemModeRegThumbAsmOperand; 135} 136def t_addrmode_rrs4 : Operand<i32>, 137 ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> { 138 let EncoderMethod = "getThumbAddrModeRegRegOpValue"; 139 let PrintMethod = "printThumbAddrModeRROperand"; 140 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 141 let ParserMatchClass = MemModeRegThumbAsmOperand; 142} 143 144// t_addrmode_is4 := reg + imm5 * 4 145// 146def t_addrmode_is4 : Operand<i32>, 147 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> { 148 let EncoderMethod = "getAddrModeISOpValue"; 149 let PrintMethod = "printThumbAddrModeImm5S4Operand"; 150 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 151 let ParserMatchClass = MemModeImmThumbAsmOperand; 152} 153 154// t_addrmode_is2 := reg + imm5 * 2 155// 156def t_addrmode_is2 : Operand<i32>, 157 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> { 158 let EncoderMethod = "getAddrModeISOpValue"; 159 let PrintMethod = "printThumbAddrModeImm5S2Operand"; 160 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 161 let ParserMatchClass = MemModeImmThumbAsmOperand; 162} 163 164// t_addrmode_is1 := reg + imm5 165// 166def t_addrmode_is1 : Operand<i32>, 167 ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> { 168 let EncoderMethod = "getAddrModeISOpValue"; 169 let PrintMethod = "printThumbAddrModeImm5S1Operand"; 170 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm); 171 let ParserMatchClass = MemModeImmThumbAsmOperand; 172} 173 174// t_addrmode_sp := sp + imm8 * 4 175// 176def t_addrmode_sp : Operand<i32>, 177 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 178 let EncoderMethod = "getAddrModeThumbSPOpValue"; 179 let PrintMethod = "printThumbAddrModeSPOperand"; 180 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 181 let ParserMatchClass = MemModeImmThumbAsmOperand; 182} 183 184// t_addrmode_pc := <label> => pc + imm8 * 4 185// 186def t_addrmode_pc : Operand<i32> { 187 let EncoderMethod = "getAddrModePCOpValue"; 188 let ParserMatchClass = MemModeImmThumbAsmOperand; 189} 190 191//===----------------------------------------------------------------------===// 192// Miscellaneous Instructions. 193// 194 195// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 196// from removing one half of the matched pairs. That breaks PEI, which assumes 197// these will always be in pairs, and asserts if it finds otherwise. Better way? 198let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 199def tADJCALLSTACKUP : 200 PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 201 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, 202 Requires<[IsThumb, IsThumb1Only]>; 203 204def tADJCALLSTACKDOWN : 205 PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 206 [(ARMcallseq_start imm:$amt)]>, 207 Requires<[IsThumb, IsThumb1Only]>; 208} 209 210// T1Disassembly - A simple class to make encoding some disassembly patterns 211// easier and less verbose. 212class T1Disassembly<bits<2> op1, bits<8> op2> 213 : T1Encoding<0b101111> { 214 let Inst{9-8} = op1; 215 let Inst{7-0} = op2; 216} 217 218def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", 219 [/* For disassembly only; pattern left blank */]>, 220 T1Disassembly<0b11, 0x00>; // A8.6.110 221 222def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", 223 [/* For disassembly only; pattern left blank */]>, 224 T1Disassembly<0b11, 0x10>; // A8.6.410 225 226def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", 227 [/* For disassembly only; pattern left blank */]>, 228 T1Disassembly<0b11, 0x20>; // A8.6.408 229 230def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", 231 [/* For disassembly only; pattern left blank */]>, 232 T1Disassembly<0b11, 0x30>; // A8.6.409 233 234def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", 235 [/* For disassembly only; pattern left blank */]>, 236 T1Disassembly<0b11, 0x40>; // A8.6.157 237 238// The i32imm operand $val can be used by a debugger to store more information 239// about the breakpoint. 240def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val", 241 [/* For disassembly only; pattern left blank */]>, 242 T1Disassembly<0b10, {?,?,?,?,?,?,?,?}> { 243 // A8.6.22 244 bits<8> val; 245 let Inst{7-0} = val; 246} 247 248def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe", 249 [/* For disassembly only; pattern left blank */]>, 250 T1Encoding<0b101101> { 251 // A8.6.156 252 let Inst{9-5} = 0b10010; 253 let Inst{4} = 1; 254 let Inst{3} = 1; // Big-Endian 255 let Inst{2-0} = 0b000; 256} 257 258def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle", 259 [/* For disassembly only; pattern left blank */]>, 260 T1Encoding<0b101101> { 261 // A8.6.156 262 let Inst{9-5} = 0b10010; 263 let Inst{4} = 1; 264 let Inst{3} = 0; // Little-Endian 265 let Inst{2-0} = 0b000; 266} 267 268// Change Processor State is a system instruction -- for disassembly only. 269def tCPS : T1I<(outs), (ins imod_op:$imod, iflags_op:$iflags), 270 NoItinerary, "cps$imod $iflags", 271 [/* For disassembly only; pattern left blank */]>, 272 T1Misc<0b0110011> { 273 // A8.6.38 & B6.1.1 274 bit imod; 275 bits<3> iflags; 276 277 let Inst{4} = imod; 278 let Inst{3} = 0; 279 let Inst{2-0} = iflags; 280} 281 282// For both thumb1 and thumb2. 283let isNotDuplicable = 1, isCodeGenOnly = 1 in 284def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, "", 285 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 286 T1Special<{0,0,?,?}> { 287 // A8.6.6 288 bits<3> dst; 289 let Inst{6-3} = 0b1111; // Rm = pc 290 let Inst{2-0} = dst; 291} 292 293// PC relative add (ADR). 294def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi, 295 "add\t$dst, pc, $rhs", []>, 296 T1Encoding<{1,0,1,0,0,?}> { 297 // A6.2 & A8.6.10 298 bits<3> dst; 299 bits<8> rhs; 300 let Inst{10-8} = dst; 301 let Inst{7-0} = rhs; 302} 303 304// ADD <Rd>, sp, #<imm8> 305// This is rematerializable, which is particularly useful for taking the 306// address of locals. 307let isReMaterializable = 1 in 308def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi, 309 "add\t$dst, $sp, $rhs", []>, 310 T1Encoding<{1,0,1,0,1,?}> { 311 // A6.2 & A8.6.8 312 bits<3> dst; 313 bits<8> rhs; 314 let Inst{10-8} = dst; 315 let Inst{7-0} = rhs; 316} 317 318// ADD sp, sp, #<imm7> 319def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 320 "add\t$dst, $rhs", []>, 321 T1Misc<{0,0,0,0,0,?,?}> { 322 // A6.2.5 & A8.6.8 323 bits<7> rhs; 324 let Inst{6-0} = rhs; 325} 326 327// SUB sp, sp, #<imm7> 328// FIXME: The encoding and the ASM string don't match up. 329def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 330 "sub\t$dst, $rhs", []>, 331 T1Misc<{0,0,0,0,1,?,?}> { 332 // A6.2.5 & A8.6.214 333 bits<7> rhs; 334 let Inst{6-0} = rhs; 335} 336 337// ADD <Rm>, sp 338def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 339 "add\t$dst, $rhs", []>, 340 T1Special<{0,0,?,?}> { 341 // A8.6.9 Encoding T1 342 bits<4> dst; 343 let Inst{7} = dst{3}; 344 let Inst{6-3} = 0b1101; 345 let Inst{2-0} = dst{2-0}; 346} 347 348// ADD sp, <Rm> 349def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 350 "add\t$dst, $rhs", []>, 351 T1Special<{0,0,?,?}> { 352 // A8.6.9 Encoding T2 353 bits<4> dst; 354 let Inst{7} = 1; 355 let Inst{6-3} = dst; 356 let Inst{2-0} = 0b101; 357} 358 359//===----------------------------------------------------------------------===// 360// Control Flow Instructions. 361// 362 363let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 364 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", 365 [(ARMretflag)]>, 366 T1Special<{1,1,0,?}> { 367 // A6.2.3 & A8.6.25 368 let Inst{6-3} = 0b1110; // Rm = lr 369 let Inst{2-0} = 0b000; 370 } 371 372 def tBX_Rm : TI<(outs), (ins pred:$p, GPR:$Rm), IIC_Br, "bx${p}\t$Rm", 373 [/* for disassembly only */]>, 374 T1Special<{1,1,0,?}> { 375 // A6.2.3 & A8.6.25 376 bits<4> Rm; 377 let Inst{6-3} = Rm; 378 let Inst{2-0} = 0b000; 379 } 380 381 // Alternative return instruction used by vararg functions. 382 def tBX_RET_vararg : TI<(outs), (ins tGPR:$Rm), 383 IIC_Br, "bx\t$Rm", 384 []>, 385 T1Special<{1,1,0,?}> { 386 // A6.2.3 & A8.6.25 387 bits<4> Rm; 388 let Inst{6-3} = Rm; 389 let Inst{2-0} = 0b000; 390 } 391} 392 393// Indirect branches 394let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 395 def tBRIND : TI<(outs), (ins GPR:$Rm), 396 IIC_Br, 397 "mov\tpc, $Rm", 398 [(brind GPR:$Rm)]>, 399 T1Special<{1,0,?,?}> { 400 // A8.6.97 401 bits<4> Rm; 402 let Inst{7} = 1; // <Rd> = Inst{7:2-0} = pc 403 let Inst{6-3} = Rm; 404 let Inst{2-0} = 0b111; 405 } 406} 407 408// FIXME: remove when we have a way to marking a MI with these properties. 409let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 410 hasExtraDefRegAllocReq = 1 in 411def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 412 IIC_iPop_Br, 413 "pop${p}\t$regs", []>, 414 T1Misc<{1,1,0,?,?,?,?}> { 415 // A8.6.121 416 bits<16> regs; 417 let Inst{8} = regs{15}; // registers = P:'0000000':register_list 418 let Inst{7-0} = regs{7-0}; 419} 420 421// All calls clobber the non-callee saved registers. SP is marked as a use to 422// prevent stack-pointer assignments that appear immediately before calls from 423// potentially appearing dead. 424let isCall = 1, 425 // On non-Darwin platforms R9 is callee-saved. 426 Defs = [R0, R1, R2, R3, R12, LR, 427 D0, D1, D2, D3, D4, D5, D6, D7, 428 D16, D17, D18, D19, D20, D21, D22, D23, 429 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR], 430 Uses = [SP] in { 431 // Also used for Thumb2 432 def tBL : TIx2<0b11110, 0b11, 1, 433 (outs), (ins t_bltarget:$func, variable_ops), IIC_Br, 434 "bl\t$func", 435 [(ARMtcall tglobaladdr:$func)]>, 436 Requires<[IsThumb, IsNotDarwin]> { 437 bits<21> func; 438 let Inst{25-16} = func{20-11}; 439 let Inst{13} = 1; 440 let Inst{11} = 1; 441 let Inst{10-0} = func{10-0}; 442 } 443 444 // ARMv5T and above, also used for Thumb2 445 def tBLXi : TIx2<0b11110, 0b11, 0, 446 (outs), (ins t_blxtarget:$func, variable_ops), IIC_Br, 447 "blx\t$func", 448 [(ARMcall tglobaladdr:$func)]>, 449 Requires<[IsThumb, HasV5T, IsNotDarwin]> { 450 bits<21> func; 451 let Inst{25-16} = func{20-11}; 452 let Inst{13} = 1; 453 let Inst{11} = 1; 454 let Inst{10-1} = func{10-1}; 455 let Inst{0} = 0; // func{0} is assumed zero 456 } 457 458 // Also used for Thumb2 459 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, 460 "blx\t$func", 461 [(ARMtcall GPR:$func)]>, 462 Requires<[IsThumb, HasV5T, IsNotDarwin]>, 463 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24; 464 465 // ARMv4T 466 // FIXME: Should be a pseudo. 467 let isCodeGenOnly = 1 in 468 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?, 469 (outs), (ins tGPR:$func, variable_ops), IIC_Br, 470 "mov\tlr, pc\n\tbx\t$func", 471 [(ARMcall_nolink tGPR:$func)]>, 472 Requires<[IsThumb, IsThumb1Only, IsNotDarwin]>; 473} 474 475let isCall = 1, 476 // On Darwin R9 is call-clobbered. 477 // R7 is marked as a use to prevent frame-pointer assignments from being 478 // moved above / below calls. 479 Defs = [R0, R1, R2, R3, R9, R12, LR, 480 D0, D1, D2, D3, D4, D5, D6, D7, 481 D16, D17, D18, D19, D20, D21, D22, D23, 482 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR], 483 Uses = [R7, SP] in { 484 // Also used for Thumb2 485 def tBLr9 : TIx2<0b11110, 0b11, 1, 486 (outs), (ins pred:$p, t_bltarget:$func, variable_ops), 487 IIC_Br, "bl${p}\t$func", 488 [(ARMtcall tglobaladdr:$func)]>, 489 Requires<[IsThumb, IsDarwin]> { 490 bits<21> func; 491 let Inst{25-16} = func{20-11}; 492 let Inst{13} = 1; 493 let Inst{11} = 1; 494 let Inst{10-0} = func{10-0}; 495 } 496 497 // ARMv5T and above, also used for Thumb2 498 def tBLXi_r9 : TIx2<0b11110, 0b11, 0, 499 (outs), (ins pred:$p, t_blxtarget:$func, variable_ops), 500 IIC_Br, "blx${p}\t$func", 501 [(ARMcall tglobaladdr:$func)]>, 502 Requires<[IsThumb, HasV5T, IsDarwin]> { 503 bits<21> func; 504 let Inst{25-16} = func{20-11}; 505 let Inst{13} = 1; 506 let Inst{11} = 1; 507 let Inst{10-1} = func{10-1}; 508 let Inst{0} = 0; // func{0} is assumed zero 509 } 510 511 // Also used for Thumb2 512 def tBLXr_r9 : TI<(outs), (ins pred:$p, GPR:$func, variable_ops), IIC_Br, 513 "blx${p}\t$func", 514 [(ARMtcall GPR:$func)]>, 515 Requires<[IsThumb, HasV5T, IsDarwin]>, 516 T1Special<{1,1,1,?}> { 517 // A6.2.3 & A8.6.24 518 bits<4> func; 519 let Inst{6-3} = func; 520 let Inst{2-0} = 0b000; 521 } 522 523 // ARMv4T 524 let isCodeGenOnly = 1 in 525 // FIXME: Should be a pseudo. 526 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?, 527 (outs), (ins tGPR:$func, variable_ops), IIC_Br, 528 "mov\tlr, pc\n\tbx\t$func", 529 [(ARMcall_nolink tGPR:$func)]>, 530 Requires<[IsThumb, IsThumb1Only, IsDarwin]>; 531} 532 533let isBranch = 1, isTerminator = 1, isBarrier = 1 in { 534 let isPredicable = 1 in 535 def tB : T1I<(outs), (ins t_brtarget:$target), IIC_Br, 536 "b\t$target", [(br bb:$target)]>, 537 T1Encoding<{1,1,1,0,0,?}> { 538 bits<11> target; 539 let Inst{10-0} = target; 540 } 541 542 // Far jump 543 // Just a pseudo for a tBL instruction. Needed to let regalloc know about 544 // the clobber of LR. 545 let Defs = [LR] in 546 def tBfar : tPseudoInst<(outs), (ins t_bltarget:$target), 547 Size4Bytes, IIC_Br, []>; 548 549 def tBR_JTr : tPseudoInst<(outs), 550 (ins tGPR:$target, i32imm:$jt, i32imm:$id), 551 SizeSpecial, IIC_Br, 552 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]> { 553 list<Predicate> Predicates = [IsThumb, IsThumb1Only]; 554 } 555} 556 557// FIXME: should be able to write a pattern for ARMBrcond, but can't use 558// a two-value operand where a dag node expects two operands. :( 559let isBranch = 1, isTerminator = 1 in 560 def tBcc : T1I<(outs), (ins t_bcctarget:$target, pred:$p), IIC_Br, 561 "b${p}\t$target", 562 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 563 T1Encoding<{1,1,0,1,?,?}> { 564 bits<4> p; 565 bits<8> target; 566 let Inst{11-8} = p; 567 let Inst{7-0} = target; 568} 569 570// Compare and branch on zero / non-zero 571let isBranch = 1, isTerminator = 1 in { 572 def tCBZ : T1I<(outs), (ins tGPR:$Rn, t_cbtarget:$target), IIC_Br, 573 "cbz\t$Rn, $target", []>, 574 T1Misc<{0,0,?,1,?,?,?}> { 575 // A8.6.27 576 bits<6> target; 577 bits<3> Rn; 578 let Inst{9} = target{5}; 579 let Inst{7-3} = target{4-0}; 580 let Inst{2-0} = Rn; 581 } 582 583 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, t_cbtarget:$target), IIC_Br, 584 "cbnz\t$cmp, $target", []>, 585 T1Misc<{1,0,?,1,?,?,?}> { 586 // A8.6.27 587 bits<6> target; 588 bits<3> Rn; 589 let Inst{9} = target{5}; 590 let Inst{7-3} = target{4-0}; 591 let Inst{2-0} = Rn; 592 } 593} 594 595// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only 596// A8.6.16 B: Encoding T1 597// If Inst{11-8} == 0b1111 then SEE SVC 598let isCall = 1, Uses = [SP] in 599def tSVC : T1pI<(outs), (ins i32imm:$imm), IIC_Br, 600 "svc", "\t$imm", []>, Encoding16 { 601 bits<8> imm; 602 let Inst{15-12} = 0b1101; 603 let Inst{11-8} = 0b1111; 604 let Inst{7-0} = imm; 605} 606 607// The assembler uses 0xDEFE for a trap instruction. 608let isBarrier = 1, isTerminator = 1 in 609def tTRAP : TI<(outs), (ins), IIC_Br, 610 "trap", [(trap)]>, Encoding16 { 611 let Inst = 0xdefe; 612} 613 614//===----------------------------------------------------------------------===// 615// Load Store Instructions. 616// 617 618// Loads: reg/reg and reg/imm5 619let canFoldAsLoad = 1, isReMaterializable = 1 in 620multiclass thumb_ld_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 621 Operand AddrMode_r, Operand AddrMode_i, 622 AddrMode am, InstrItinClass itin_r, 623 InstrItinClass itin_i, string asm, 624 PatFrag opnode> { 625 def r : // reg/reg 626 T1pILdStEncode<reg_opc, 627 (outs tGPR:$Rt), (ins AddrMode_r:$addr), 628 am, itin_r, asm, "\t$Rt, $addr", 629 [(set tGPR:$Rt, (opnode AddrMode_r:$addr))]>; 630 def i : // reg/imm5 631 T1pILdStEncodeImm<imm_opc, 1 /* Load */, 632 (outs tGPR:$Rt), (ins AddrMode_i:$addr), 633 am, itin_i, asm, "\t$Rt, $addr", 634 [(set tGPR:$Rt, (opnode AddrMode_i:$addr))]>; 635} 636// Stores: reg/reg and reg/imm5 637multiclass thumb_st_rr_ri_enc<bits<3> reg_opc, bits<4> imm_opc, 638 Operand AddrMode_r, Operand AddrMode_i, 639 AddrMode am, InstrItinClass itin_r, 640 InstrItinClass itin_i, string asm, 641 PatFrag opnode> { 642 def r : // reg/reg 643 T1pILdStEncode<reg_opc, 644 (outs), (ins tGPR:$Rt, AddrMode_r:$addr), 645 am, itin_r, asm, "\t$Rt, $addr", 646 [(opnode tGPR:$Rt, AddrMode_r:$addr)]>; 647 def i : // reg/imm5 648 T1pILdStEncodeImm<imm_opc, 0 /* Store */, 649 (outs), (ins tGPR:$Rt, AddrMode_i:$addr), 650 am, itin_i, asm, "\t$Rt, $addr", 651 [(opnode tGPR:$Rt, AddrMode_i:$addr)]>; 652} 653 654// A8.6.57 & A8.6.60 655defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4, 656 t_addrmode_is4, AddrModeT1_4, 657 IIC_iLoad_r, IIC_iLoad_i, "ldr", 658 UnOpFrag<(load node:$Src)>>; 659 660// A8.6.64 & A8.6.61 661defm tLDRB : thumb_ld_rr_ri_enc<0b110, 0b0111, t_addrmode_rrs1, 662 t_addrmode_is1, AddrModeT1_1, 663 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrb", 664 UnOpFrag<(zextloadi8 node:$Src)>>; 665 666// A8.6.76 & A8.6.73 667defm tLDRH : thumb_ld_rr_ri_enc<0b101, 0b1000, t_addrmode_rrs2, 668 t_addrmode_is2, AddrModeT1_2, 669 IIC_iLoad_bh_r, IIC_iLoad_bh_i, "ldrh", 670 UnOpFrag<(zextloadi16 node:$Src)>>; 671 672let AddedComplexity = 10 in 673def tLDRSB : // A8.6.80 674 T1pILdStEncode<0b011, (outs tGPR:$dst), (ins t_addrmode_rr:$addr), 675 AddrModeT1_1, IIC_iLoad_bh_r, 676 "ldrsb", "\t$dst, $addr", 677 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>; 678 679let AddedComplexity = 10 in 680def tLDRSH : // A8.6.84 681 T1pILdStEncode<0b111, (outs tGPR:$dst), (ins t_addrmode_rr:$addr), 682 AddrModeT1_2, IIC_iLoad_bh_r, 683 "ldrsh", "\t$dst, $addr", 684 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>; 685 686let canFoldAsLoad = 1 in 687def tLDRspi : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 688 "ldr", "\t$Rt, $addr", 689 [(set tGPR:$Rt, (load t_addrmode_sp:$addr))]>, 690 T1LdStSP<{1,?,?}> { 691 bits<3> Rt; 692 bits<8> addr; 693 let Inst{10-8} = Rt; 694 let Inst{7-0} = addr; 695} 696 697// Special instruction for restore. It cannot clobber condition register 698// when it's expanded by eliminateCallFramePseudoInstr(). 699let canFoldAsLoad = 1, mayLoad = 1, neverHasSideEffects = 1 in 700// FIXME: Pseudo for tLDRspi 701def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoad_i, 702 "ldr", "\t$dst, $addr", []>, 703 T1LdStSP<{1,?,?}> { 704 bits<3> Rt; 705 bits<8> addr; 706 let Inst{10-8} = Rt; 707 let Inst{7-0} = addr; 708} 709 710// Load tconstpool 711// FIXME: Use ldr.n to work around a Darwin assembler bug. 712let canFoldAsLoad = 1, isReMaterializable = 1 in 713def tLDRpci : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 714 "ldr", ".n\t$Rt, $addr", 715 [(set tGPR:$Rt, (load (ARMWrapper tconstpool:$addr)))]>, 716 T1Encoding<{0,1,0,0,1,?}> { 717 // A6.2 & A8.6.59 718 bits<3> Rt; 719 bits<8> addr; 720 let Inst{10-8} = Rt; 721 let Inst{7-0} = addr; 722} 723 724// FIXME: Remove this entry when the above ldr.n workaround is fixed. 725// For disassembly use only. 726def tLDRpciDIS : T1pIs<(outs tGPR:$Rt), (ins t_addrmode_pc:$addr), IIC_iLoad_i, 727 "ldr", "\t$Rt, $addr", 728 [/* disassembly only */]>, 729 T1Encoding<{0,1,0,0,1,?}> { 730 // A6.2 & A8.6.59 731 bits<3> Rt; 732 bits<8> addr; 733 let Inst{10-8} = Rt; 734 let Inst{7-0} = addr; 735} 736 737// A8.6.194 & A8.6.192 738defm tSTR : thumb_st_rr_ri_enc<0b000, 0b0110, t_addrmode_rrs4, 739 t_addrmode_is4, AddrModeT1_4, 740 IIC_iStore_r, IIC_iStore_i, "str", 741 BinOpFrag<(store node:$LHS, node:$RHS)>>; 742 743// A8.6.197 & A8.6.195 744defm tSTRB : thumb_st_rr_ri_enc<0b010, 0b0111, t_addrmode_rrs1, 745 t_addrmode_is1, AddrModeT1_1, 746 IIC_iStore_bh_r, IIC_iStore_bh_i, "strb", 747 BinOpFrag<(truncstorei8 node:$LHS, node:$RHS)>>; 748 749// A8.6.207 & A8.6.205 750defm tSTRH : thumb_st_rr_ri_enc<0b001, 0b1000, t_addrmode_rrs2, 751 t_addrmode_is2, AddrModeT1_2, 752 IIC_iStore_bh_r, IIC_iStore_bh_i, "strh", 753 BinOpFrag<(truncstorei16 node:$LHS, node:$RHS)>>; 754 755 756def tSTRspi : T1pIs<(outs), (ins tGPR:$Rt, t_addrmode_sp:$addr), IIC_iStore_i, 757 "str", "\t$Rt, $addr", 758 [(store tGPR:$Rt, t_addrmode_sp:$addr)]>, 759 T1LdStSP<{0,?,?}> { 760 bits<3> Rt; 761 bits<8> addr; 762 let Inst{10-8} = Rt; 763 let Inst{7-0} = addr; 764} 765 766let mayStore = 1, neverHasSideEffects = 1 in 767// Special instruction for spill. It cannot clobber condition register when it's 768// expanded by eliminateCallFramePseudoInstr(). 769// FIXME: Pseudo for tSTRspi 770def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStore_i, 771 "str", "\t$src, $addr", []>, 772 T1LdStSP<{0,?,?}> { 773 bits<3> Rt; 774 bits<8> addr; 775 let Inst{10-8} = Rt; 776 let Inst{7-0} = addr; 777} 778 779//===----------------------------------------------------------------------===// 780// Load / store multiple Instructions. 781// 782 783multiclass thumb_ldst_mult<string asm, InstrItinClass itin, 784 InstrItinClass itin_upd, bits<6> T1Enc, 785 bit L_bit> { 786 def IA : 787 T1I<(outs), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 788 itin, !strconcat(asm, "ia${p}\t$Rn, $regs"), []>, 789 T1Encoding<T1Enc> { 790 bits<3> Rn; 791 bits<8> regs; 792 let Inst{10-8} = Rn; 793 let Inst{7-0} = regs; 794 } 795 def IA_UPD : 796 T1It<(outs GPR:$wb), (ins GPR:$Rn, pred:$p, reglist:$regs, variable_ops), 797 itin_upd, !strconcat(asm, "ia${p}\t$Rn!, $regs"), "$Rn = $wb", []>, 798 T1Encoding<T1Enc> { 799 bits<3> Rn; 800 bits<8> regs; 801 let Inst{10-8} = Rn; 802 let Inst{7-0} = regs; 803 } 804} 805 806// These require base address to be written back or one of the loaded regs. 807let neverHasSideEffects = 1 in { 808 809let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 810defm tLDM : thumb_ldst_mult<"ldm", IIC_iLoad_m, IIC_iLoad_mu, 811 {1,1,0,0,1,?}, 1>; 812 813let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 814defm tSTM : thumb_ldst_mult<"stm", IIC_iStore_m, IIC_iStore_mu, 815 {1,1,0,0,0,?}, 0>; 816 817} // neverHasSideEffects 818 819let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 820def tPOP : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 821 IIC_iPop, 822 "pop${p}\t$regs", []>, 823 T1Misc<{1,1,0,?,?,?,?}> { 824 bits<16> regs; 825 let Inst{8} = regs{15}; 826 let Inst{7-0} = regs{7-0}; 827} 828 829let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 830def tPUSH : T1I<(outs), (ins pred:$p, reglist:$regs, variable_ops), 831 IIC_iStore_m, 832 "push${p}\t$regs", []>, 833 T1Misc<{0,1,0,?,?,?,?}> { 834 bits<16> regs; 835 let Inst{8} = regs{14}; 836 let Inst{7-0} = regs{7-0}; 837} 838 839//===----------------------------------------------------------------------===// 840// Arithmetic Instructions. 841// 842 843// Helper classes for encoding T1pI patterns: 844class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 845 string opc, string asm, list<dag> pattern> 846 : T1pI<oops, iops, itin, opc, asm, pattern>, 847 T1DataProcessing<opA> { 848 bits<3> Rm; 849 bits<3> Rn; 850 let Inst{5-3} = Rm; 851 let Inst{2-0} = Rn; 852} 853class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin, 854 string opc, string asm, list<dag> pattern> 855 : T1pI<oops, iops, itin, opc, asm, pattern>, 856 T1Misc<opA> { 857 bits<3> Rm; 858 bits<3> Rd; 859 let Inst{5-3} = Rm; 860 let Inst{2-0} = Rd; 861} 862 863// Helper classes for encoding T1sI patterns: 864class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 865 string opc, string asm, list<dag> pattern> 866 : T1sI<oops, iops, itin, opc, asm, pattern>, 867 T1DataProcessing<opA> { 868 bits<3> Rd; 869 bits<3> Rn; 870 let Inst{5-3} = Rn; 871 let Inst{2-0} = Rd; 872} 873class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 874 string opc, string asm, list<dag> pattern> 875 : T1sI<oops, iops, itin, opc, asm, pattern>, 876 T1General<opA> { 877 bits<3> Rm; 878 bits<3> Rn; 879 bits<3> Rd; 880 let Inst{8-6} = Rm; 881 let Inst{5-3} = Rn; 882 let Inst{2-0} = Rd; 883} 884class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 885 string opc, string asm, list<dag> pattern> 886 : T1sI<oops, iops, itin, opc, asm, pattern>, 887 T1General<opA> { 888 bits<3> Rd; 889 bits<3> Rm; 890 let Inst{5-3} = Rm; 891 let Inst{2-0} = Rd; 892} 893 894// Helper classes for encoding T1sIt patterns: 895class T1sItDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin, 896 string opc, string asm, list<dag> pattern> 897 : T1sIt<oops, iops, itin, opc, asm, pattern>, 898 T1DataProcessing<opA> { 899 bits<3> Rdn; 900 bits<3> Rm; 901 let Inst{5-3} = Rm; 902 let Inst{2-0} = Rdn; 903} 904class T1sItGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin, 905 string opc, string asm, list<dag> pattern> 906 : T1sIt<oops, iops, itin, opc, asm, pattern>, 907 T1General<opA> { 908 bits<3> Rdn; 909 bits<8> imm8; 910 let Inst{10-8} = Rdn; 911 let Inst{7-0} = imm8; 912} 913 914// Add with carry register 915let isCommutable = 1, Uses = [CPSR] in 916def tADC : // A8.6.2 917 T1sItDPEncode<0b0101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), IIC_iALUr, 918 "adc", "\t$Rdn, $Rm", 919 [(set tGPR:$Rdn, (adde tGPR:$Rn, tGPR:$Rm))]>; 920 921// Add immediate 922def tADDi3 : // A8.6.4 T1 923 T1sIGenEncodeImm<0b01110, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), IIC_iALUi, 924 "add", "\t$Rd, $Rm, $imm3", 925 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7:$imm3))]> { 926 bits<3> imm3; 927 let Inst{8-6} = imm3; 928} 929 930def tADDi8 : // A8.6.4 T2 931 T1sItGenEncodeImm<{1,1,0,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), 932 IIC_iALUi, 933 "add", "\t$Rdn, $imm8", 934 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255:$imm8))]>; 935 936// Add register 937let isCommutable = 1 in 938def tADDrr : // A8.6.6 T1 939 T1sIGenEncode<0b01100, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 940 IIC_iALUr, 941 "add", "\t$Rd, $Rn, $Rm", 942 [(set tGPR:$Rd, (add tGPR:$Rn, tGPR:$Rm))]>; 943 944let neverHasSideEffects = 1 in 945def tADDhirr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iALUr, 946 "add", "\t$Rdn, $Rm", []>, 947 T1Special<{0,0,?,?}> { 948 // A8.6.6 T2 949 bits<4> Rdn; 950 bits<4> Rm; 951 let Inst{7} = Rdn{3}; 952 let Inst{6-3} = Rm; 953 let Inst{2-0} = Rdn{2-0}; 954} 955 956// AND register 957let isCommutable = 1 in 958def tAND : // A8.6.12 959 T1sItDPEncode<0b0000, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 960 IIC_iBITr, 961 "and", "\t$Rdn, $Rm", 962 [(set tGPR:$Rdn, (and tGPR:$Rn, tGPR:$Rm))]>; 963 964// ASR immediate 965def tASRri : // A8.6.14 966 T1sIGenEncodeImm<{0,1,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), 967 IIC_iMOVsi, 968 "asr", "\t$Rd, $Rm, $imm5", 969 [(set tGPR:$Rd, (sra tGPR:$Rm, (i32 imm:$imm5)))]> { 970 bits<5> imm5; 971 let Inst{10-6} = imm5; 972} 973 974// ASR register 975def tASRrr : // A8.6.15 976 T1sItDPEncode<0b0100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 977 IIC_iMOVsr, 978 "asr", "\t$Rdn, $Rm", 979 [(set tGPR:$Rdn, (sra tGPR:$Rn, tGPR:$Rm))]>; 980 981// BIC register 982def tBIC : // A8.6.20 983 T1sItDPEncode<0b1110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 984 IIC_iBITr, 985 "bic", "\t$Rdn, $Rm", 986 [(set tGPR:$Rdn, (and tGPR:$Rn, (not tGPR:$Rm)))]>; 987 988// CMN register 989let isCompare = 1, Defs = [CPSR] in { 990//FIXME: Disable CMN, as CCodes are backwards from compare expectations 991// Compare-to-zero still works out, just not the relationals 992//def tCMN : // A8.6.33 993// T1pIDPEncode<0b1011, (outs), (ins tGPR:$lhs, tGPR:$rhs), 994// IIC_iCMPr, 995// "cmn", "\t$lhs, $rhs", 996// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>; 997 998def tCMNz : // A8.6.33 999 T1pIDPEncode<0b1011, (outs), (ins tGPR:$Rn, tGPR:$Rm), 1000 IIC_iCMPr, 1001 "cmn", "\t$Rn, $Rm", 1002 [(ARMcmpZ tGPR:$Rn, (ineg tGPR:$Rm))]>; 1003 1004} // isCompare = 1, Defs = [CPSR] 1005 1006// CMP immediate 1007let isCompare = 1, Defs = [CPSR] in { 1008def tCMPi8 : T1pI<(outs), (ins tGPR:$Rn, i32imm:$imm8), IIC_iCMPi, 1009 "cmp", "\t$Rn, $imm8", 1010 [(ARMcmp tGPR:$Rn, imm0_255:$imm8)]>, 1011 T1General<{1,0,1,?,?}> { 1012 // A8.6.35 1013 bits<3> Rn; 1014 bits<8> imm8; 1015 let Inst{10-8} = Rn; 1016 let Inst{7-0} = imm8; 1017} 1018 1019// CMP register 1020def tCMPr : // A8.6.36 T1 1021 T1pIDPEncode<0b1010, (outs), (ins tGPR:$Rn, tGPR:$Rm), 1022 IIC_iCMPr, 1023 "cmp", "\t$Rn, $Rm", 1024 [(ARMcmp tGPR:$Rn, tGPR:$Rm)]>; 1025 1026def tCMPhir : T1pI<(outs), (ins GPR:$Rn, GPR:$Rm), IIC_iCMPr, 1027 "cmp", "\t$Rn, $Rm", []>, 1028 T1Special<{0,1,?,?}> { 1029 // A8.6.36 T2 1030 bits<4> Rm; 1031 bits<4> Rn; 1032 let Inst{7} = Rn{3}; 1033 let Inst{6-3} = Rm; 1034 let Inst{2-0} = Rn{2-0}; 1035} 1036} // isCompare = 1, Defs = [CPSR] 1037 1038 1039// XOR register 1040let isCommutable = 1 in 1041def tEOR : // A8.6.45 1042 T1sItDPEncode<0b0001, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1043 IIC_iBITr, 1044 "eor", "\t$Rdn, $Rm", 1045 [(set tGPR:$Rdn, (xor tGPR:$Rn, tGPR:$Rm))]>; 1046 1047// LSL immediate 1048def tLSLri : // A8.6.88 1049 T1sIGenEncodeImm<{0,0,0,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), 1050 IIC_iMOVsi, 1051 "lsl", "\t$Rd, $Rm, $imm5", 1052 [(set tGPR:$Rd, (shl tGPR:$Rm, (i32 imm:$imm5)))]> { 1053 bits<5> imm5; 1054 let Inst{10-6} = imm5; 1055} 1056 1057// LSL register 1058def tLSLrr : // A8.6.89 1059 T1sItDPEncode<0b0010, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1060 IIC_iMOVsr, 1061 "lsl", "\t$Rdn, $Rm", 1062 [(set tGPR:$Rdn, (shl tGPR:$Rn, tGPR:$Rm))]>; 1063 1064// LSR immediate 1065def tLSRri : // A8.6.90 1066 T1sIGenEncodeImm<{0,0,1,?,?}, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm5), 1067 IIC_iMOVsi, 1068 "lsr", "\t$Rd, $Rm, $imm5", 1069 [(set tGPR:$Rd, (srl tGPR:$Rm, (i32 imm:$imm5)))]> { 1070 bits<5> imm5; 1071 let Inst{10-6} = imm5; 1072} 1073 1074// LSR register 1075def tLSRrr : // A8.6.91 1076 T1sItDPEncode<0b0011, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1077 IIC_iMOVsr, 1078 "lsr", "\t$Rdn, $Rm", 1079 [(set tGPR:$Rdn, (srl tGPR:$Rn, tGPR:$Rm))]>; 1080 1081// Move register 1082let isMoveImm = 1 in 1083def tMOVi8 : T1sI<(outs tGPR:$Rd), (ins i32imm:$imm8), IIC_iMOVi, 1084 "mov", "\t$Rd, $imm8", 1085 [(set tGPR:$Rd, imm0_255:$imm8)]>, 1086 T1General<{1,0,0,?,?}> { 1087 // A8.6.96 1088 bits<3> Rd; 1089 bits<8> imm8; 1090 let Inst{10-8} = Rd; 1091 let Inst{7-0} = imm8; 1092} 1093 1094// TODO: A7-73: MOV(2) - mov setting flag. 1095 1096let neverHasSideEffects = 1 in { 1097// FIXME: Make this predicable. 1098def tMOVr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1099 "mov\t$Rd, $Rm", []>, 1100 T1Special<0b1000> { 1101 // A8.6.97 1102 bits<4> Rd; 1103 bits<4> Rm; 1104 // Bits {7-6} are encoded by the T1Special value. 1105 let Inst{5-3} = Rm{2-0}; 1106 let Inst{2-0} = Rd{2-0}; 1107} 1108let Defs = [CPSR] in 1109def tMOVSr : T1I<(outs tGPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1110 "movs\t$Rd, $Rm", []>, Encoding16 { 1111 // A8.6.97 1112 bits<3> Rd; 1113 bits<3> Rm; 1114 let Inst{15-6} = 0b0000000000; 1115 let Inst{5-3} = Rm; 1116 let Inst{2-0} = Rd; 1117} 1118 1119// FIXME: Make these predicable. 1120def tMOVgpr2tgpr : T1I<(outs tGPR:$Rd), (ins GPR:$Rm), IIC_iMOVr, 1121 "mov\t$Rd, $Rm", []>, 1122 T1Special<{1,0,0,?}> { 1123 // A8.6.97 1124 bits<4> Rd; 1125 bits<4> Rm; 1126 // Bit {7} is encoded by the T1Special value. 1127 let Inst{6-3} = Rm; 1128 let Inst{2-0} = Rd{2-0}; 1129} 1130def tMOVtgpr2gpr : T1I<(outs GPR:$Rd), (ins tGPR:$Rm), IIC_iMOVr, 1131 "mov\t$Rd, $Rm", []>, 1132 T1Special<{1,0,?,0}> { 1133 // A8.6.97 1134 bits<4> Rd; 1135 bits<4> Rm; 1136 // Bit {6} is encoded by the T1Special value. 1137 let Inst{7} = Rd{3}; 1138 let Inst{5-3} = Rm{2-0}; 1139 let Inst{2-0} = Rd{2-0}; 1140} 1141def tMOVgpr2gpr : T1I<(outs GPR:$Rd), (ins GPR:$Rm), IIC_iMOVr, 1142 "mov\t$Rd, $Rm", []>, 1143 T1Special<{1,0,?,?}> { 1144 // A8.6.97 1145 bits<4> Rd; 1146 bits<4> Rm; 1147 let Inst{7} = Rd{3}; 1148 let Inst{6-3} = Rm; 1149 let Inst{2-0} = Rd{2-0}; 1150} 1151} // neverHasSideEffects 1152 1153// Multiply register 1154let isCommutable = 1 in 1155def tMUL : // A8.6.105 T1 1156 T1sItDPEncode<0b1101, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1157 IIC_iMUL32, 1158 "mul", "\t$Rdn, $Rm, $Rdn", 1159 [(set tGPR:$Rdn, (mul tGPR:$Rn, tGPR:$Rm))]>; 1160 1161// Move inverse register 1162def tMVN : // A8.6.107 1163 T1sIDPEncode<0b1111, (outs tGPR:$Rd), (ins tGPR:$Rn), IIC_iMVNr, 1164 "mvn", "\t$Rd, $Rn", 1165 [(set tGPR:$Rd, (not tGPR:$Rn))]>; 1166 1167// Bitwise or register 1168let isCommutable = 1 in 1169def tORR : // A8.6.114 1170 T1sItDPEncode<0b1100, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1171 IIC_iBITr, 1172 "orr", "\t$Rdn, $Rm", 1173 [(set tGPR:$Rdn, (or tGPR:$Rn, tGPR:$Rm))]>; 1174 1175// Swaps 1176def tREV : // A8.6.134 1177 T1pIMiscEncode<{1,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1178 IIC_iUNAr, 1179 "rev", "\t$Rd, $Rm", 1180 [(set tGPR:$Rd, (bswap tGPR:$Rm))]>, 1181 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1182 1183def tREV16 : // A8.6.135 1184 T1pIMiscEncode<{1,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1185 IIC_iUNAr, 1186 "rev16", "\t$Rd, $Rm", 1187 [(set tGPR:$Rd, 1188 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF), 1189 (or (and (shl tGPR:$Rm, (i32 8)), 0xFF00), 1190 (or (and (srl tGPR:$Rm, (i32 8)), 0xFF0000), 1191 (and (shl tGPR:$Rm, (i32 8)), 0xFF000000)))))]>, 1192 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1193 1194def tREVSH : // A8.6.136 1195 T1pIMiscEncode<{1,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1196 IIC_iUNAr, 1197 "revsh", "\t$Rd, $Rm", 1198 [(set tGPR:$Rd, 1199 (sext_inreg 1200 (or (srl tGPR:$Rm, (i32 8)), 1201 (shl tGPR:$Rm, (i32 8))), i16))]>, 1202 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1203 1204def : T1Pat<(sext_inreg (or (srl (and tGPR:$Rm, 0xFF00), (i32 8)), 1205 (shl tGPR:$Rm, (i32 8))), i16), 1206 (tREVSH tGPR:$Rm)>, 1207 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1208 1209def : T1Pat<(sra (bswap tGPR:$Rm), (i32 16)), (tREVSH tGPR:$Rm)>, 1210 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1211 1212// Rotate right register 1213def tROR : // A8.6.139 1214 T1sItDPEncode<0b0111, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1215 IIC_iMOVsr, 1216 "ror", "\t$Rdn, $Rm", 1217 [(set tGPR:$Rdn, (rotr tGPR:$Rn, tGPR:$Rm))]>; 1218 1219// Negate register 1220def tRSB : // A8.6.141 1221 T1sIDPEncode<0b1001, (outs tGPR:$Rd), (ins tGPR:$Rn), 1222 IIC_iALUi, 1223 "rsb", "\t$Rd, $Rn, #0", 1224 [(set tGPR:$Rd, (ineg tGPR:$Rn))]>; 1225 1226// Subtract with carry register 1227let Uses = [CPSR] in 1228def tSBC : // A8.6.151 1229 T1sItDPEncode<0b0110, (outs tGPR:$Rdn), (ins tGPR:$Rn, tGPR:$Rm), 1230 IIC_iALUr, 1231 "sbc", "\t$Rdn, $Rm", 1232 [(set tGPR:$Rdn, (sube tGPR:$Rn, tGPR:$Rm))]>; 1233 1234// Subtract immediate 1235def tSUBi3 : // A8.6.210 T1 1236 T1sIGenEncodeImm<0b01111, (outs tGPR:$Rd), (ins tGPR:$Rm, i32imm:$imm3), 1237 IIC_iALUi, 1238 "sub", "\t$Rd, $Rm, $imm3", 1239 [(set tGPR:$Rd, (add tGPR:$Rm, imm0_7_neg:$imm3))]> { 1240 bits<3> imm3; 1241 let Inst{8-6} = imm3; 1242} 1243 1244def tSUBi8 : // A8.6.210 T2 1245 T1sItGenEncodeImm<{1,1,1,?,?}, (outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$imm8), 1246 IIC_iALUi, 1247 "sub", "\t$Rdn, $imm8", 1248 [(set tGPR:$Rdn, (add tGPR:$Rn, imm8_255_neg:$imm8))]>; 1249 1250// Subtract register 1251def tSUBrr : // A8.6.212 1252 T1sIGenEncode<0b01101, (outs tGPR:$Rd), (ins tGPR:$Rn, tGPR:$Rm), 1253 IIC_iALUr, 1254 "sub", "\t$Rd, $Rn, $Rm", 1255 [(set tGPR:$Rd, (sub tGPR:$Rn, tGPR:$Rm))]>; 1256 1257// TODO: A7-96: STMIA - store multiple. 1258 1259// Sign-extend byte 1260def tSXTB : // A8.6.222 1261 T1pIMiscEncode<{0,0,1,0,0,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1262 IIC_iUNAr, 1263 "sxtb", "\t$Rd, $Rm", 1264 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i8))]>, 1265 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1266 1267// Sign-extend short 1268def tSXTH : // A8.6.224 1269 T1pIMiscEncode<{0,0,1,0,0,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1270 IIC_iUNAr, 1271 "sxth", "\t$Rd, $Rm", 1272 [(set tGPR:$Rd, (sext_inreg tGPR:$Rm, i16))]>, 1273 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1274 1275// Test 1276let isCompare = 1, isCommutable = 1, Defs = [CPSR] in 1277def tTST : // A8.6.230 1278 T1pIDPEncode<0b1000, (outs), (ins tGPR:$Rn, tGPR:$Rm), IIC_iTSTr, 1279 "tst", "\t$Rn, $Rm", 1280 [(ARMcmpZ (and_su tGPR:$Rn, tGPR:$Rm), 0)]>; 1281 1282// Zero-extend byte 1283def tUXTB : // A8.6.262 1284 T1pIMiscEncode<{0,0,1,0,1,1,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1285 IIC_iUNAr, 1286 "uxtb", "\t$Rd, $Rm", 1287 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFF))]>, 1288 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1289 1290// Zero-extend short 1291def tUXTH : // A8.6.264 1292 T1pIMiscEncode<{0,0,1,0,1,0,?}, (outs tGPR:$Rd), (ins tGPR:$Rm), 1293 IIC_iUNAr, 1294 "uxth", "\t$Rd, $Rm", 1295 [(set tGPR:$Rd, (and tGPR:$Rm, 0xFFFF))]>, 1296 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1297 1298// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 1299// Expanded after instruction selection into a branch sequence. 1300let usesCustomInserter = 1 in // Expanded after instruction selection. 1301 def tMOVCCr_pseudo : 1302 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 1303 NoItinerary, 1304 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 1305 1306 1307// 16-bit movcc in IT blocks for Thumb2. 1308let neverHasSideEffects = 1 in { 1309def tMOVCCr : T1pIt<(outs GPR:$Rdn), (ins GPR:$Rn, GPR:$Rm), IIC_iCMOVr, 1310 "mov", "\t$Rdn, $Rm", []>, 1311 T1Special<{1,0,?,?}> { 1312 bits<4> Rdn; 1313 bits<4> Rm; 1314 let Inst{7} = Rdn{3}; 1315 let Inst{6-3} = Rm; 1316 let Inst{2-0} = Rdn{2-0}; 1317} 1318 1319let isMoveImm = 1 in 1320def tMOVCCi : T1pIt<(outs tGPR:$Rdn), (ins tGPR:$Rn, i32imm:$Rm), IIC_iCMOVi, 1321 "mov", "\t$Rdn, $Rm", []>, 1322 T1General<{1,0,0,?,?}> { 1323 bits<3> Rdn; 1324 bits<8> Rm; 1325 let Inst{10-8} = Rdn; 1326 let Inst{7-0} = Rm; 1327} 1328 1329} // neverHasSideEffects 1330 1331// tLEApcrel - Load a pc-relative address into a register without offending the 1332// assembler. 1333 1334def tADR : T1I<(outs tGPR:$Rd), (ins t_adrlabel:$addr, pred:$p), 1335 IIC_iALUi, "adr{$p}\t$Rd, #$addr", []>, 1336 T1Encoding<{1,0,1,0,0,?}> { 1337 bits<3> Rd; 1338 bits<8> addr; 1339 let Inst{10-8} = Rd; 1340 let Inst{7-0} = addr; 1341} 1342 1343let neverHasSideEffects = 1, isReMaterializable = 1 in 1344def tLEApcrel : tPseudoInst<(outs tGPR:$Rd), (ins i32imm:$label, pred:$p), 1345 Size2Bytes, IIC_iALUi, []>; 1346 1347def tLEApcrelJT : tPseudoInst<(outs tGPR:$Rd), 1348 (ins i32imm:$label, nohash_imm:$id, pred:$p), 1349 Size2Bytes, IIC_iALUi, []>; 1350 1351//===----------------------------------------------------------------------===// 1352// Move between coprocessor and ARM core register -- for disassembly only 1353// 1354 1355class tMovRCopro<string opc, bit direction, dag oops, dag iops> 1356 : T1Cop<oops, iops, !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"), 1357 [/* For disassembly only; pattern left blank */]> { 1358 let Inst{27-24} = 0b1110; 1359 let Inst{20} = direction; 1360 let Inst{4} = 1; 1361 1362 bits<4> Rt; 1363 bits<4> cop; 1364 bits<3> opc1; 1365 bits<3> opc2; 1366 bits<4> CRm; 1367 bits<4> CRn; 1368 1369 let Inst{15-12} = Rt; 1370 let Inst{11-8} = cop; 1371 let Inst{23-21} = opc1; 1372 let Inst{7-5} = opc2; 1373 let Inst{3-0} = CRm; 1374 let Inst{19-16} = CRn; 1375} 1376 1377def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */, 1378 (outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, c_imm:$CRn, 1379 c_imm:$CRm, i32imm:$opc2)>; 1380def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */, 1381 (outs GPR:$Rt), (ins p_imm:$cop, i32imm:$opc1, c_imm:$CRn, 1382 c_imm:$CRm, i32imm:$opc2)>; 1383 1384class tMovRRCopro<string opc, bit direction> 1385 : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm), 1386 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), 1387 [/* For disassembly only; pattern left blank */]> { 1388 let Inst{27-24} = 0b1100; 1389 let Inst{23-21} = 0b010; 1390 let Inst{20} = direction; 1391 1392 bits<4> Rt; 1393 bits<4> Rt2; 1394 bits<4> cop; 1395 bits<4> opc1; 1396 bits<4> CRm; 1397 1398 let Inst{15-12} = Rt; 1399 let Inst{19-16} = Rt2; 1400 let Inst{11-8} = cop; 1401 let Inst{7-4} = opc1; 1402 let Inst{3-0} = CRm; 1403} 1404 1405def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>; 1406def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>; 1407 1408//===----------------------------------------------------------------------===// 1409// Other Coprocessor Instructions. For disassembly only. 1410// 1411def tCDP : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, 1412 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2), 1413 "cdp\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2", 1414 [/* For disassembly only; pattern left blank */]> { 1415 let Inst{27-24} = 0b1110; 1416 1417 bits<4> opc1; 1418 bits<4> CRn; 1419 bits<4> CRd; 1420 bits<4> cop; 1421 bits<3> opc2; 1422 bits<4> CRm; 1423 1424 let Inst{3-0} = CRm; 1425 let Inst{4} = 0; 1426 let Inst{7-5} = opc2; 1427 let Inst{11-8} = cop; 1428 let Inst{15-12} = CRd; 1429 let Inst{19-16} = CRn; 1430 let Inst{23-20} = opc1; 1431} 1432 1433//===----------------------------------------------------------------------===// 1434// TLS Instructions 1435// 1436 1437// __aeabi_read_tp preserves the registers r1-r3. 1438let isCall = 1, Defs = [R0, LR], Uses = [SP] in 1439def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br, 1440 "bl\t__aeabi_read_tp", 1441 [(set R0, ARMthread_pointer)]> { 1442 // Encoding is 0xf7fffffe. 1443 let Inst = 0xf7fffffe; 1444} 1445 1446//===----------------------------------------------------------------------===// 1447// SJLJ Exception handling intrinsics 1448// 1449 1450// eh_sjlj_setjmp() is an instruction sequence to store the return address and 1451// save #0 in R0 for the non-longjmp case. Since by its nature we may be coming 1452// from some other function to get here, and we're using the stack frame for the 1453// containing function to save/restore registers, we can't keep anything live in 1454// regs across the eh_sjlj_setjmp(), else it will almost certainly have been 1455// tromped upon when we get here from a longjmp(). We force everything out of 1456// registers except for our own input by listing the relevant registers in 1457// Defs. By doing so, we also cause the prologue/epilogue code to actively 1458// preserve all of the callee-saved resgisters, which is exactly what we want. 1459// $val is a scratch register for our use. 1460let Defs = [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ], 1461 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1 in 1462def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 1463 AddrModeNone, SizeSpecial, NoItinerary, "","", 1464 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 1465 1466// FIXME: Non-Darwin version(s) 1467let isBarrier = 1, hasSideEffects = 1, isTerminator = 1, isCodeGenOnly = 1, 1468 Defs = [ R7, LR, SP ] in 1469def tInt_eh_sjlj_longjmp : XI<(outs), (ins GPR:$src, GPR:$scratch), 1470 AddrModeNone, SizeSpecial, IndexModeNone, 1471 Pseudo, NoItinerary, "", "", 1472 [(ARMeh_sjlj_longjmp GPR:$src, GPR:$scratch)]>, 1473 Requires<[IsThumb, IsDarwin]>; 1474 1475//===----------------------------------------------------------------------===// 1476// Non-Instruction Patterns 1477// 1478 1479// Comparisons 1480def : T1Pat<(ARMcmpZ tGPR:$Rn, imm0_255:$imm8), 1481 (tCMPi8 tGPR:$Rn, imm0_255:$imm8)>; 1482def : T1Pat<(ARMcmpZ tGPR:$Rn, tGPR:$Rm), 1483 (tCMPr tGPR:$Rn, tGPR:$Rm)>; 1484 1485// Add with carry 1486def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 1487 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 1488def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 1489 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 1490def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 1491 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 1492 1493// Subtract with carry 1494def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 1495 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 1496def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 1497 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 1498def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 1499 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 1500 1501// ConstantPool, GlobalAddress 1502def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 1503def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 1504 1505// JumpTable 1506def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 1507 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 1508 1509// Direct calls 1510def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 1511 Requires<[IsThumb, IsNotDarwin]>; 1512def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>, 1513 Requires<[IsThumb, IsDarwin]>; 1514 1515def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 1516 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 1517def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>, 1518 Requires<[IsThumb, HasV5T, IsDarwin]>; 1519 1520// Indirect calls to ARM routines 1521def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 1522 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 1523def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>, 1524 Requires<[IsThumb, HasV5T, IsDarwin]>; 1525 1526// zextload i1 -> zextload i8 1527def : T1Pat<(zextloadi1 t_addrmode_rrs1:$addr), 1528 (tLDRBr t_addrmode_rrs1:$addr)>; 1529def : T1Pat<(zextloadi1 t_addrmode_is1:$addr), 1530 (tLDRBi t_addrmode_is1:$addr)>; 1531 1532// extload -> zextload 1533def : T1Pat<(extloadi1 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1534def : T1Pat<(extloadi1 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1535def : T1Pat<(extloadi8 t_addrmode_rrs1:$addr), (tLDRBr t_addrmode_rrs1:$addr)>; 1536def : T1Pat<(extloadi8 t_addrmode_is1:$addr), (tLDRBi t_addrmode_is1:$addr)>; 1537def : T1Pat<(extloadi16 t_addrmode_rrs2:$addr), (tLDRHr t_addrmode_rrs2:$addr)>; 1538def : T1Pat<(extloadi16 t_addrmode_is2:$addr), (tLDRHi t_addrmode_is2:$addr)>; 1539 1540// If it's impossible to use [r,r] address mode for sextload, select to 1541// ldr{b|h} + sxt{b|h} instead. 1542def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1543 (tSXTB (tLDRBi t_addrmode_is1:$addr))>, 1544 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1545def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1546 (tSXTB (tLDRBr t_addrmode_rrs1:$addr))>, 1547 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1548def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1549 (tSXTH (tLDRHi t_addrmode_is2:$addr))>, 1550 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1551def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1552 (tSXTH (tLDRHr t_addrmode_rrs2:$addr))>, 1553 Requires<[IsThumb, IsThumb1Only, HasV6]>; 1554 1555def : T1Pat<(sextloadi8 t_addrmode_rrs1:$addr), 1556 (tASRri (tLSLri (tLDRBr t_addrmode_rrs1:$addr), 24), 24)>; 1557def : T1Pat<(sextloadi8 t_addrmode_is1:$addr), 1558 (tASRri (tLSLri (tLDRBi t_addrmode_is1:$addr), 24), 24)>; 1559def : T1Pat<(sextloadi16 t_addrmode_rrs2:$addr), 1560 (tASRri (tLSLri (tLDRHr t_addrmode_rrs2:$addr), 16), 16)>; 1561def : T1Pat<(sextloadi16 t_addrmode_is2:$addr), 1562 (tASRri (tLSLri (tLDRHi t_addrmode_is2:$addr), 16), 16)>; 1563 1564// Large immediate handling. 1565 1566// Two piece imms. 1567def : T1Pat<(i32 thumb_immshifted:$src), 1568 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1569 (thumb_immshifted_shamt imm:$src))>; 1570 1571def : T1Pat<(i32 imm0_255_comp:$src), 1572 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1573 1574// Pseudo instruction that combines ldr from constpool and add pc. This should 1575// be expanded into two instructions late to allow if-conversion and 1576// scheduling. 1577let isReMaterializable = 1 in 1578def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1579 NoItinerary, 1580 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1581 imm:$cp))]>, 1582 Requires<[IsThumb, IsThumb1Only]>; 1583