ARMInstrThumb.td revision 205218
1//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 20 21def imm_neg_XFORM : SDNodeXForm<imm, [{ 22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 23}]>; 24def imm_comp_XFORM : SDNodeXForm<imm, [{ 25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 26}]>; 27 28 29/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7]. 30def imm0_7 : PatLeaf<(i32 imm), [{ 31 return (uint32_t)N->getZExtValue() < 8; 32}]>; 33def imm0_7_neg : PatLeaf<(i32 imm), [{ 34 return (uint32_t)-N->getZExtValue() < 8; 35}], imm_neg_XFORM>; 36 37def imm0_255 : PatLeaf<(i32 imm), [{ 38 return (uint32_t)N->getZExtValue() < 256; 39}]>; 40def imm0_255_comp : PatLeaf<(i32 imm), [{ 41 return ~((uint32_t)N->getZExtValue()) < 256; 42}]>; 43 44def imm8_255 : PatLeaf<(i32 imm), [{ 45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256; 46}]>; 47def imm8_255_neg : PatLeaf<(i32 imm), [{ 48 unsigned Val = -N->getZExtValue(); 49 return Val >= 8 && Val < 256; 50}], imm_neg_XFORM>; 51 52// Break imm's up into two pieces: an immediate + a left shift. 53// This uses thumb_immshifted to match and thumb_immshifted_val and 54// thumb_immshifted_shamt to get the val/shift pieces. 55def thumb_immshifted : PatLeaf<(imm), [{ 56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 57}]>; 58 59def thumb_immshifted_val : SDNodeXForm<imm, [{ 60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 61 return CurDAG->getTargetConstant(V, MVT::i32); 62}]>; 63 64def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 66 return CurDAG->getTargetConstant(V, MVT::i32); 67}]>; 68 69// Scaled 4 immediate. 70def t_imm_s4 : Operand<i32> { 71 let PrintMethod = "printThumbS4ImmOperand"; 72} 73 74// Define Thumb specific addressing modes. 75 76// t_addrmode_rr := reg + reg 77// 78def t_addrmode_rr : Operand<i32>, 79 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 80 let PrintMethod = "printThumbAddrModeRROperand"; 81 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 82} 83 84// t_addrmode_s4 := reg + reg 85// reg + imm5 * 4 86// 87def t_addrmode_s4 : Operand<i32>, 88 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> { 89 let PrintMethod = "printThumbAddrModeS4Operand"; 90 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 91} 92 93// t_addrmode_s2 := reg + reg 94// reg + imm5 * 2 95// 96def t_addrmode_s2 : Operand<i32>, 97 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> { 98 let PrintMethod = "printThumbAddrModeS2Operand"; 99 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 100} 101 102// t_addrmode_s1 := reg + reg 103// reg + imm5 104// 105def t_addrmode_s1 : Operand<i32>, 106 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> { 107 let PrintMethod = "printThumbAddrModeS1Operand"; 108 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 109} 110 111// t_addrmode_sp := sp + imm8 * 4 112// 113def t_addrmode_sp : Operand<i32>, 114 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 115 let PrintMethod = "printThumbAddrModeSPOperand"; 116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 117} 118 119//===----------------------------------------------------------------------===// 120// Miscellaneous Instructions. 121// 122 123// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE 124// from removing one half of the matched pairs. That breaks PEI, which assumes 125// these will always be in pairs, and asserts if it finds otherwise. Better way? 126let Defs = [SP], Uses = [SP], hasSideEffects = 1 in { 127def tADJCALLSTACKUP : 128PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 129 "@ tADJCALLSTACKUP $amt1", 130 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>; 131 132def tADJCALLSTACKDOWN : 133PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 134 "@ tADJCALLSTACKDOWN $amt", 135 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>; 136} 137 138def tNOP : T1pI<(outs), (ins), NoItinerary, "nop", "", 139 [/* For disassembly only; pattern left blank */]>, 140 T1Encoding<0b101111> { 141 let Inst{9-8} = 0b11; 142 let Inst{7-0} = 0b00000000; 143} 144 145def tYIELD : T1pI<(outs), (ins), NoItinerary, "yield", "", 146 [/* For disassembly only; pattern left blank */]>, 147 T1Encoding<0b101111> { 148 let Inst{9-8} = 0b11; 149 let Inst{7-0} = 0b00010000; 150} 151 152def tWFE : T1pI<(outs), (ins), NoItinerary, "wfe", "", 153 [/* For disassembly only; pattern left blank */]>, 154 T1Encoding<0b101111> { 155 let Inst{9-8} = 0b11; 156 let Inst{7-0} = 0b00100000; 157} 158 159def tWFI : T1pI<(outs), (ins), NoItinerary, "wfi", "", 160 [/* For disassembly only; pattern left blank */]>, 161 T1Encoding<0b101111> { 162 let Inst{9-8} = 0b11; 163 let Inst{7-0} = 0b00110000; 164} 165 166def tSEV : T1pI<(outs), (ins), NoItinerary, "sev", "", 167 [/* For disassembly only; pattern left blank */]>, 168 T1Encoding<0b101111> { 169 let Inst{9-8} = 0b11; 170 let Inst{7-0} = 0b01000000; 171} 172 173def tSETENDBE : T1I<(outs), (ins), NoItinerary, "setend\tbe", 174 [/* For disassembly only; pattern left blank */]>, 175 T1Encoding<0b101101> { 176 let Inst{9-5} = 0b10010; 177 let Inst{3} = 1; 178} 179 180def tSETENDLE : T1I<(outs), (ins), NoItinerary, "setend\tle", 181 [/* For disassembly only; pattern left blank */]>, 182 T1Encoding<0b101101> { 183 let Inst{9-5} = 0b10010; 184 let Inst{3} = 0; 185} 186 187// The i32imm operand $val can be used by a debugger to store more information 188// about the breakpoint. 189def tBKPT : T1I<(outs), (ins i32imm:$val), NoItinerary, "bkpt\t$val", 190 [/* For disassembly only; pattern left blank */]>, 191 T1Encoding<0b101111> { 192 let Inst{9-8} = 0b10; 193} 194 195// Change Processor State is a system instruction -- for disassembly only. 196// The singleton $opt operand contains the following information: 197// opt{4-0} = mode ==> don't care 198// opt{5} = changemode ==> 0 (false for 16-bit Thumb instr) 199// opt{8-6} = AIF from Inst{2-0} 200// opt{10-9} = 1:imod from Inst{4} with 0b10 as enable and 0b11 as disable 201// 202// The opt{4-0} and opt{5} sub-fields are to accommodate 32-bit Thumb and ARM 203// CPS which has more options. 204def tCPS : T1I<(outs), (ins cps_opt:$opt), NoItinerary, "cps$opt", 205 [/* For disassembly only; pattern left blank */]>, 206 T1Misc<0b0110011>; 207 208// For both thumb1 and thumb2. 209let isNotDuplicable = 1 in 210def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, 211 "\n$cp:\n\tadd\t$dst, pc", 212 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 213 T1Special<{0,0,?,?}> { 214 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc 215} 216 217// PC relative add. 218def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi, 219 "add\t$dst, pc, $rhs", []>, 220 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10 221 222// ADD rd, sp, #imm8 223def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi, 224 "add\t$dst, $sp, $rhs", []>, 225 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8 226 227// ADD sp, sp, #imm7 228def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 229 "add\t$dst, $rhs", []>, 230 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8 231 232// SUB sp, sp, #imm7 233def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 234 "sub\t$dst, $rhs", []>, 235 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215 236 237// ADD rm, sp 238def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 239 "add\t$dst, $rhs", []>, 240 T1Special<{0,0,?,?}> { 241 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1 242} 243 244// ADD sp, rm 245def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 246 "add\t$dst, $rhs", []>, 247 T1Special<{0,0,?,?}> { 248 // A8.6.9 Encoding T2 249 let Inst{7} = 1; 250 let Inst{2-0} = 0b101; 251} 252 253// Pseudo instruction that will expand into a tSUBspi + a copy. 254let usesCustomInserter = 1 in { // Expanded after instruction selection. 255def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), 256 NoItinerary, "@ sub\t$dst, $rhs", []>; 257 258def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 259 NoItinerary, "@ add\t$dst, $rhs", []>; 260 261let Defs = [CPSR] in 262def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), 263 NoItinerary, "@ and\t$dst, $rhs", []>; 264} // usesCustomInserter 265 266//===----------------------------------------------------------------------===// 267// Control Flow Instructions. 268// 269 270let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 271 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>, 272 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25 273 let Inst{6-3} = 0b1110; // Rm = lr 274 } 275 // Alternative return instruction used by vararg functions. 276 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target",[]>, 277 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25 278} 279 280// Indirect branches 281let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 282 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst", 283 [(brind GPR:$dst)]>, 284 T1Special<{1,0,1,?}> { 285 // <Rd> = Inst{7:2-0} = pc 286 let Inst{2-0} = 0b111; 287 } 288} 289 290// FIXME: remove when we have a way to marking a MI with these properties. 291let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 292 hasExtraDefRegAllocReq = 1 in 293def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), IIC_Br, 294 "pop${p}\t$dsts", []>, 295 T1Misc<{1,1,0,?,?,?,?}>; 296 297let isCall = 1, 298 Defs = [R0, R1, R2, R3, R12, LR, 299 D0, D1, D2, D3, D4, D5, D6, D7, 300 D16, D17, D18, D19, D20, D21, D22, D23, 301 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 302 // Also used for Thumb2 303 def tBL : TIx2<0b11110, 0b11, 1, 304 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 305 "bl\t${func:call}", 306 [(ARMtcall tglobaladdr:$func)]>, 307 Requires<[IsThumb, IsNotDarwin]>; 308 309 // ARMv5T and above, also used for Thumb2 310 def tBLXi : TIx2<0b11110, 0b11, 0, 311 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 312 "blx\t${func:call}", 313 [(ARMcall tglobaladdr:$func)]>, 314 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 315 316 // Also used for Thumb2 317 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, 318 "blx\t$func", 319 [(ARMtcall GPR:$func)]>, 320 Requires<[IsThumb, HasV5T, IsNotDarwin]>, 321 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24; 322 323 // ARMv4T 324 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?, 325 (outs), (ins tGPR:$func, variable_ops), IIC_Br, 326 "mov\tlr, pc\n\tbx\t$func", 327 [(ARMcall_nolink tGPR:$func)]>, 328 Requires<[IsThumb1Only, IsNotDarwin]>; 329} 330 331// On Darwin R9 is call-clobbered. 332let isCall = 1, 333 Defs = [R0, R1, R2, R3, R9, R12, LR, 334 D0, D1, D2, D3, D4, D5, D6, D7, 335 D16, D17, D18, D19, D20, D21, D22, D23, 336 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 337 // Also used for Thumb2 338 def tBLr9 : TIx2<0b11110, 0b11, 1, 339 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 340 "bl\t${func:call}", 341 [(ARMtcall tglobaladdr:$func)]>, 342 Requires<[IsThumb, IsDarwin]>; 343 344 // ARMv5T and above, also used for Thumb2 345 def tBLXi_r9 : TIx2<0b11110, 0b11, 0, 346 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 347 "blx\t${func:call}", 348 [(ARMcall tglobaladdr:$func)]>, 349 Requires<[IsThumb, HasV5T, IsDarwin]>; 350 351 // Also used for Thumb2 352 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, 353 "blx\t$func", 354 [(ARMtcall GPR:$func)]>, 355 Requires<[IsThumb, HasV5T, IsDarwin]>, 356 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24 357 358 // ARMv4T 359 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?, 360 (outs), (ins tGPR:$func, variable_ops), IIC_Br, 361 "mov\tlr, pc\n\tbx\t$func", 362 [(ARMcall_nolink tGPR:$func)]>, 363 Requires<[IsThumb1Only, IsDarwin]>; 364} 365 366let isBranch = 1, isTerminator = 1 in { 367 let isBarrier = 1 in { 368 let isPredicable = 1 in 369 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br, 370 "b\t$target", [(br bb:$target)]>, 371 T1Encoding<{1,1,1,0,0,?}>; 372 373 // Far jump 374 let Defs = [LR] in 375 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br, 376 "bl\t$target\t@ far jump",[]>; 377 378 def tBR_JTr : T1JTI<(outs), 379 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id), 380 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt", 381 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>, 382 Encoding16 { 383 let Inst{15-7} = 0b010001101; 384 let Inst{2-0} = 0b111; 385 } 386 } 387} 388 389// FIXME: should be able to write a pattern for ARMBrcond, but can't use 390// a two-value operand where a dag node expects two operands. :( 391let isBranch = 1, isTerminator = 1 in 392 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br, 393 "b$cc\t$target", 394 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 395 T1Encoding<{1,1,0,1,?,?}>; 396 397// Compare and branch on zero / non-zero 398let isBranch = 1, isTerminator = 1 in { 399 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br, 400 "cbz\t$cmp, $target", []>, 401 T1Misc<{0,0,?,1,?,?,?}>; 402 403 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br, 404 "cbnz\t$cmp, $target", []>, 405 T1Misc<{1,0,?,1,?,?,?}>; 406} 407 408// A8.6.218 Supervisor Call (Software Interrupt) -- for disassembly only 409// A8.6.16 B: Encoding T1 410// If Inst{11-8} == 0b1111 then SEE SVC 411let isCall = 1 in { 412def tSVC : T1pI<(outs), (ins i32imm:$svc), IIC_Br, "svc", "\t$svc", []>, 413 Encoding16 { 414 let Inst{15-12} = 0b1101; 415 let Inst{11-8} = 0b1111; 416} 417} 418 419// A8.6.16 B: Encoding T1 -- for disassembly only 420// If Inst{11-8} == 0b1110 then UNDEFINED 421def tTRAP : T1I<(outs), (ins), IIC_Br, "trap", []>, Encoding16 { 422 let Inst{15-12} = 0b1101; 423 let Inst{11-8} = 0b1110; 424} 425 426//===----------------------------------------------------------------------===// 427// Load Store Instructions. 428// 429 430let canFoldAsLoad = 1, isReMaterializable = 1 in 431def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr, 432 "ldr", "\t$dst, $addr", 433 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>, 434 T1LdSt<0b100>; 435def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr, 436 "ldr", "\t$dst, $addr", 437 []>, 438 T1LdSt4Imm<{1,?,?}>; 439 440def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr, 441 "ldrb", "\t$dst, $addr", 442 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>, 443 T1LdSt<0b110>; 444def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr, 445 "ldrb", "\t$dst, $addr", 446 []>, 447 T1LdSt1Imm<{1,?,?}>; 448 449def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr, 450 "ldrh", "\t$dst, $addr", 451 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>, 452 T1LdSt<0b101>; 453def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr, 454 "ldrh", "\t$dst, $addr", 455 []>, 456 T1LdSt2Imm<{1,?,?}>; 457 458let AddedComplexity = 10 in 459def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr, 460 "ldrsb", "\t$dst, $addr", 461 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>, 462 T1LdSt<0b011>; 463 464let AddedComplexity = 10 in 465def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr, 466 "ldrsh", "\t$dst, $addr", 467 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>, 468 T1LdSt<0b111>; 469 470let canFoldAsLoad = 1 in 471def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi, 472 "ldr", "\t$dst, $addr", 473 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>, 474 T1LdStSP<{1,?,?}>; 475 476// Special instruction for restore. It cannot clobber condition register 477// when it's expanded by eliminateCallFramePseudoInstr(). 478let canFoldAsLoad = 1, mayLoad = 1 in 479def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi, 480 "ldr", "\t$dst, $addr", []>, 481 T1LdStSP<{1,?,?}>; 482 483// Load tconstpool 484// FIXME: Use ldr.n to work around a Darwin assembler bug. 485let canFoldAsLoad = 1, isReMaterializable = 1 in 486def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 487 "ldr", ".n\t$dst, $addr", 488 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>, 489 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59 490 491// Special LDR for loads from non-pc-relative constpools. 492let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1 in 493def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 494 "ldr", "\t$dst, $addr", []>, 495 T1LdStSP<{1,?,?}>; 496 497def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer, 498 "str", "\t$src, $addr", 499 [(store tGPR:$src, t_addrmode_s4:$addr)]>, 500 T1LdSt<0b000>; 501def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer, 502 "str", "\t$src, $addr", 503 []>, 504 T1LdSt4Imm<{0,?,?}>; 505 506def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer, 507 "strb", "\t$src, $addr", 508 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>, 509 T1LdSt<0b010>; 510def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer, 511 "strb", "\t$src, $addr", 512 []>, 513 T1LdSt1Imm<{0,?,?}>; 514 515def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer, 516 "strh", "\t$src, $addr", 517 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>, 518 T1LdSt<0b001>; 519def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer, 520 "strh", "\t$src, $addr", 521 []>, 522 T1LdSt2Imm<{0,?,?}>; 523 524def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei, 525 "str", "\t$src, $addr", 526 [(store tGPR:$src, t_addrmode_sp:$addr)]>, 527 T1LdStSP<{0,?,?}>; 528 529let mayStore = 1 in { 530// Special instruction for spill. It cannot clobber condition register 531// when it's expanded by eliminateCallFramePseudoInstr(). 532def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei, 533 "str", "\t$src, $addr", []>, 534 T1LdStSP<{0,?,?}>; 535} 536 537//===----------------------------------------------------------------------===// 538// Load / store multiple Instructions. 539// 540 541// These requires base address to be written back or one of the loaded regs. 542let mayLoad = 1, hasExtraDefRegAllocReq = 1 in { 543def tLDM : T1I<(outs), 544 (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), 545 IIC_iLoadm, 546 "ldm${addr:submode}${p}\t$addr, $dsts", []>, 547 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53 548 549def tLDM_UPD : T1It<(outs tGPR:$wb), 550 (ins addrmode4:$addr, pred:$p, reglist:$dsts, variable_ops), 551 IIC_iLoadm, 552 "ldm${addr:submode}${p}\t$addr, $dsts", 553 "$addr.addr = $wb", []>, 554 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53 555} // mayLoad, hasExtraDefRegAllocReq 556 557let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 558def tSTM_UPD : T1It<(outs tGPR:$wb), 559 (ins addrmode4:$addr, pred:$p, reglist:$srcs, variable_ops), 560 IIC_iStorem, 561 "stm${addr:submode}${p}\t$addr, $srcs", 562 "$addr.addr = $wb", []>, 563 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189 564 565let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 566def tPOP : T1I<(outs), (ins pred:$p, reglist:$dsts, variable_ops), IIC_Br, 567 "pop${p}\t$dsts", []>, 568 T1Misc<{1,1,0,?,?,?,?}>; 569 570let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 571def tPUSH : T1I<(outs), (ins pred:$p, reglist:$srcs, variable_ops), IIC_Br, 572 "push${p}\t$srcs", []>, 573 T1Misc<{0,1,0,?,?,?,?}>; 574 575//===----------------------------------------------------------------------===// 576// Arithmetic Instructions. 577// 578 579// Add with carry register 580let isCommutable = 1, Uses = [CPSR] in 581def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 582 "adc", "\t$dst, $rhs", 583 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>, 584 T1DataProcessing<0b0101>; 585 586// Add immediate 587def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 588 "add", "\t$dst, $lhs, $rhs", 589 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>, 590 T1General<0b01110>; 591 592def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 593 "add", "\t$dst, $rhs", 594 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>, 595 T1General<{1,1,0,?,?}>; 596 597// Add register 598let isCommutable = 1 in 599def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 600 "add", "\t$dst, $lhs, $rhs", 601 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>, 602 T1General<0b01100>; 603 604let neverHasSideEffects = 1 in 605def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 606 "add", "\t$dst, $rhs", []>, 607 T1Special<{0,0,?,?}>; 608 609// And register 610let isCommutable = 1 in 611def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 612 "and", "\t$dst, $rhs", 613 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>, 614 T1DataProcessing<0b0000>; 615 616// ASR immediate 617def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 618 "asr", "\t$dst, $lhs, $rhs", 619 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>, 620 T1General<{0,1,0,?,?}>; 621 622// ASR register 623def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 624 "asr", "\t$dst, $rhs", 625 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>, 626 T1DataProcessing<0b0100>; 627 628// BIC register 629def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 630 "bic", "\t$dst, $rhs", 631 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>, 632 T1DataProcessing<0b1110>; 633 634// CMN register 635let Defs = [CPSR] in { 636//FIXME: Disable CMN, as CCodes are backwards from compare expectations 637// Compare-to-zero still works out, just not the relationals 638//def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 639// "cmn", "\t$lhs, $rhs", 640// [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>, 641// T1DataProcessing<0b1011>; 642def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 643 "cmn", "\t$lhs, $rhs", 644 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>, 645 T1DataProcessing<0b1011>; 646} 647 648// CMP immediate 649let Defs = [CPSR] in { 650def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi, 651 "cmp", "\t$lhs, $rhs", 652 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>, 653 T1General<{1,0,1,?,?}>; 654def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi, 655 "cmp", "\t$lhs, $rhs", 656 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>, 657 T1General<{1,0,1,?,?}>; 658} 659 660// CMP register 661let Defs = [CPSR] in { 662def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 663 "cmp", "\t$lhs, $rhs", 664 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>, 665 T1DataProcessing<0b1010>; 666def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 667 "cmp", "\t$lhs, $rhs", 668 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>, 669 T1DataProcessing<0b1010>; 670 671def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 672 "cmp", "\t$lhs, $rhs", []>, 673 T1Special<{0,1,?,?}>; 674def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 675 "cmp", "\t$lhs, $rhs", []>, 676 T1Special<{0,1,?,?}>; 677} 678 679 680// XOR register 681let isCommutable = 1 in 682def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 683 "eor", "\t$dst, $rhs", 684 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>, 685 T1DataProcessing<0b0001>; 686 687// LSL immediate 688def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 689 "lsl", "\t$dst, $lhs, $rhs", 690 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>, 691 T1General<{0,0,0,?,?}>; 692 693// LSL register 694def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 695 "lsl", "\t$dst, $rhs", 696 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>, 697 T1DataProcessing<0b0010>; 698 699// LSR immediate 700def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 701 "lsr", "\t$dst, $lhs, $rhs", 702 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>, 703 T1General<{0,0,1,?,?}>; 704 705// LSR register 706def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 707 "lsr", "\t$dst, $rhs", 708 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>, 709 T1DataProcessing<0b0011>; 710 711// move register 712def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi, 713 "mov", "\t$dst, $src", 714 [(set tGPR:$dst, imm0_255:$src)]>, 715 T1General<{1,0,0,?,?}>; 716 717// TODO: A7-73: MOV(2) - mov setting flag. 718 719 720let neverHasSideEffects = 1 in { 721// FIXME: Make this predicable. 722def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 723 "mov\t$dst, $src", []>, 724 T1Special<0b1000>; 725let Defs = [CPSR] in 726def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 727 "movs\t$dst, $src", []>, Encoding16 { 728 let Inst{15-6} = 0b0000000000; 729} 730 731// FIXME: Make these predicable. 732def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr, 733 "mov\t$dst, $src", []>, 734 T1Special<{1,0,0,?}>; 735def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr, 736 "mov\t$dst, $src", []>, 737 T1Special<{1,0,?,0}>; 738def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 739 "mov\t$dst, $src", []>, 740 T1Special<{1,0,?,?}>; 741} // neverHasSideEffects 742 743// multiply register 744let isCommutable = 1 in 745def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32, 746 "mul", "\t$dst, $rhs, $dst", /* A8.6.105 MUL Encoding T1 */ 747 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>, 748 T1DataProcessing<0b1101>; 749 750// move inverse register 751def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 752 "mvn", "\t$dst, $src", 753 [(set tGPR:$dst, (not tGPR:$src))]>, 754 T1DataProcessing<0b1111>; 755 756// bitwise or register 757let isCommutable = 1 in 758def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 759 "orr", "\t$dst, $rhs", 760 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>, 761 T1DataProcessing<0b1100>; 762 763// swaps 764def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 765 "rev", "\t$dst, $src", 766 [(set tGPR:$dst, (bswap tGPR:$src))]>, 767 Requires<[IsThumb1Only, HasV6]>, 768 T1Misc<{1,0,1,0,0,0,?}>; 769 770def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 771 "rev16", "\t$dst, $src", 772 [(set tGPR:$dst, 773 (or (and (srl tGPR:$src, (i32 8)), 0xFF), 774 (or (and (shl tGPR:$src, (i32 8)), 0xFF00), 775 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000), 776 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>, 777 Requires<[IsThumb1Only, HasV6]>, 778 T1Misc<{1,0,1,0,0,1,?}>; 779 780def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 781 "revsh", "\t$dst, $src", 782 [(set tGPR:$dst, 783 (sext_inreg 784 (or (srl (and tGPR:$src, 0xFF00), (i32 8)), 785 (shl tGPR:$src, (i32 8))), i16))]>, 786 Requires<[IsThumb1Only, HasV6]>, 787 T1Misc<{1,0,1,0,1,1,?}>; 788 789// rotate right register 790def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 791 "ror", "\t$dst, $rhs", 792 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>, 793 T1DataProcessing<0b0111>; 794 795// negate register 796def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi, 797 "rsb", "\t$dst, $src, #0", 798 [(set tGPR:$dst, (ineg tGPR:$src))]>, 799 T1DataProcessing<0b1001>; 800 801// Subtract with carry register 802let Uses = [CPSR] in 803def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 804 "sbc", "\t$dst, $rhs", 805 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>, 806 T1DataProcessing<0b0110>; 807 808// Subtract immediate 809def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 810 "sub", "\t$dst, $lhs, $rhs", 811 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>, 812 T1General<0b01111>; 813 814def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 815 "sub", "\t$dst, $rhs", 816 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>, 817 T1General<{1,1,1,?,?}>; 818 819// subtract register 820def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 821 "sub", "\t$dst, $lhs, $rhs", 822 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>, 823 T1General<0b01101>; 824 825// TODO: A7-96: STMIA - store multiple. 826 827// sign-extend byte 828def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 829 "sxtb", "\t$dst, $src", 830 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>, 831 Requires<[IsThumb1Only, HasV6]>, 832 T1Misc<{0,0,1,0,0,1,?}>; 833 834// sign-extend short 835def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 836 "sxth", "\t$dst, $src", 837 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>, 838 Requires<[IsThumb1Only, HasV6]>, 839 T1Misc<{0,0,1,0,0,0,?}>; 840 841// test 842let isCommutable = 1, Defs = [CPSR] in 843def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 844 "tst", "\t$lhs, $rhs", 845 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>, 846 T1DataProcessing<0b1000>; 847 848// zero-extend byte 849def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 850 "uxtb", "\t$dst, $src", 851 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>, 852 Requires<[IsThumb1Only, HasV6]>, 853 T1Misc<{0,0,1,0,1,1,?}>; 854 855// zero-extend short 856def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 857 "uxth", "\t$dst, $src", 858 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>, 859 Requires<[IsThumb1Only, HasV6]>, 860 T1Misc<{0,0,1,0,1,0,?}>; 861 862 863// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC operation. 864// Expanded after instruction selection into a branch sequence. 865let usesCustomInserter = 1 in // Expanded after instruction selection. 866 def tMOVCCr_pseudo : 867 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 868 NoItinerary, "@ tMOVCCr $cc", 869 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 870 871 872// 16-bit movcc in IT blocks for Thumb2. 873def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr, 874 "mov", "\t$dst, $rhs", []>, 875 T1Special<{1,0,?,?}>; 876 877def tMOVCCi : T1pIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMOVi, 878 "mov", "\t$dst, $rhs", []>, 879 T1General<{1,0,0,?,?}>; 880 881// tLEApcrel - Load a pc-relative address into a register without offending the 882// assembler. 883def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, 884 "adr$p\t$dst, #$label", []>, 885 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10 886 887def tLEApcrelJT : T1I<(outs tGPR:$dst), 888 (ins i32imm:$label, nohash_imm:$id, pred:$p), 889 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>, 890 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10 891 892//===----------------------------------------------------------------------===// 893// TLS Instructions 894// 895 896// __aeabi_read_tp preserves the registers r1-r3. 897let isCall = 1, 898 Defs = [R0, LR] in { 899 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br, 900 "bl\t__aeabi_read_tp", 901 [(set R0, ARMthread_pointer)]>; 902} 903 904// SJLJ Exception handling intrinsics 905// eh_sjlj_setjmp() is an instruction sequence to store the return 906// address and save #0 in R0 for the non-longjmp case. 907// Since by its nature we may be coming from some other function to get 908// here, and we're using the stack frame for the containing function to 909// save/restore registers, we can't keep anything live in regs across 910// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 911// when we get here from a longjmp(). We force everthing out of registers 912// except for our own input by listing the relevant registers in Defs. By 913// doing so, we also cause the prologue/epilogue code to actively preserve 914// all of the callee-saved resgisters, which is exactly what we want. 915// The current SP is passed in $val, and we reuse the reg as a scratch. 916let Defs = 917 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ] in { 918 def tInt_eh_sjlj_setjmp : ThumbXI<(outs),(ins tGPR:$src, tGPR:$val), 919 AddrModeNone, SizeSpecial, NoItinerary, 920 "str\t$val, [$src, #8]\t@ begin eh.setjmp\n" 921 "\tmov\t$val, pc\n" 922 "\tadds\t$val, #9\n" 923 "\tstr\t$val, [$src, #4]\n" 924 "\tmovs\tr0, #0\n" 925 "\tb\t1f\n" 926 "\tmovs\tr0, #1\t@ end eh.setjmp\n" 927 "1:", "", 928 [(set R0, (ARMeh_sjlj_setjmp tGPR:$src, tGPR:$val))]>; 929} 930//===----------------------------------------------------------------------===// 931// Non-Instruction Patterns 932// 933 934// Add with carry 935def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 936 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 937def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 938 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 939def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 940 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 941 942// Subtract with carry 943def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 944 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 945def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 946 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 947def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 948 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 949 950// ConstantPool, GlobalAddress 951def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 952def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 953 954// JumpTable 955def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 956 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 957 958// Direct calls 959def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 960 Requires<[IsThumb, IsNotDarwin]>; 961def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>, 962 Requires<[IsThumb, IsDarwin]>; 963 964def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 965 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 966def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>, 967 Requires<[IsThumb, HasV5T, IsDarwin]>; 968 969// Indirect calls to ARM routines 970def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 971 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 972def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>, 973 Requires<[IsThumb, HasV5T, IsDarwin]>; 974 975// zextload i1 -> zextload i8 976def : T1Pat<(zextloadi1 t_addrmode_s1:$addr), 977 (tLDRB t_addrmode_s1:$addr)>; 978 979// extload -> zextload 980def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>; 981def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>; 982def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>; 983 984// If it's impossible to use [r,r] address mode for sextload, select to 985// ldr{b|h} + sxt{b|h} instead. 986def : T1Pat<(sextloadi8 t_addrmode_s1:$addr), 987 (tSXTB (tLDRB t_addrmode_s1:$addr))>, 988 Requires<[IsThumb1Only, HasV6]>; 989def : T1Pat<(sextloadi16 t_addrmode_s2:$addr), 990 (tSXTH (tLDRH t_addrmode_s2:$addr))>, 991 Requires<[IsThumb1Only, HasV6]>; 992 993def : T1Pat<(sextloadi8 t_addrmode_s1:$addr), 994 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>; 995def : T1Pat<(sextloadi16 t_addrmode_s1:$addr), 996 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>; 997 998// Large immediate handling. 999 1000// Two piece imms. 1001def : T1Pat<(i32 thumb_immshifted:$src), 1002 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 1003 (thumb_immshifted_shamt imm:$src))>; 1004 1005def : T1Pat<(i32 imm0_255_comp:$src), 1006 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 1007 1008// Pseudo instruction that combines ldr from constpool and add pc. This should 1009// be expanded into two instructions late to allow if-conversion and 1010// scheduling. 1011let isReMaterializable = 1 in 1012def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 1013 NoItinerary, "@ ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc", 1014 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 1015 imm:$cp))]>, 1016 Requires<[IsThumb1Only]>; 1017