ARMInstrThumb.td revision 202375
1//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 20 21def imm_neg_XFORM : SDNodeXForm<imm, [{ 22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 23}]>; 24def imm_comp_XFORM : SDNodeXForm<imm, [{ 25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 26}]>; 27 28 29/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7]. 30def imm0_7 : PatLeaf<(i32 imm), [{ 31 return (uint32_t)N->getZExtValue() < 8; 32}]>; 33def imm0_7_neg : PatLeaf<(i32 imm), [{ 34 return (uint32_t)-N->getZExtValue() < 8; 35}], imm_neg_XFORM>; 36 37def imm0_255 : PatLeaf<(i32 imm), [{ 38 return (uint32_t)N->getZExtValue() < 256; 39}]>; 40def imm0_255_comp : PatLeaf<(i32 imm), [{ 41 return ~((uint32_t)N->getZExtValue()) < 256; 42}]>; 43 44def imm8_255 : PatLeaf<(i32 imm), [{ 45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256; 46}]>; 47def imm8_255_neg : PatLeaf<(i32 imm), [{ 48 unsigned Val = -N->getZExtValue(); 49 return Val >= 8 && Val < 256; 50}], imm_neg_XFORM>; 51 52// Break imm's up into two pieces: an immediate + a left shift. 53// This uses thumb_immshifted to match and thumb_immshifted_val and 54// thumb_immshifted_shamt to get the val/shift pieces. 55def thumb_immshifted : PatLeaf<(imm), [{ 56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 57}]>; 58 59def thumb_immshifted_val : SDNodeXForm<imm, [{ 60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 61 return CurDAG->getTargetConstant(V, MVT::i32); 62}]>; 63 64def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 66 return CurDAG->getTargetConstant(V, MVT::i32); 67}]>; 68 69// Scaled 4 immediate. 70def t_imm_s4 : Operand<i32> { 71 let PrintMethod = "printThumbS4ImmOperand"; 72} 73 74// Define Thumb specific addressing modes. 75 76// t_addrmode_rr := reg + reg 77// 78def t_addrmode_rr : Operand<i32>, 79 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 80 let PrintMethod = "printThumbAddrModeRROperand"; 81 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 82} 83 84// t_addrmode_s4 := reg + reg 85// reg + imm5 * 4 86// 87def t_addrmode_s4 : Operand<i32>, 88 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> { 89 let PrintMethod = "printThumbAddrModeS4Operand"; 90 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 91} 92 93// t_addrmode_s2 := reg + reg 94// reg + imm5 * 2 95// 96def t_addrmode_s2 : Operand<i32>, 97 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> { 98 let PrintMethod = "printThumbAddrModeS2Operand"; 99 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 100} 101 102// t_addrmode_s1 := reg + reg 103// reg + imm5 104// 105def t_addrmode_s1 : Operand<i32>, 106 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> { 107 let PrintMethod = "printThumbAddrModeS1Operand"; 108 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 109} 110 111// t_addrmode_sp := sp + imm8 * 4 112// 113def t_addrmode_sp : Operand<i32>, 114 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 115 let PrintMethod = "printThumbAddrModeSPOperand"; 116 let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm); 117} 118 119//===----------------------------------------------------------------------===// 120// Miscellaneous Instructions. 121// 122 123let Defs = [SP], Uses = [SP] in { 124def tADJCALLSTACKUP : 125PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 126 "@ tADJCALLSTACKUP $amt1", 127 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>; 128 129def tADJCALLSTACKDOWN : 130PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 131 "@ tADJCALLSTACKDOWN $amt", 132 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>; 133} 134 135// For both thumb1 and thumb2. 136let isNotDuplicable = 1 in 137def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, 138 "\n$cp:\n\tadd\t$dst, pc", 139 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 140 T1Special<{0,0,?,?}> { 141 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc 142} 143 144// PC relative add. 145def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi, 146 "add\t$dst, pc, $rhs", []>, 147 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10 148 149// ADD rd, sp, #imm8 150def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi, 151 "add\t$dst, $sp, $rhs", []>, 152 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8 153 154// ADD sp, sp, #imm7 155def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 156 "add\t$dst, $rhs", []>, 157 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8 158 159// SUB sp, sp, #imm7 160def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 161 "sub\t$dst, $rhs", []>, 162 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215 163 164// ADD rm, sp 165def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 166 "add\t$dst, $rhs", []>, 167 T1Special<{0,0,?,?}> { 168 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1 169} 170 171// ADD sp, rm 172def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 173 "add\t$dst, $rhs", []>, 174 T1Special<{0,0,?,?}> { 175 // A8.6.9 Encoding T2 176 let Inst{7} = 1; 177 let Inst{2-0} = 0b101; 178} 179 180// Pseudo instruction that will expand into a tSUBspi + a copy. 181let usesCustomInserter = 1 in { // Expanded after instruction selection. 182def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), 183 NoItinerary, "@ sub\t$dst, $rhs", []>; 184 185def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 186 NoItinerary, "@ add\t$dst, $rhs", []>; 187 188let Defs = [CPSR] in 189def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), 190 NoItinerary, "@ and\t$dst, $rhs", []>; 191} // usesCustomInserter 192 193//===----------------------------------------------------------------------===// 194// Control Flow Instructions. 195// 196 197let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 198 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>, 199 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25 200 let Inst{6-3} = 0b1110; // Rm = lr 201 } 202 // Alternative return instruction used by vararg functions. 203 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>, 204 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25 205} 206 207// Indirect branches 208let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 209 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst", 210 [(brind GPR:$dst)]>, 211 T1Special<{1,0,1,1}> { 212 // <Rd> = Inst{7:2-0} = pc 213 let Inst{2-0} = 0b111; 214 } 215} 216 217// FIXME: remove when we have a way to marking a MI with these properties. 218let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 219 hasExtraDefRegAllocReq = 1 in 220def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br, 221 "pop${p}\t$wb", []>, 222 T1Misc<{1,1,0,?,?,?,?}>; 223 224let isCall = 1, 225 Defs = [R0, R1, R2, R3, R12, LR, 226 D0, D1, D2, D3, D4, D5, D6, D7, 227 D16, D17, D18, D19, D20, D21, D22, D23, 228 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 229 // Also used for Thumb2 230 def tBL : TIx2<0b11110, 0b11, 1, 231 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 232 "bl\t${func:call}", 233 [(ARMtcall tglobaladdr:$func)]>, 234 Requires<[IsThumb, IsNotDarwin]>; 235 236 // ARMv5T and above, also used for Thumb2 237 def tBLXi : TIx2<0b11110, 0b11, 0, 238 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 239 "blx\t${func:call}", 240 [(ARMcall tglobaladdr:$func)]>, 241 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 242 243 // Also used for Thumb2 244 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, 245 "blx\t$func", 246 [(ARMtcall GPR:$func)]>, 247 Requires<[IsThumb, HasV5T, IsNotDarwin]>, 248 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24; 249 250 // ARMv4T 251 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?, 252 (outs), (ins tGPR:$func, variable_ops), IIC_Br, 253 "mov\tlr, pc\n\tbx\t$func", 254 [(ARMcall_nolink tGPR:$func)]>, 255 Requires<[IsThumb1Only, IsNotDarwin]>; 256} 257 258// On Darwin R9 is call-clobbered. 259let isCall = 1, 260 Defs = [R0, R1, R2, R3, R9, R12, LR, 261 D0, D1, D2, D3, D4, D5, D6, D7, 262 D16, D17, D18, D19, D20, D21, D22, D23, 263 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 264 // Also used for Thumb2 265 def tBLr9 : TIx2<0b11110, 0b11, 1, 266 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 267 "bl\t${func:call}", 268 [(ARMtcall tglobaladdr:$func)]>, 269 Requires<[IsThumb, IsDarwin]>; 270 271 // ARMv5T and above, also used for Thumb2 272 def tBLXi_r9 : TIx2<0b11110, 0b11, 0, 273 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 274 "blx\t${func:call}", 275 [(ARMcall tglobaladdr:$func)]>, 276 Requires<[IsThumb, HasV5T, IsDarwin]>; 277 278 // Also used for Thumb2 279 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, 280 "blx\t$func", 281 [(ARMtcall GPR:$func)]>, 282 Requires<[IsThumb, HasV5T, IsDarwin]>, 283 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24 284 285 // ARMv4T 286 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?, 287 (outs), (ins tGPR:$func, variable_ops), IIC_Br, 288 "mov\tlr, pc\n\tbx\t$func", 289 [(ARMcall_nolink tGPR:$func)]>, 290 Requires<[IsThumb1Only, IsDarwin]>; 291} 292 293let isBranch = 1, isTerminator = 1 in { 294 let isBarrier = 1 in { 295 let isPredicable = 1 in 296 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br, 297 "b\t$target", [(br bb:$target)]>, 298 T1Encoding<{1,1,1,0,0,?}>; 299 300 // Far jump 301 let Defs = [LR] in 302 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br, 303 "bl\t$target\t@ far jump",[]>; 304 305 def tBR_JTr : T1JTI<(outs), 306 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id), 307 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt", 308 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>, 309 Encoding16 { 310 let Inst{15-7} = 0b010001101; 311 let Inst{2-0} = 0b111; 312 } 313 } 314} 315 316// FIXME: should be able to write a pattern for ARMBrcond, but can't use 317// a two-value operand where a dag node expects two operands. :( 318let isBranch = 1, isTerminator = 1 in 319 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br, 320 "b$cc\t$target", 321 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 322 T1Encoding<{1,1,0,1,?,?}>; 323 324// Compare and branch on zero / non-zero 325let isBranch = 1, isTerminator = 1 in { 326 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br, 327 "cbz\t$cmp, $target", []>, 328 T1Misc<{0,0,?,1,?,?,?}>; 329 330 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br, 331 "cbnz\t$cmp, $target", []>, 332 T1Misc<{1,0,?,1,?,?,?}>; 333} 334 335//===----------------------------------------------------------------------===// 336// Load Store Instructions. 337// 338 339let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in 340def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr, 341 "ldr", "\t$dst, $addr", 342 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>, 343 T1LdSt<0b100>; 344def tLDRi: T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr, 345 "ldr", "\t$dst, $addr", 346 []>, 347 T1LdSt4Imm<{1,?,?}>; 348 349def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr, 350 "ldrb", "\t$dst, $addr", 351 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>, 352 T1LdSt<0b110>; 353def tLDRBi: T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr, 354 "ldrb", "\t$dst, $addr", 355 []>, 356 T1LdSt1Imm<{1,?,?}>; 357 358def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr, 359 "ldrh", "\t$dst, $addr", 360 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>, 361 T1LdSt<0b101>; 362def tLDRHi: T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr, 363 "ldrh", "\t$dst, $addr", 364 []>, 365 T1LdSt2Imm<{1,?,?}>; 366 367let AddedComplexity = 10 in 368def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr, 369 "ldrsb", "\t$dst, $addr", 370 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>, 371 T1LdSt<0b011>; 372 373let AddedComplexity = 10 in 374def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr, 375 "ldrsh", "\t$dst, $addr", 376 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>, 377 T1LdSt<0b111>; 378 379let canFoldAsLoad = 1 in 380def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi, 381 "ldr", "\t$dst, $addr", 382 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>, 383 T1LdStSP<{1,?,?}>; 384 385// Special instruction for restore. It cannot clobber condition register 386// when it's expanded by eliminateCallFramePseudoInstr(). 387let canFoldAsLoad = 1, mayLoad = 1 in 388def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi, 389 "ldr", "\t$dst, $addr", []>, 390 T1LdStSP<{1,?,?}>; 391 392// Load tconstpool 393// FIXME: Use ldr.n to work around a Darwin assembler bug. 394let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in 395def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 396 "ldr", ".n\t$dst, $addr", 397 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>, 398 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59 399 400// Special LDR for loads from non-pc-relative constpools. 401let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, 402 mayHaveSideEffects = 1 in 403def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 404 "ldr", "\t$dst, $addr", []>, 405 T1LdStSP<{1,?,?}>; 406 407def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer, 408 "str", "\t$src, $addr", 409 [(store tGPR:$src, t_addrmode_s4:$addr)]>, 410 T1LdSt<0b000>; 411def tSTRi: T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer, 412 "str", "\t$src, $addr", 413 []>, 414 T1LdSt4Imm<{0,?,?}>; 415 416def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer, 417 "strb", "\t$src, $addr", 418 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>, 419 T1LdSt<0b010>; 420def tSTRBi: T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer, 421 "strb", "\t$src, $addr", 422 []>, 423 T1LdSt1Imm<{0,?,?}>; 424 425def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer, 426 "strh", "\t$src, $addr", 427 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>, 428 T1LdSt<0b001>; 429def tSTRHi: T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer, 430 "strh", "\t$src, $addr", 431 []>, 432 T1LdSt2Imm<{0,?,?}>; 433 434def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei, 435 "str", "\t$src, $addr", 436 [(store tGPR:$src, t_addrmode_sp:$addr)]>, 437 T1LdStSP<{0,?,?}>; 438 439let mayStore = 1 in { 440// Special instruction for spill. It cannot clobber condition register 441// when it's expanded by eliminateCallFramePseudoInstr(). 442def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei, 443 "str", "\t$src, $addr", []>, 444 T1LdStSP<{0,?,?}>; 445} 446 447//===----------------------------------------------------------------------===// 448// Load / store multiple Instructions. 449// 450 451// These requires base address to be written back or one of the loaded regs. 452let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 453def tLDM : T1I<(outs), 454 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 455 IIC_iLoadm, 456 "ldm${addr:submode}${p}\t$addr, $wb", []>, 457 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53 458 459let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 460def tSTM : T1I<(outs), 461 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 462 IIC_iStorem, 463 "stm${addr:submode}${p}\t$addr, $wb", []>, 464 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189 465 466let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 467def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br, 468 "pop${p}\t$wb", []>, 469 T1Misc<{1,1,0,?,?,?,?}>; 470 471let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 472def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br, 473 "push${p}\t$wb", []>, 474 T1Misc<{0,1,0,?,?,?,?}>; 475 476//===----------------------------------------------------------------------===// 477// Arithmetic Instructions. 478// 479 480// Add with carry register 481let isCommutable = 1, Uses = [CPSR] in 482def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 483 "adc", "\t$dst, $rhs", 484 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>, 485 T1DataProcessing<0b0101>; 486 487// Add immediate 488def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 489 "add", "\t$dst, $lhs, $rhs", 490 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>, 491 T1General<0b01110>; 492 493def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 494 "add", "\t$dst, $rhs", 495 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>, 496 T1General<{1,1,0,?,?}>; 497 498// Add register 499let isCommutable = 1 in 500def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 501 "add", "\t$dst, $lhs, $rhs", 502 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>, 503 T1General<0b01100>; 504 505let neverHasSideEffects = 1 in 506def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 507 "add", "\t$dst, $rhs", []>, 508 T1Special<{0,0,?,?}>; 509 510// And register 511let isCommutable = 1 in 512def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 513 "and", "\t$dst, $rhs", 514 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>, 515 T1DataProcessing<0b0000>; 516 517// ASR immediate 518def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 519 "asr", "\t$dst, $lhs, $rhs", 520 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>, 521 T1General<{0,1,0,?,?}>; 522 523// ASR register 524def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 525 "asr", "\t$dst, $rhs", 526 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>, 527 T1DataProcessing<0b0100>; 528 529// BIC register 530def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 531 "bic", "\t$dst, $rhs", 532 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>, 533 T1DataProcessing<0b1110>; 534 535// CMN register 536let Defs = [CPSR] in { 537def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 538 "cmn", "\t$lhs, $rhs", 539 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>, 540 T1DataProcessing<0b1011>; 541def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 542 "cmn", "\t$lhs, $rhs", 543 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>, 544 T1DataProcessing<0b1011>; 545} 546 547// CMP immediate 548let Defs = [CPSR] in { 549def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi, 550 "cmp", "\t$lhs, $rhs", 551 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>, 552 T1General<{1,0,1,?,?}>; 553def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi, 554 "cmp", "\t$lhs, $rhs", 555 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>, 556 T1General<{1,0,1,?,?}>; 557} 558 559// CMP register 560let Defs = [CPSR] in { 561def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 562 "cmp", "\t$lhs, $rhs", 563 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>, 564 T1DataProcessing<0b1010>; 565def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 566 "cmp", "\t$lhs, $rhs", 567 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>, 568 T1DataProcessing<0b1010>; 569 570def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 571 "cmp", "\t$lhs, $rhs", []>, 572 T1Special<{0,1,?,?}>; 573def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 574 "cmp", "\t$lhs, $rhs", []>, 575 T1Special<{0,1,?,?}>; 576} 577 578 579// XOR register 580let isCommutable = 1 in 581def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 582 "eor", "\t$dst, $rhs", 583 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>, 584 T1DataProcessing<0b0001>; 585 586// LSL immediate 587def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 588 "lsl", "\t$dst, $lhs, $rhs", 589 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>, 590 T1General<{0,0,0,?,?}>; 591 592// LSL register 593def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 594 "lsl", "\t$dst, $rhs", 595 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>, 596 T1DataProcessing<0b0010>; 597 598// LSR immediate 599def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 600 "lsr", "\t$dst, $lhs, $rhs", 601 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>, 602 T1General<{0,0,1,?,?}>; 603 604// LSR register 605def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 606 "lsr", "\t$dst, $rhs", 607 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>, 608 T1DataProcessing<0b0011>; 609 610// move register 611def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi, 612 "mov", "\t$dst, $src", 613 [(set tGPR:$dst, imm0_255:$src)]>, 614 T1General<{1,0,0,?,?}>; 615 616// TODO: A7-73: MOV(2) - mov setting flag. 617 618 619let neverHasSideEffects = 1 in { 620// FIXME: Make this predicable. 621def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 622 "mov\t$dst, $src", []>, 623 T1Special<0b1000>; 624let Defs = [CPSR] in 625def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 626 "movs\t$dst, $src", []>, Encoding16 { 627 let Inst{15-6} = 0b0000000000; 628} 629 630// FIXME: Make these predicable. 631def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr, 632 "mov\t$dst, $src", []>, 633 T1Special<{1,0,0,1}>; 634def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr, 635 "mov\t$dst, $src", []>, 636 T1Special<{1,0,1,0}>; 637def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 638 "mov\t$dst, $src", []>, 639 T1Special<{1,0,1,1}>; 640} // neverHasSideEffects 641 642// multiply register 643let isCommutable = 1 in 644def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32, 645 "mul", "\t$dst, $rhs", 646 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>, 647 T1DataProcessing<0b1101>; 648 649// move inverse register 650def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 651 "mvn", "\t$dst, $src", 652 [(set tGPR:$dst, (not tGPR:$src))]>, 653 T1DataProcessing<0b1111>; 654 655// bitwise or register 656let isCommutable = 1 in 657def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 658 "orr", "\t$dst, $rhs", 659 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>, 660 T1DataProcessing<0b1100>; 661 662// swaps 663def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 664 "rev", "\t$dst, $src", 665 [(set tGPR:$dst, (bswap tGPR:$src))]>, 666 Requires<[IsThumb1Only, HasV6]>, 667 T1Misc<{1,0,1,0,0,0,?}>; 668 669def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 670 "rev16", "\t$dst, $src", 671 [(set tGPR:$dst, 672 (or (and (srl tGPR:$src, (i32 8)), 0xFF), 673 (or (and (shl tGPR:$src, (i32 8)), 0xFF00), 674 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000), 675 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>, 676 Requires<[IsThumb1Only, HasV6]>, 677 T1Misc<{1,0,1,0,0,1,?}>; 678 679def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 680 "revsh", "\t$dst, $src", 681 [(set tGPR:$dst, 682 (sext_inreg 683 (or (srl (and tGPR:$src, 0xFF00), (i32 8)), 684 (shl tGPR:$src, (i32 8))), i16))]>, 685 Requires<[IsThumb1Only, HasV6]>, 686 T1Misc<{1,0,1,0,1,1,?}>; 687 688// rotate right register 689def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 690 "ror", "\t$dst, $rhs", 691 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>, 692 T1DataProcessing<0b0111>; 693 694// negate register 695def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi, 696 "rsb", "\t$dst, $src, #0", 697 [(set tGPR:$dst, (ineg tGPR:$src))]>, 698 T1DataProcessing<0b1001>; 699 700// Subtract with carry register 701let Uses = [CPSR] in 702def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 703 "sbc", "\t$dst, $rhs", 704 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>, 705 T1DataProcessing<0b0110>; 706 707// Subtract immediate 708def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 709 "sub", "\t$dst, $lhs, $rhs", 710 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>, 711 T1General<0b01111>; 712 713def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 714 "sub", "\t$dst, $rhs", 715 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>, 716 T1General<{1,1,1,?,?}>; 717 718// subtract register 719def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 720 "sub", "\t$dst, $lhs, $rhs", 721 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>, 722 T1General<0b01101>; 723 724// TODO: A7-96: STMIA - store multiple. 725 726// sign-extend byte 727def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 728 "sxtb", "\t$dst, $src", 729 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>, 730 Requires<[IsThumb1Only, HasV6]>, 731 T1Misc<{0,0,1,0,0,1,?}>; 732 733// sign-extend short 734def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 735 "sxth", "\t$dst, $src", 736 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>, 737 Requires<[IsThumb1Only, HasV6]>, 738 T1Misc<{0,0,1,0,0,0,?}>; 739 740// test 741let isCommutable = 1, Defs = [CPSR] in 742def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 743 "tst", "\t$lhs, $rhs", 744 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>, 745 T1DataProcessing<0b1000>; 746 747// zero-extend byte 748def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 749 "uxtb", "\t$dst, $src", 750 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>, 751 Requires<[IsThumb1Only, HasV6]>, 752 T1Misc<{0,0,1,0,1,1,?}>; 753 754// zero-extend short 755def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 756 "uxth", "\t$dst, $src", 757 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>, 758 Requires<[IsThumb1Only, HasV6]>, 759 T1Misc<{0,0,1,0,1,0,?}>; 760 761 762// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation. 763// Expanded after instruction selection into a branch sequence. 764let usesCustomInserter = 1 in // Expanded after instruction selection. 765 def tMOVCCr_pseudo : 766 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 767 NoItinerary, "@ tMOVCCr $cc", 768 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 769 770 771// 16-bit movcc in IT blocks for Thumb2. 772def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr, 773 "mov", "\t$dst, $rhs", []>, 774 T1Special<{1,0,1,1}>; 775 776def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iCMOVi, 777 "mov", "\t$dst, $rhs", []>, 778 T1General<{1,0,0,?,?}>; 779 780// tLEApcrel - Load a pc-relative address into a register without offending the 781// assembler. 782def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, 783 "adr$p\t$dst, #$label", []>, 784 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10 785 786def tLEApcrelJT : T1I<(outs tGPR:$dst), 787 (ins i32imm:$label, nohash_imm:$id, pred:$p), 788 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>, 789 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10 790 791//===----------------------------------------------------------------------===// 792// TLS Instructions 793// 794 795// __aeabi_read_tp preserves the registers r1-r3. 796let isCall = 1, 797 Defs = [R0, LR] in { 798 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br, 799 "bl\t__aeabi_read_tp", 800 [(set R0, ARMthread_pointer)]>; 801} 802 803// SJLJ Exception handling intrinsics 804// eh_sjlj_setjmp() is an instruction sequence to store the return 805// address and save #0 in R0 for the non-longjmp case. 806// Since by its nature we may be coming from some other function to get 807// here, and we're using the stack frame for the containing function to 808// save/restore registers, we can't keep anything live in regs across 809// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 810// when we get here from a longjmp(). We force everthing out of registers 811// except for our own input by listing the relevant registers in Defs. By 812// doing so, we also cause the prologue/epilogue code to actively preserve 813// all of the callee-saved resgisters, which is exactly what we want. 814let Defs = 815 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ] in { 816 def tInt_eh_sjlj_setjmp : ThumbXI<(outs), (ins GPR:$src), 817 AddrModeNone, SizeSpecial, NoItinerary, 818 "mov\tr12, r1\t@ begin eh.setjmp\n" 819 "\tmov\tr1, sp\n" 820 "\tstr\tr1, [$src, #8]\n" 821 "\tadr\tr1, 0f\n" 822 "\tadds\tr1, #1\n" 823 "\tstr\tr1, [$src, #4]\n" 824 "\tmov\tr1, r12\n" 825 "\tmovs\tr0, #0\n" 826 "\tb\t1f\n" 827 ".align 2\n" 828 "0:\tmovs\tr0, #1\t@ end eh.setjmp\n" 829 "1:", "", 830 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>; 831} 832//===----------------------------------------------------------------------===// 833// Non-Instruction Patterns 834// 835 836// Add with carry 837def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 838 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 839def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 840 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 841def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 842 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 843 844// Subtract with carry 845def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 846 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 847def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 848 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 849def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 850 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 851 852// ConstantPool, GlobalAddress 853def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 854def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 855 856// JumpTable 857def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 858 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 859 860// Direct calls 861def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 862 Requires<[IsThumb, IsNotDarwin]>; 863def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>, 864 Requires<[IsThumb, IsDarwin]>; 865 866def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 867 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 868def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>, 869 Requires<[IsThumb, HasV5T, IsDarwin]>; 870 871// Indirect calls to ARM routines 872def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 873 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 874def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>, 875 Requires<[IsThumb, HasV5T, IsDarwin]>; 876 877// zextload i1 -> zextload i8 878def : T1Pat<(zextloadi1 t_addrmode_s1:$addr), 879 (tLDRB t_addrmode_s1:$addr)>; 880 881// extload -> zextload 882def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>; 883def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>; 884def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>; 885 886// If it's impossible to use [r,r] address mode for sextload, select to 887// ldr{b|h} + sxt{b|h} instead. 888def : T1Pat<(sextloadi8 t_addrmode_s1:$addr), 889 (tSXTB (tLDRB t_addrmode_s1:$addr))>, 890 Requires<[IsThumb1Only, HasV6]>; 891def : T1Pat<(sextloadi16 t_addrmode_s2:$addr), 892 (tSXTH (tLDRH t_addrmode_s2:$addr))>, 893 Requires<[IsThumb1Only, HasV6]>; 894 895def : T1Pat<(sextloadi8 t_addrmode_s1:$addr), 896 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>; 897def : T1Pat<(sextloadi16 t_addrmode_s1:$addr), 898 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>; 899 900// Large immediate handling. 901 902// Two piece imms. 903def : T1Pat<(i32 thumb_immshifted:$src), 904 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 905 (thumb_immshifted_shamt imm:$src))>; 906 907def : T1Pat<(i32 imm0_255_comp:$src), 908 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 909 910// Pseudo instruction that combines ldr from constpool and add pc. This should 911// be expanded into two instructions late to allow if-conversion and 912// scheduling. 913let isReMaterializable = 1 in 914def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 915 NoItinerary, "@ ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc", 916 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 917 imm:$cp))]>, 918 Requires<[IsThumb1Only]>; 919