ARMInstrThumb.td revision 201360
1//===- ARMInstrThumb.td - Thumb support for ARM ---------------------------===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the Thumb instruction set. 11// 12//===----------------------------------------------------------------------===// 13 14//===----------------------------------------------------------------------===// 15// Thumb specific DAG Nodes. 16// 17 18def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall, 19 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>; 20 21def imm_neg_XFORM : SDNodeXForm<imm, [{ 22 return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32); 23}]>; 24def imm_comp_XFORM : SDNodeXForm<imm, [{ 25 return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32); 26}]>; 27 28 29/// imm0_7 predicate - True if the 32-bit immediate is in the range [0,7]. 30def imm0_7 : PatLeaf<(i32 imm), [{ 31 return (uint32_t)N->getZExtValue() < 8; 32}]>; 33def imm0_7_neg : PatLeaf<(i32 imm), [{ 34 return (uint32_t)-N->getZExtValue() < 8; 35}], imm_neg_XFORM>; 36 37def imm0_255 : PatLeaf<(i32 imm), [{ 38 return (uint32_t)N->getZExtValue() < 256; 39}]>; 40def imm0_255_comp : PatLeaf<(i32 imm), [{ 41 return ~((uint32_t)N->getZExtValue()) < 256; 42}]>; 43 44def imm8_255 : PatLeaf<(i32 imm), [{ 45 return (uint32_t)N->getZExtValue() >= 8 && (uint32_t)N->getZExtValue() < 256; 46}]>; 47def imm8_255_neg : PatLeaf<(i32 imm), [{ 48 unsigned Val = -N->getZExtValue(); 49 return Val >= 8 && Val < 256; 50}], imm_neg_XFORM>; 51 52// Break imm's up into two pieces: an immediate + a left shift. 53// This uses thumb_immshifted to match and thumb_immshifted_val and 54// thumb_immshifted_shamt to get the val/shift pieces. 55def thumb_immshifted : PatLeaf<(imm), [{ 56 return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue()); 57}]>; 58 59def thumb_immshifted_val : SDNodeXForm<imm, [{ 60 unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue()); 61 return CurDAG->getTargetConstant(V, MVT::i32); 62}]>; 63 64def thumb_immshifted_shamt : SDNodeXForm<imm, [{ 65 unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue()); 66 return CurDAG->getTargetConstant(V, MVT::i32); 67}]>; 68 69// Scaled 4 immediate. 70def t_imm_s4 : Operand<i32> { 71 let PrintMethod = "printThumbS4ImmOperand"; 72} 73 74// Define Thumb specific addressing modes. 75 76// t_addrmode_rr := reg + reg 77// 78def t_addrmode_rr : Operand<i32>, 79 ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> { 80 let PrintMethod = "printThumbAddrModeRROperand"; 81 let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg); 82} 83 84// t_addrmode_s4 := reg + reg 85// reg + imm5 * 4 86// 87def t_addrmode_s4 : Operand<i32>, 88 ComplexPattern<i32, 3, "SelectThumbAddrModeS4", []> { 89 let PrintMethod = "printThumbAddrModeS4Operand"; 90 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 91} 92 93// t_addrmode_s2 := reg + reg 94// reg + imm5 * 2 95// 96def t_addrmode_s2 : Operand<i32>, 97 ComplexPattern<i32, 3, "SelectThumbAddrModeS2", []> { 98 let PrintMethod = "printThumbAddrModeS2Operand"; 99 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 100} 101 102// t_addrmode_s1 := reg + reg 103// reg + imm5 104// 105def t_addrmode_s1 : Operand<i32>, 106 ComplexPattern<i32, 3, "SelectThumbAddrModeS1", []> { 107 let PrintMethod = "printThumbAddrModeS1Operand"; 108 let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm, tGPR:$offsreg); 109} 110 111// t_addrmode_sp := sp + imm8 * 4 112// 113def t_addrmode_sp : Operand<i32>, 114 ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> { 115 let PrintMethod = "printThumbAddrModeSPOperand"; 116 let MIOperandInfo = (ops JustSP:$base, i32imm:$offsimm); 117} 118 119//===----------------------------------------------------------------------===// 120// Miscellaneous Instructions. 121// 122 123let Defs = [SP], Uses = [SP] in { 124def tADJCALLSTACKUP : 125PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary, 126 "@ tADJCALLSTACKUP $amt1", 127 [(ARMcallseq_end imm:$amt1, imm:$amt2)]>, Requires<[IsThumb1Only]>; 128 129def tADJCALLSTACKDOWN : 130PseudoInst<(outs), (ins i32imm:$amt), NoItinerary, 131 "@ tADJCALLSTACKDOWN $amt", 132 [(ARMcallseq_start imm:$amt)]>, Requires<[IsThumb1Only]>; 133} 134 135// For both thumb1 and thumb2. 136let isNotDuplicable = 1 in 137def tPICADD : TIt<(outs GPR:$dst), (ins GPR:$lhs, pclabel:$cp), IIC_iALUr, 138 "\n$cp:\n\tadd\t$dst, pc", 139 [(set GPR:$dst, (ARMpic_add GPR:$lhs, imm:$cp))]>, 140 T1Special<{0,0,?,?}> { 141 let Inst{6-3} = 0b1111; // A8.6.6 Rm = pc 142} 143 144// PC relative add. 145def tADDrPCi : T1I<(outs tGPR:$dst), (ins t_imm_s4:$rhs), IIC_iALUi, 146 "add\t$dst, pc, $rhs", []>, 147 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10 148 149// ADD rd, sp, #imm8 150def tADDrSPi : T1I<(outs tGPR:$dst), (ins GPR:$sp, t_imm_s4:$rhs), IIC_iALUi, 151 "add\t$dst, $sp, $rhs", []>, 152 T1Encoding<{1,0,1,0,1,?}>; // A6.2 & A8.6.8 153 154// ADD sp, sp, #imm7 155def tADDspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 156 "add\t$dst, $rhs", []>, 157 T1Misc<{0,0,0,0,0,?,?}>; // A6.2.5 & A8.6.8 158 159// SUB sp, sp, #imm7 160def tSUBspi : TIt<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), IIC_iALUi, 161 "sub\t$dst, $rhs", []>, 162 T1Misc<{0,0,0,0,1,?,?}>; // A6.2.5 & A8.6.215 163 164// ADD rm, sp 165def tADDrSP : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 166 "add\t$dst, $rhs", []>, 167 T1Special<{0,0,?,?}> { 168 let Inst{6-3} = 0b1101; // A8.6.9 Encoding T1 169} 170 171// ADD sp, rm 172def tADDspr : TIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 173 "add\t$dst, $rhs", []>, 174 T1Special<{0,0,?,?}> { 175 // A8.6.9 Encoding T2 176 let Inst{7} = 1; 177 let Inst{2-0} = 0b101; 178} 179 180// Pseudo instruction that will expand into a tSUBspi + a copy. 181let usesCustomInserter = 1 in { // Expanded after instruction selection. 182def tSUBspi_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, t_imm_s4:$rhs), 183 NoItinerary, "@ sub\t$dst, $rhs", []>; 184 185def tADDspr_ : PseudoInst<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), 186 NoItinerary, "@ add\t$dst, $rhs", []>; 187 188let Defs = [CPSR] in 189def tANDsp : PseudoInst<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), 190 NoItinerary, "@ and\t$dst, $rhs", []>; 191} // usesCustomInserter 192 193//===----------------------------------------------------------------------===// 194// Control Flow Instructions. 195// 196 197let isReturn = 1, isTerminator = 1, isBarrier = 1 in { 198 def tBX_RET : TI<(outs), (ins), IIC_Br, "bx\tlr", [(ARMretflag)]>, 199 T1Special<{1,1,0,?}> { // A6.2.3 & A8.6.25 200 let Inst{6-3} = 0b1110; // Rm = lr 201 } 202 // Alternative return instruction used by vararg functions. 203 def tBX_RET_vararg : TI<(outs), (ins tGPR:$target), IIC_Br, "bx\t$target", []>, 204 T1Special<{1,1,0,?}>; // A6.2.3 & A8.6.25 205} 206 207// Indirect branches 208let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in { 209 def tBRIND : TI<(outs), (ins GPR:$dst), IIC_Br, "mov\tpc, $dst", 210 [(brind GPR:$dst)]>, 211 T1Special<{1,0,?,?}> { 212 // <Rd> = pc 213 let Inst{7} = 1; 214 let Inst{2-0} = 0b111; 215 } 216} 217 218// FIXME: remove when we have a way to marking a MI with these properties. 219let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, 220 hasExtraDefRegAllocReq = 1 in 221def tPOP_RET : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br, 222 "pop${p}\t$wb", []>, 223 T1Misc<{1,1,0,?,?,?,?}>; 224 225let isCall = 1, 226 Defs = [R0, R1, R2, R3, R12, LR, 227 D0, D1, D2, D3, D4, D5, D6, D7, 228 D16, D17, D18, D19, D20, D21, D22, D23, 229 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 230 // Also used for Thumb2 231 def tBL : TIx2<0b11110, 0b11, 1, 232 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 233 "bl\t${func:call}", 234 [(ARMtcall tglobaladdr:$func)]>, 235 Requires<[IsThumb, IsNotDarwin]>; 236 237 // ARMv5T and above, also used for Thumb2 238 def tBLXi : TIx2<0b11110, 0b11, 0, 239 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 240 "blx\t${func:call}", 241 [(ARMcall tglobaladdr:$func)]>, 242 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 243 244 // Also used for Thumb2 245 def tBLXr : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, 246 "blx\t$func", 247 [(ARMtcall GPR:$func)]>, 248 Requires<[IsThumb, HasV5T, IsNotDarwin]>, 249 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24; 250 251 // ARMv4T 252 def tBX : TIx2<{?,?,?,?,?}, {?,?}, ?, 253 (outs), (ins tGPR:$func, variable_ops), IIC_Br, 254 "mov\tlr, pc\n\tbx\t$func", 255 [(ARMcall_nolink tGPR:$func)]>, 256 Requires<[IsThumb1Only, IsNotDarwin]>; 257} 258 259// On Darwin R9 is call-clobbered. 260let isCall = 1, 261 Defs = [R0, R1, R2, R3, R9, R12, LR, 262 D0, D1, D2, D3, D4, D5, D6, D7, 263 D16, D17, D18, D19, D20, D21, D22, D23, 264 D24, D25, D26, D27, D28, D29, D30, D31, CPSR, FPSCR] in { 265 // Also used for Thumb2 266 def tBLr9 : TIx2<0b11110, 0b11, 1, 267 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 268 "bl\t${func:call}", 269 [(ARMtcall tglobaladdr:$func)]>, 270 Requires<[IsThumb, IsDarwin]>; 271 272 // ARMv5T and above, also used for Thumb2 273 def tBLXi_r9 : TIx2<0b11110, 0b11, 0, 274 (outs), (ins i32imm:$func, variable_ops), IIC_Br, 275 "blx\t${func:call}", 276 [(ARMcall tglobaladdr:$func)]>, 277 Requires<[IsThumb, HasV5T, IsDarwin]>; 278 279 // Also used for Thumb2 280 def tBLXr_r9 : TI<(outs), (ins GPR:$func, variable_ops), IIC_Br, 281 "blx\t$func", 282 [(ARMtcall GPR:$func)]>, 283 Requires<[IsThumb, HasV5T, IsDarwin]>, 284 T1Special<{1,1,1,?}>; // A6.2.3 & A8.6.24 285 286 // ARMv4T 287 def tBXr9 : TIx2<{?,?,?,?,?}, {?,?}, ?, 288 (outs), (ins tGPR:$func, variable_ops), IIC_Br, 289 "mov\tlr, pc\n\tbx\t$func", 290 [(ARMcall_nolink tGPR:$func)]>, 291 Requires<[IsThumb1Only, IsDarwin]>; 292} 293 294let isBranch = 1, isTerminator = 1 in { 295 let isBarrier = 1 in { 296 let isPredicable = 1 in 297 def tB : T1I<(outs), (ins brtarget:$target), IIC_Br, 298 "b\t$target", [(br bb:$target)]>, 299 T1Encoding<{1,1,1,0,0,?}>; 300 301 // Far jump 302 let Defs = [LR] in 303 def tBfar : TIx2<0b11110, 0b11, 1, (outs), (ins brtarget:$target), IIC_Br, 304 "bl\t$target\t@ far jump",[]>; 305 306 def tBR_JTr : T1JTI<(outs), 307 (ins tGPR:$target, jtblock_operand:$jt, i32imm:$id), 308 IIC_Br, "mov\tpc, $target\n\t.align\t2\n$jt", 309 [(ARMbrjt tGPR:$target, tjumptable:$jt, imm:$id)]>, 310 Encoding16 { 311 let Inst{15-7} = 0b010001101; 312 let Inst{2-0} = 0b111; 313 } 314 } 315} 316 317// FIXME: should be able to write a pattern for ARMBrcond, but can't use 318// a two-value operand where a dag node expects two operands. :( 319let isBranch = 1, isTerminator = 1 in 320 def tBcc : T1I<(outs), (ins brtarget:$target, pred:$cc), IIC_Br, 321 "b$cc\t$target", 322 [/*(ARMbrcond bb:$target, imm:$cc)*/]>, 323 T1Encoding<{1,1,0,1,?,?}>; 324 325// Compare and branch on zero / non-zero 326let isBranch = 1, isTerminator = 1 in { 327 def tCBZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br, 328 "cbz\t$cmp, $target", []>, 329 T1Misc<{0,0,?,1,?,?,?}>; 330 331 def tCBNZ : T1I<(outs), (ins tGPR:$cmp, brtarget:$target), IIC_Br, 332 "cbnz\t$cmp, $target", []>, 333 T1Misc<{1,0,?,1,?,?,?}>; 334} 335 336//===----------------------------------------------------------------------===// 337// Load Store Instructions. 338// 339 340let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in 341def tLDR : T1pI4<(outs tGPR:$dst), (ins t_addrmode_s4:$addr), IIC_iLoadr, 342 "ldr", "\t$dst, $addr", 343 [(set tGPR:$dst, (load t_addrmode_s4:$addr))]>, 344 T1LdSt<0b100>; 345 346def tLDRB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_s1:$addr), IIC_iLoadr, 347 "ldrb", "\t$dst, $addr", 348 [(set tGPR:$dst, (zextloadi8 t_addrmode_s1:$addr))]>, 349 T1LdSt<0b110>; 350 351def tLDRH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_s2:$addr), IIC_iLoadr, 352 "ldrh", "\t$dst, $addr", 353 [(set tGPR:$dst, (zextloadi16 t_addrmode_s2:$addr))]>, 354 T1LdSt<0b101>; 355 356let AddedComplexity = 10 in 357def tLDRSB : T1pI1<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr, 358 "ldrsb", "\t$dst, $addr", 359 [(set tGPR:$dst, (sextloadi8 t_addrmode_rr:$addr))]>, 360 T1LdSt<0b011>; 361 362let AddedComplexity = 10 in 363def tLDRSH : T1pI2<(outs tGPR:$dst), (ins t_addrmode_rr:$addr), IIC_iLoadr, 364 "ldrsh", "\t$dst, $addr", 365 [(set tGPR:$dst, (sextloadi16 t_addrmode_rr:$addr))]>, 366 T1LdSt<0b111>; 367 368let canFoldAsLoad = 1 in 369def tLDRspi : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi, 370 "ldr", "\t$dst, $addr", 371 [(set tGPR:$dst, (load t_addrmode_sp:$addr))]>, 372 T1LdStSP<{1,?,?}>; 373 374// Special instruction for restore. It cannot clobber condition register 375// when it's expanded by eliminateCallFramePseudoInstr(). 376let canFoldAsLoad = 1, mayLoad = 1 in 377def tRestore : T1pIs<(outs tGPR:$dst), (ins t_addrmode_sp:$addr), IIC_iLoadi, 378 "ldr", "\t$dst, $addr", []>, 379 T1LdStSP<{1,?,?}>; 380 381// Load tconstpool 382// FIXME: Use ldr.n to work around a Darwin assembler bug. 383let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in 384def tLDRpci : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 385 "ldr", ".n\t$dst, $addr", 386 [(set tGPR:$dst, (load (ARMWrapper tconstpool:$addr)))]>, 387 T1Encoding<{0,1,0,0,1,?}>; // A6.2 & A8.6.59 388 389// Special LDR for loads from non-pc-relative constpools. 390let canFoldAsLoad = 1, mayLoad = 1, isReMaterializable = 1, 391 mayHaveSideEffects = 1 in 392def tLDRcp : T1pIs<(outs tGPR:$dst), (ins i32imm:$addr), IIC_iLoadi, 393 "ldr", "\t$dst, $addr", []>, 394 T1LdStSP<{1,?,?}>; 395 396def tSTR : T1pI4<(outs), (ins tGPR:$src, t_addrmode_s4:$addr), IIC_iStorer, 397 "str", "\t$src, $addr", 398 [(store tGPR:$src, t_addrmode_s4:$addr)]>, 399 T1LdSt<0b000>; 400 401def tSTRB : T1pI1<(outs), (ins tGPR:$src, t_addrmode_s1:$addr), IIC_iStorer, 402 "strb", "\t$src, $addr", 403 [(truncstorei8 tGPR:$src, t_addrmode_s1:$addr)]>, 404 T1LdSt<0b010>; 405 406def tSTRH : T1pI2<(outs), (ins tGPR:$src, t_addrmode_s2:$addr), IIC_iStorer, 407 "strh", "\t$src, $addr", 408 [(truncstorei16 tGPR:$src, t_addrmode_s2:$addr)]>, 409 T1LdSt<0b001>; 410 411def tSTRspi : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei, 412 "str", "\t$src, $addr", 413 [(store tGPR:$src, t_addrmode_sp:$addr)]>, 414 T1LdStSP<{0,?,?}>; 415 416let mayStore = 1 in { 417// Special instruction for spill. It cannot clobber condition register 418// when it's expanded by eliminateCallFramePseudoInstr(). 419def tSpill : T1pIs<(outs), (ins tGPR:$src, t_addrmode_sp:$addr), IIC_iStorei, 420 "str", "\t$src, $addr", []>, 421 T1LdStSP<{0,?,?}>; 422} 423 424//===----------------------------------------------------------------------===// 425// Load / store multiple Instructions. 426// 427 428// These requires base address to be written back or one of the loaded regs. 429let mayLoad = 1, hasExtraDefRegAllocReq = 1 in 430def tLDM : T1I<(outs), 431 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 432 IIC_iLoadm, 433 "ldm${addr:submode}${p}\t$addr, $wb", []>, 434 T1Encoding<{1,1,0,0,1,?}>; // A6.2 & A8.6.53 435 436let mayStore = 1, hasExtraSrcRegAllocReq = 1 in 437def tSTM : T1I<(outs), 438 (ins addrmode4:$addr, pred:$p, reglist:$wb, variable_ops), 439 IIC_iStorem, 440 "stm${addr:submode}${p}\t$addr, $wb", []>, 441 T1Encoding<{1,1,0,0,0,?}>; // A6.2 & A8.6.189 442 443let mayLoad = 1, Uses = [SP], Defs = [SP], hasExtraDefRegAllocReq = 1 in 444def tPOP : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br, 445 "pop${p}\t$wb", []>, 446 T1Misc<{1,1,0,?,?,?,?}>; 447 448let mayStore = 1, Uses = [SP], Defs = [SP], hasExtraSrcRegAllocReq = 1 in 449def tPUSH : T1I<(outs), (ins pred:$p, reglist:$wb, variable_ops), IIC_Br, 450 "push${p}\t$wb", []>, 451 T1Misc<{0,1,0,?,?,?,?}>; 452 453//===----------------------------------------------------------------------===// 454// Arithmetic Instructions. 455// 456 457// Add with carry register 458let isCommutable = 1, Uses = [CPSR] in 459def tADC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 460 "adc", "\t$dst, $rhs", 461 [(set tGPR:$dst, (adde tGPR:$lhs, tGPR:$rhs))]>, 462 T1DataProcessing<0b0101>; 463 464// Add immediate 465def tADDi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 466 "add", "\t$dst, $lhs, $rhs", 467 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7:$rhs))]>, 468 T1General<0b01110>; 469 470def tADDi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 471 "add", "\t$dst, $rhs", 472 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255:$rhs))]>, 473 T1General<{1,1,0,?,?}>; 474 475// Add register 476let isCommutable = 1 in 477def tADDrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 478 "add", "\t$dst, $lhs, $rhs", 479 [(set tGPR:$dst, (add tGPR:$lhs, tGPR:$rhs))]>, 480 T1General<0b01100>; 481 482let neverHasSideEffects = 1 in 483def tADDhirr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iALUr, 484 "add", "\t$dst, $rhs", []>, 485 T1Special<{0,0,?,?}>; 486 487// And register 488let isCommutable = 1 in 489def tAND : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 490 "and", "\t$dst, $rhs", 491 [(set tGPR:$dst, (and tGPR:$lhs, tGPR:$rhs))]>, 492 T1DataProcessing<0b0000>; 493 494// ASR immediate 495def tASRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 496 "asr", "\t$dst, $lhs, $rhs", 497 [(set tGPR:$dst, (sra tGPR:$lhs, (i32 imm:$rhs)))]>, 498 T1General<{0,1,0,?,?}>; 499 500// ASR register 501def tASRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 502 "asr", "\t$dst, $rhs", 503 [(set tGPR:$dst, (sra tGPR:$lhs, tGPR:$rhs))]>, 504 T1DataProcessing<0b0100>; 505 506// BIC register 507def tBIC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 508 "bic", "\t$dst, $rhs", 509 [(set tGPR:$dst, (and tGPR:$lhs, (not tGPR:$rhs)))]>, 510 T1DataProcessing<0b1110>; 511 512// CMN register 513let Defs = [CPSR] in { 514def tCMN : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 515 "cmn", "\t$lhs, $rhs", 516 [(ARMcmp tGPR:$lhs, (ineg tGPR:$rhs))]>, 517 T1DataProcessing<0b1011>; 518def tCMNz : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 519 "cmn", "\t$lhs, $rhs", 520 [(ARMcmpZ tGPR:$lhs, (ineg tGPR:$rhs))]>, 521 T1DataProcessing<0b1011>; 522} 523 524// CMP immediate 525let Defs = [CPSR] in { 526def tCMPi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi, 527 "cmp", "\t$lhs, $rhs", 528 [(ARMcmp tGPR:$lhs, imm0_255:$rhs)]>, 529 T1General<{1,0,1,?,?}>; 530def tCMPzi8 : T1pI<(outs), (ins tGPR:$lhs, i32imm:$rhs), IIC_iCMPi, 531 "cmp", "\t$lhs, $rhs", 532 [(ARMcmpZ tGPR:$lhs, imm0_255:$rhs)]>, 533 T1General<{1,0,1,?,?}>; 534} 535 536// CMP register 537let Defs = [CPSR] in { 538def tCMPr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 539 "cmp", "\t$lhs, $rhs", 540 [(ARMcmp tGPR:$lhs, tGPR:$rhs)]>, 541 T1DataProcessing<0b1010>; 542def tCMPzr : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 543 "cmp", "\t$lhs, $rhs", 544 [(ARMcmpZ tGPR:$lhs, tGPR:$rhs)]>, 545 T1DataProcessing<0b1010>; 546 547def tCMPhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 548 "cmp", "\t$lhs, $rhs", []>, 549 T1Special<{0,1,?,?}>; 550def tCMPzhir : T1pI<(outs), (ins GPR:$lhs, GPR:$rhs), IIC_iCMPr, 551 "cmp", "\t$lhs, $rhs", []>, 552 T1Special<{0,1,?,?}>; 553} 554 555 556// XOR register 557let isCommutable = 1 in 558def tEOR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 559 "eor", "\t$dst, $rhs", 560 [(set tGPR:$dst, (xor tGPR:$lhs, tGPR:$rhs))]>, 561 T1DataProcessing<0b0001>; 562 563// LSL immediate 564def tLSLri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 565 "lsl", "\t$dst, $lhs, $rhs", 566 [(set tGPR:$dst, (shl tGPR:$lhs, (i32 imm:$rhs)))]>, 567 T1General<{0,0,0,?,?}>; 568 569// LSL register 570def tLSLrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 571 "lsl", "\t$dst, $rhs", 572 [(set tGPR:$dst, (shl tGPR:$lhs, tGPR:$rhs))]>, 573 T1DataProcessing<0b0010>; 574 575// LSR immediate 576def tLSRri : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iMOVsi, 577 "lsr", "\t$dst, $lhs, $rhs", 578 [(set tGPR:$dst, (srl tGPR:$lhs, (i32 imm:$rhs)))]>, 579 T1General<{0,0,1,?,?}>; 580 581// LSR register 582def tLSRrr : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 583 "lsr", "\t$dst, $rhs", 584 [(set tGPR:$dst, (srl tGPR:$lhs, tGPR:$rhs))]>, 585 T1DataProcessing<0b0011>; 586 587// move register 588def tMOVi8 : T1sI<(outs tGPR:$dst), (ins i32imm:$src), IIC_iMOVi, 589 "mov", "\t$dst, $src", 590 [(set tGPR:$dst, imm0_255:$src)]>, 591 T1General<{1,0,0,?,?}>; 592 593// TODO: A7-73: MOV(2) - mov setting flag. 594 595 596let neverHasSideEffects = 1 in { 597// FIXME: Make this predicable. 598def tMOVr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 599 "mov\t$dst, $src", []>, 600 T1Special<0b1000>; 601let Defs = [CPSR] in 602def tMOVSr : T1I<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 603 "movs\t$dst, $src", []>, Encoding16 { 604 let Inst{15-6} = 0b0000000000; 605} 606 607// FIXME: Make these predicable. 608def tMOVgpr2tgpr : T1I<(outs tGPR:$dst), (ins GPR:$src), IIC_iMOVr, 609 "mov\t$dst, $src", []>, 610 T1Special<{1,0,0,1}>; 611def tMOVtgpr2gpr : T1I<(outs GPR:$dst), (ins tGPR:$src), IIC_iMOVr, 612 "mov\t$dst, $src", []>, 613 T1Special<{1,0,1,0}>; 614def tMOVgpr2gpr : T1I<(outs GPR:$dst), (ins GPR:$src), IIC_iMOVr, 615 "mov\t$dst, $src", []>, 616 T1Special<{1,0,1,1}>; 617} // neverHasSideEffects 618 619// multiply register 620let isCommutable = 1 in 621def tMUL : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMUL32, 622 "mul", "\t$dst, $rhs", 623 [(set tGPR:$dst, (mul tGPR:$lhs, tGPR:$rhs))]>, 624 T1DataProcessing<0b1101>; 625 626// move inverse register 627def tMVN : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iMOVr, 628 "mvn", "\t$dst, $src", 629 [(set tGPR:$dst, (not tGPR:$src))]>, 630 T1DataProcessing<0b1111>; 631 632// bitwise or register 633let isCommutable = 1 in 634def tORR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 635 "orr", "\t$dst, $rhs", 636 [(set tGPR:$dst, (or tGPR:$lhs, tGPR:$rhs))]>, 637 T1DataProcessing<0b1100>; 638 639// swaps 640def tREV : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 641 "rev", "\t$dst, $src", 642 [(set tGPR:$dst, (bswap tGPR:$src))]>, 643 Requires<[IsThumb1Only, HasV6]>, 644 T1Misc<{1,0,1,0,0,0,?}>; 645 646def tREV16 : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 647 "rev16", "\t$dst, $src", 648 [(set tGPR:$dst, 649 (or (and (srl tGPR:$src, (i32 8)), 0xFF), 650 (or (and (shl tGPR:$src, (i32 8)), 0xFF00), 651 (or (and (srl tGPR:$src, (i32 8)), 0xFF0000), 652 (and (shl tGPR:$src, (i32 8)), 0xFF000000)))))]>, 653 Requires<[IsThumb1Only, HasV6]>, 654 T1Misc<{1,0,1,0,0,1,?}>; 655 656def tREVSH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 657 "revsh", "\t$dst, $src", 658 [(set tGPR:$dst, 659 (sext_inreg 660 (or (srl (and tGPR:$src, 0xFF00), (i32 8)), 661 (shl tGPR:$src, (i32 8))), i16))]>, 662 Requires<[IsThumb1Only, HasV6]>, 663 T1Misc<{1,0,1,0,1,1,?}>; 664 665// rotate right register 666def tROR : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iMOVsr, 667 "ror", "\t$dst, $rhs", 668 [(set tGPR:$dst, (rotr tGPR:$lhs, tGPR:$rhs))]>, 669 T1DataProcessing<0b0111>; 670 671// negate register 672def tRSB : T1sI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iALUi, 673 "rsb", "\t$dst, $src, #0", 674 [(set tGPR:$dst, (ineg tGPR:$src))]>, 675 T1DataProcessing<0b1001>; 676 677// Subtract with carry register 678let Uses = [CPSR] in 679def tSBC : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 680 "sbc", "\t$dst, $rhs", 681 [(set tGPR:$dst, (sube tGPR:$lhs, tGPR:$rhs))]>, 682 T1DataProcessing<0b0110>; 683 684// Subtract immediate 685def tSUBi3 : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 686 "sub", "\t$dst, $lhs, $rhs", 687 [(set tGPR:$dst, (add tGPR:$lhs, imm0_7_neg:$rhs))]>, 688 T1General<0b01111>; 689 690def tSUBi8 : T1sIt<(outs tGPR:$dst), (ins tGPR:$lhs, i32imm:$rhs), IIC_iALUi, 691 "sub", "\t$dst, $rhs", 692 [(set tGPR:$dst, (add tGPR:$lhs, imm8_255_neg:$rhs))]>, 693 T1General<{1,1,1,?,?}>; 694 695// subtract register 696def tSUBrr : T1sI<(outs tGPR:$dst), (ins tGPR:$lhs, tGPR:$rhs), IIC_iALUr, 697 "sub", "\t$dst, $lhs, $rhs", 698 [(set tGPR:$dst, (sub tGPR:$lhs, tGPR:$rhs))]>, 699 T1General<0b01101>; 700 701// TODO: A7-96: STMIA - store multiple. 702 703// sign-extend byte 704def tSXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 705 "sxtb", "\t$dst, $src", 706 [(set tGPR:$dst, (sext_inreg tGPR:$src, i8))]>, 707 Requires<[IsThumb1Only, HasV6]>, 708 T1Misc<{0,0,1,0,0,1,?}>; 709 710// sign-extend short 711def tSXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 712 "sxth", "\t$dst, $src", 713 [(set tGPR:$dst, (sext_inreg tGPR:$src, i16))]>, 714 Requires<[IsThumb1Only, HasV6]>, 715 T1Misc<{0,0,1,0,0,0,?}>; 716 717// test 718let isCommutable = 1, Defs = [CPSR] in 719def tTST : T1pI<(outs), (ins tGPR:$lhs, tGPR:$rhs), IIC_iCMPr, 720 "tst", "\t$lhs, $rhs", 721 [(ARMcmpZ (and tGPR:$lhs, tGPR:$rhs), 0)]>, 722 T1DataProcessing<0b1000>; 723 724// zero-extend byte 725def tUXTB : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 726 "uxtb", "\t$dst, $src", 727 [(set tGPR:$dst, (and tGPR:$src, 0xFF))]>, 728 Requires<[IsThumb1Only, HasV6]>, 729 T1Misc<{0,0,1,0,1,1,?}>; 730 731// zero-extend short 732def tUXTH : T1pI<(outs tGPR:$dst), (ins tGPR:$src), IIC_iUNAr, 733 "uxth", "\t$dst, $src", 734 [(set tGPR:$dst, (and tGPR:$src, 0xFFFF))]>, 735 Requires<[IsThumb1Only, HasV6]>, 736 T1Misc<{0,0,1,0,1,0,?}>; 737 738 739// Conditional move tMOVCCr - Used to implement the Thumb SELECT_CC DAG operation. 740// Expanded after instruction selection into a branch sequence. 741let usesCustomInserter = 1 in // Expanded after instruction selection. 742 def tMOVCCr_pseudo : 743 PseudoInst<(outs tGPR:$dst), (ins tGPR:$false, tGPR:$true, pred:$cc), 744 NoItinerary, "@ tMOVCCr $cc", 745 [/*(set tGPR:$dst, (ARMcmov tGPR:$false, tGPR:$true, imm:$cc))*/]>; 746 747 748// 16-bit movcc in IT blocks for Thumb2. 749def tMOVCCr : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, GPR:$rhs), IIC_iCMOVr, 750 "mov", "\t$dst, $rhs", []>, 751 T1Special<{1,0,?,?}>; 752 753def tMOVCCi : T1pIt<(outs GPR:$dst), (ins GPR:$lhs, i32imm:$rhs), IIC_iCMOVi, 754 "mov", "\t$dst, $rhs", []>, 755 T1General<{1,0,0,?,?}>; 756 757// tLEApcrel - Load a pc-relative address into a register without offending the 758// assembler. 759def tLEApcrel : T1I<(outs tGPR:$dst), (ins i32imm:$label, pred:$p), IIC_iALUi, 760 "adr$p\t$dst, #$label", []>, 761 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10 762 763def tLEApcrelJT : T1I<(outs tGPR:$dst), 764 (ins i32imm:$label, nohash_imm:$id, pred:$p), 765 IIC_iALUi, "adr$p\t$dst, #${label}_${id}", []>, 766 T1Encoding<{1,0,1,0,0,?}>; // A6.2 & A8.6.10 767 768//===----------------------------------------------------------------------===// 769// TLS Instructions 770// 771 772// __aeabi_read_tp preserves the registers r1-r3. 773let isCall = 1, 774 Defs = [R0, LR] in { 775 def tTPsoft : TIx2<0b11110, 0b11, 1, (outs), (ins), IIC_Br, 776 "bl\t__aeabi_read_tp", 777 [(set R0, ARMthread_pointer)]>; 778} 779 780// SJLJ Exception handling intrinsics 781// eh_sjlj_setjmp() is an instruction sequence to store the return 782// address and save #0 in R0 for the non-longjmp case. 783// Since by its nature we may be coming from some other function to get 784// here, and we're using the stack frame for the containing function to 785// save/restore registers, we can't keep anything live in regs across 786// the eh_sjlj_setjmp(), else it will almost certainly have been tromped upon 787// when we get here from a longjmp(). We force everthing out of registers 788// except for our own input by listing the relevant registers in Defs. By 789// doing so, we also cause the prologue/epilogue code to actively preserve 790// all of the callee-saved resgisters, which is exactly what we want. 791let Defs = 792 [ R0, R1, R2, R3, R4, R5, R6, R7, R12 ] in { 793 def tInt_eh_sjlj_setjmp : ThumbXI<(outs), (ins GPR:$src), 794 AddrModeNone, SizeSpecial, NoItinerary, 795 "mov\tr12, r1\t@ begin eh.setjmp\n" 796 "\tmov\tr1, sp\n" 797 "\tstr\tr1, [$src, #8]\n" 798 "\tadr\tr1, 0f\n" 799 "\tadds\tr1, #1\n" 800 "\tstr\tr1, [$src, #4]\n" 801 "\tmov\tr1, r12\n" 802 "\tmovs\tr0, #0\n" 803 "\tb\t1f\n" 804 ".align 2\n" 805 "0:\tmovs\tr0, #1\t@ end eh.setjmp\n" 806 "1:", "", 807 [(set R0, (ARMeh_sjlj_setjmp GPR:$src))]>; 808} 809//===----------------------------------------------------------------------===// 810// Non-Instruction Patterns 811// 812 813// Add with carry 814def : T1Pat<(addc tGPR:$lhs, imm0_7:$rhs), 815 (tADDi3 tGPR:$lhs, imm0_7:$rhs)>; 816def : T1Pat<(addc tGPR:$lhs, imm8_255:$rhs), 817 (tADDi8 tGPR:$lhs, imm8_255:$rhs)>; 818def : T1Pat<(addc tGPR:$lhs, tGPR:$rhs), 819 (tADDrr tGPR:$lhs, tGPR:$rhs)>; 820 821// Subtract with carry 822def : T1Pat<(addc tGPR:$lhs, imm0_7_neg:$rhs), 823 (tSUBi3 tGPR:$lhs, imm0_7_neg:$rhs)>; 824def : T1Pat<(addc tGPR:$lhs, imm8_255_neg:$rhs), 825 (tSUBi8 tGPR:$lhs, imm8_255_neg:$rhs)>; 826def : T1Pat<(subc tGPR:$lhs, tGPR:$rhs), 827 (tSUBrr tGPR:$lhs, tGPR:$rhs)>; 828 829// ConstantPool, GlobalAddress 830def : T1Pat<(ARMWrapper tglobaladdr :$dst), (tLEApcrel tglobaladdr :$dst)>; 831def : T1Pat<(ARMWrapper tconstpool :$dst), (tLEApcrel tconstpool :$dst)>; 832 833// JumpTable 834def : T1Pat<(ARMWrapperJT tjumptable:$dst, imm:$id), 835 (tLEApcrelJT tjumptable:$dst, imm:$id)>; 836 837// Direct calls 838def : T1Pat<(ARMtcall texternalsym:$func), (tBL texternalsym:$func)>, 839 Requires<[IsThumb, IsNotDarwin]>; 840def : T1Pat<(ARMtcall texternalsym:$func), (tBLr9 texternalsym:$func)>, 841 Requires<[IsThumb, IsDarwin]>; 842 843def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi texternalsym:$func)>, 844 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 845def : Tv5Pat<(ARMcall texternalsym:$func), (tBLXi_r9 texternalsym:$func)>, 846 Requires<[IsThumb, HasV5T, IsDarwin]>; 847 848// Indirect calls to ARM routines 849def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr GPR:$dst)>, 850 Requires<[IsThumb, HasV5T, IsNotDarwin]>; 851def : Tv5Pat<(ARMcall GPR:$dst), (tBLXr_r9 GPR:$dst)>, 852 Requires<[IsThumb, HasV5T, IsDarwin]>; 853 854// zextload i1 -> zextload i8 855def : T1Pat<(zextloadi1 t_addrmode_s1:$addr), 856 (tLDRB t_addrmode_s1:$addr)>; 857 858// extload -> zextload 859def : T1Pat<(extloadi1 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>; 860def : T1Pat<(extloadi8 t_addrmode_s1:$addr), (tLDRB t_addrmode_s1:$addr)>; 861def : T1Pat<(extloadi16 t_addrmode_s2:$addr), (tLDRH t_addrmode_s2:$addr)>; 862 863// If it's impossible to use [r,r] address mode for sextload, select to 864// ldr{b|h} + sxt{b|h} instead. 865def : T1Pat<(sextloadi8 t_addrmode_s1:$addr), 866 (tSXTB (tLDRB t_addrmode_s1:$addr))>, 867 Requires<[IsThumb1Only, HasV6]>; 868def : T1Pat<(sextloadi16 t_addrmode_s2:$addr), 869 (tSXTH (tLDRH t_addrmode_s2:$addr))>, 870 Requires<[IsThumb1Only, HasV6]>; 871 872def : T1Pat<(sextloadi8 t_addrmode_s1:$addr), 873 (tASRri (tLSLri (tLDRB t_addrmode_s1:$addr), 24), 24)>; 874def : T1Pat<(sextloadi16 t_addrmode_s1:$addr), 875 (tASRri (tLSLri (tLDRH t_addrmode_s1:$addr), 16), 16)>; 876 877// Large immediate handling. 878 879// Two piece imms. 880def : T1Pat<(i32 thumb_immshifted:$src), 881 (tLSLri (tMOVi8 (thumb_immshifted_val imm:$src)), 882 (thumb_immshifted_shamt imm:$src))>; 883 884def : T1Pat<(i32 imm0_255_comp:$src), 885 (tMVN (tMOVi8 (imm_comp_XFORM imm:$src)))>; 886 887// Pseudo instruction that combines ldr from constpool and add pc. This should 888// be expanded into two instructions late to allow if-conversion and 889// scheduling. 890let isReMaterializable = 1 in 891def tLDRpci_pic : PseudoInst<(outs GPR:$dst), (ins i32imm:$addr, pclabel:$cp), 892 NoItinerary, "@ ldr.n\t$dst, $addr\n$cp:\n\tadd\t$dst, pc", 893 [(set GPR:$dst, (ARMpic_add (load (ARMWrapper tconstpool:$addr)), 894 imm:$cp))]>, 895 Requires<[IsThumb1Only]>; 896